Power supply circuit with reverse output circuit and anti-misplug protection circuit

Abstract

The utility model discloses a power supply circuit with a reverse output circuit and an anti-misplug protection circuit. The power supply circuit comprises the reverse output circuit and the anti-misplug protection circuit. The reverse output circuit comprises a conversion chip and a protocol chip, and the conversion chip can convert a DP signal into a mipi csi camera input signal supported by the SOC chip of the tablet computer, so that the SOC chip of the tablet computer supports a DPIN function; the protocol chip is provided with a communication pin CC, and after the protocol chip is connected with the equipment supporting DP output, communication is established through the communication pin CC and the equipment supporting DP output. The power supply circuit provided by the utility model is provided with the reverse output circuit, and the reverse output circuit can enable the tablet SOC to support DPIN input and reversely charge other equipment. The power supply circuit is provided with the anti-misplug protection circuit, and the anti-misplug protection circuit prevents irreversible damage to the mainboard after misplug.

Description

Technical Field

[0001] The utility model relates to a power supply protection circuit, in particular to a power supply circuit with a reverse output circuit and an anti-misinsertion protection circuit. Background Art

[0002] For existing Android devices, the Type-C DP OUT port and the device are voltage output rather than power receiver, or cannot be used as a voltage output to charge DP OUT devices when DPIN input is in progress. It cannot be used as both DP IN and voltage output at the same time. When the TYPE-C is mistakenly plugged into a large power source, the motherboard may be damaged by the high voltage.

[0003] In view of this, it is necessary to improve the power supply circuit connected via type-c in the prior art. Utility Model Content

[0004] In response to the deficiencies in the existing technology, the technical problem to be solved by the present invention is to provide a power supply circuit with a reverse output circuit and an anti-misinsertion protection circuit. The purpose of designing this protection circuit is: first, to design the existing power supply circuit into a power supply side and a power receiving side, and second, to provide an anti-misinsertion protection circuit to protect the motherboard.

[0005] In order to solve the above technical problems, the present invention is implemented through the following solutions: The present invention provides a power supply circuit with a reverse output circuit and an anti-misinsertion protection circuit, comprising a reverse output circuit and an anti-misinsertion protection circuit;

[0006] The reverse output circuit includes:

[0007] A conversion chip with a DP to mipi csi circuit structure, which can convert the DP signal into a mipi csi camera input signal supported by the tablet computer SOC chip, so that the tablet computer SOC chip supports the DP1 function;

[0008] A protocol chip capable of activating the DP output of an input device and charging the device. The protocol chip is provided with a communication pin CC. After the protocol chip establishes a connection with a device that supports DP output, it establishes communication with the device through the communication pin CC;

[0009] The anti-misinsertion protection circuit includes:

[0010] A first MOS transistor U9007, wherein a resistor R1 is connected between the drain D of the first MOS transistor U9007 and the 28-pin VIN of the protocol chip, and the gate G of the first MOS transistor U9007 is connected to the 25-pin GATE / GPIO20 of the protocol chip;

[0011] a second MOS transistor U9008, wherein a gate G of the second MOS transistor U9008 is connected to a gate G of the first MOS transistor U9007, a source S of the second MOS transistor U9008 is connected to a source S of the first MOS transistor U9007, a drain D of the second MOS transistor U9008 is connected to a first end of a capacitor C7, and a second end of the capacitor C7 is grounded;

[0012] a surge tube DU9 , wherein a first end of the surge tube DU9 is grounded, and a second end and a third end thereof are both connected to the drain D of the second MOS tube U9008 ;

[0013] a polarized capacitor C9006, wherein the positive electrode of the polarized capacitor C9006 is connected to the second end of the surge tube DU9, and the negative electrode thereof is grounded;

[0014] a capacitor C9005, wherein a first end of the capacitor C9005 is connected to the positive electrode of the polarized capacitor C9006, and a second end of the capacitor C9005 is grounded;

[0015] Resistor R9209, a first end of the resistor R9209 is connected to the positive electrode of the polarized capacitor C9006, and a second end of the resistor R9209 is grounded.

[0016] Furthermore, the conversion chip is a LT7911D chip, and the protocol chip is a SW2505H chip.

[0017] Furthermore, both ends of the resistor R1 are respectively connected to pin 27 CSPH and pin 26 CSNH of the protocol chip.

[0018] Pin 5 VD3V3 of the protocol chip is connected to the first end of capacitor C3, pin 4 VDD1V5 of the protocol chip is connected to the first end of capacitor C4, pin 3 VCC5V of the protocol chip is connected to the first end of capacitor C4, the second ends of capacitor C3, capacitor C4, and capacitor C5 are connected to each other and then grounded and connected to the first end of capacitor C1, and the second end of capacitor C1 is connected to the 5V input port of the power interface;

[0019] The second end of the capacitor C1 is also connected to the 28-pin VIN of the protocol chip;

[0020] The FB port of the power interface is connected to the 7-pin VD / FB / GPIO14 of the protocol chip;

[0021] The OPTO port of the power interface is respectively connected to the OPTO / RFB / GPIO19 pin 1 of the protocol chip, the first end of the resistor R2, the first end of the resistor R3, and the first end of the resistor 4. The second end of the resistor R2 is grounded and connected to the first end of the capacitor C8. The second end of the capacitor C8 is connected to the IFB / GPIO16 pin 6 of the protocol chip. The second end of the resistor R3 is connected to the first end of the capacitor C2. The second end of the capacitor C2 is connected to the IFB / GPIO16 pin 6 of the protocol chip. The second end of the resistor R4 is connected to the first end of the capacitor C6. The second end of the capacitor C6 is connected to the VFB / GPIO19 pin 2 of the protocol chip.

[0022] Furthermore, the 22nd pin CC1 / ID / GPIO10 of the protocol chip is connected to the first end of the ESD diode D9203, and the second end of the ESD diode D9203 is grounded;

[0023] Pin 23 CC2 / GPIO11 of the protocol chip is connected to a first end of an ESD diode D9204, and a second end of the ESD diode D9204 is grounded.

[0024] Compared with the prior art, the beneficial effects of the present invention are:

[0025] 1. The power supply circuit of the utility model has a reverse output circuit, which enables the tablet SOC to support DPIN input and reverse charge other devices.

[0026] 2. The power supply circuit of the present invention has an anti-misinsertion protection circuit, which prevents irreversible damage to the mainboard after misinsertion. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a principle block diagram of the power supply circuit of this utility model.

[0028] Figure 2-Figure 5 After the circuits are connected, the overall circuit diagram of the power supply circuit of the utility model is formed.

[0029] Figure 6 This is the circuit diagram of the TYPE C interface of the utility model. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more specific definition of the scope of protection of the present invention. Obviously, the embodiments described in the present invention are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0031] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0032] Example 1: The specific structure of the utility model is as follows:

[0033] Please refer to the attached Figure 1-6 , the utility model is a power supply circuit with a reverse output circuit and an anti-misinsertion protection circuit, including a reverse output circuit and an anti-misinsertion protection circuit;

[0034] The reverse output circuit includes a conversion chip with a DP to mipi csi circuit structure and a protocol chip that can realize the DP output of the activated input device and the device charging function.

[0035] The conversion chip is an LT7911D model chip. This conversion chip can convert the DP signal into the MIPI CSI camera input signal supported by the tablet computer SOC chip, thereby enabling the tablet computer SOC chip to support the DPIN function. In the prior art, the typical tablet computer SOC does not support the DPIN function. Therefore, the utility model uses the LT7911D DP to MIPI CSI conversion chip to convert the DP signal into the MIPI CSI camera input signal supported by the tablet SOC chip, thereby enabling the tablet SOC product to support the DPIN function. Because the CC pin of the LT7911D conversion chip can only simply activate the DP function and cannot activate the DP output of the input device or the device charging function, it is necessary to add a customized CC protocol chip SW2505H to activate the DP output of the input device and the device charging function.

[0036] The protocol chip adopts the SW2505H model chip. The protocol chip is provided with a communication pin CC, such as Figure 2 As shown, the communication pin CC is the 19-pin GPIO0 / ADC of the protocol chip. After the protocol chip establishes a connection with a device that supports DP output, the DP output device of the utility model adopts a tablet computer, and communication is established with the device that supports DP output through the communication pin CC.

[0037] The following is the principle of the reverse charging function of the reverse output circuit:

[0038] Use dual C lines to connect to a device that supports DP output (mobile phone or tablet), and the other end to the TYPE C (DPIN input port) of this circuit device. Through the dual C lines, the CC pins of the two devices communicate. The CC of this utility model device is connected to the CC pin of the protocol chip SW2505H, and then the protocol chip SW2505H will communicate with the output device, such as Figure 2-5 As shown:

[0039] 1. Pin 19 EN of the protocol chip SW2505H: distinguish between the front and back sides, the front side gives a high level, the back side gives a low level, and is given to pin 14 of the conversion chip LT7911D.

[0040] 2. The TYPE C port is a source port, which only discharges to the outside but does not charge the inside.

[0041] 3. When a load is inserted into the TYPE C port, pin 19 of the protocol chip SW2505H gives a signal, broadcasting the DP mode, informing the load that video transmission is possible, and opening the path MOS of the charging circuit. Pin 18 of the protocol chip SW2505H generates a pull-down 15ms reset signal to the conversion chip LT7911D, and the conversion chip LT7911D starts conversion work. At this time, the device activates the DP output of the input device and the device charging function.

[0042] The anti-misinsertion protection circuit includes:

[0043] A first MOS transistor U9007, which is an NMOS transistor. A resistor R1 is connected between the drain D of the first MOS transistor U9007 and the 28-pin VIN of the protocol chip. The gate G of the first MOS transistor U9007 is connected to the 25-pin GATE / GPIO20 of the protocol chip.

[0044] a second MOS transistor U9008, which is an NMOS transistor. A gate G of the second MOS transistor U9008 is connected to the gate G of the first MOS transistor U9007, a source S of the second MOS transistor U9008 is connected to the source S of the first MOS transistor U9007, a drain D of the second MOS transistor U9008 is connected to a first end of a capacitor C7, and a second end of the capacitor C7 is grounded;

[0045] a surge tube DU9 , wherein a first end of the surge tube DU9 is grounded, and a second end and a third end thereof are both connected to the drain D of the second MOS tube U9008 ;

[0046] a polarized capacitor C9006, wherein the positive electrode of the polarized capacitor C9006 is connected to the second end of the surge tube DU9, and the negative electrode thereof is grounded;

[0047] a capacitor C9005, wherein a first end of the capacitor C9005 is connected to the positive electrode of the polarized capacitor C9006, and a second end of the capacitor C9005 is grounded;

[0048] Resistor R9209, a first end of the resistor R9209 is connected to the positive electrode of the polarized capacitor C9006, and a second end of the resistor R9209 is grounded.

[0049] The two ends of the resistor R1 are also connected to the 27th pin CSPH and the 26th pin CSNH of the protocol chip respectively.

[0050] Pin 5 VD3V3 of the protocol chip is connected to the first end of capacitor C3, pin 4 VDD1V5 of the protocol chip is connected to the first end of capacitor C4, pin 3 VCC5V of the protocol chip is connected to the first end of capacitor C4, the second ends of capacitor C3, capacitor C4, and capacitor C5 are connected to each other and then grounded and connected to the first end of capacitor C1, and the second end of capacitor C1 is connected to the 5V input port of the power interface;

[0051] The second end of the capacitor C1 is also connected to the 28-pin VIN of the protocol chip;

[0052] The FB port of the power interface is connected to the 7-pin VD / FB / GPIO14 of the protocol chip;

[0053] The OPTO port of the power interface is respectively connected to the OPTO / RFB / GPIO19 pin 1 of the protocol chip, the first end of the resistor R2, the first end of the resistor R3, and the first end of the resistor 4. The second end of the resistor R2 is grounded and connected to the first end of the capacitor C8. The second end of the capacitor C8 is connected to the IFB / GPIO16 pin 6 of the protocol chip. The second end of the resistor R3 is connected to the first end of the capacitor C2. The second end of the capacitor C2 is connected to the IFB / GPIO16 pin 6 of the protocol chip. The second end of the resistor R4 is connected to the first end of the capacitor C6. The second end of the capacitor C6 is connected to the VFB / GPIO19 pin 2 of the protocol chip.

[0054] Pin 22 CC1 / ID / GPIO10 of the protocol chip is connected to a first end of an ESD diode D9203, and a second end of the ESD diode D9203 is grounded;

[0055] Pin 23 CC2 / GPIO11 of the protocol chip is connected to a first end of an ESD diode D9204, and a second end of the ESD diode D9204 is grounded.

[0056] The following is the working principle of the anti-misinsertion protection circuit: The VBUS pin of the Type-C port is connected to a 24V surge diode DU9. Since the power supply's CC cannot communicate with the protocol chip SW2505H, pin 25 of the protocol chip SW2505H controls the switching of an NMOS transistor (AO4402-MS). This protection circuit exploits the characteristics of the protocol chip and the NMOS transistor. The drain D and source S of the NMOS transistor cannot directly pass current, while the source S and drain D can directly pass overvoltage and current, but with a voltage drop. Therefore, the first MOS transistor U9007 and the second MOS transistor U9008 are reversed and disconnected using pin 25 of the protocol chip SW2505H. This ensures that the NMOS transistor turns on to provide external power only after the protocol chip SW2505H completes its protocol. If a power supply is inserted before the protocol is completed, the NMOS transistor turns off, and the surge diode DU9 absorbs the surge voltage, providing dual protection. This protects the Type-C (DPIN) port from being accidentally connected to a high-voltage power supply and damaging the motherboard due to the high voltage.

[0057] In summary, the power supply circuit of the present invention has a reverse output circuit that enables the tablet SOC to support DPIN input and reverse charge other devices. The power supply circuit of the present invention also has an anti-misinsertion protection circuit that prevents irreversible damage to the motherboard caused by misinsertion.

[0058] The above description is only a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A power supply circuit with a reverse output circuit and an anti-misinsertion protection circuit, characterized in that: Including reverse output circuit and anti-misinsertion protection circuit; The reverse output circuit includes: A conversion chip with a DP to mipi csi circuit structure, which can convert the DP signal into a mipi csi camera input signal supported by the tablet computer SOC chip, so that the tablet computer SOC chip supports the DP1 function; A protocol chip capable of activating the DP output of an input device and charging the device. The protocol chip is provided with a communication pin CC. After the protocol chip establishes a connection with a device that supports DP output, it establishes communication with the device through the communication pin CC; The anti-misinsertion protection circuit includes: A first MOS transistor U9007, wherein a resistor R1 is connected between the drain D of the first MOS transistor U9007 and the 28-pin VIN of the protocol chip, and the gate G of the first MOS transistor U9007 is connected to the 25-pin GATE / GPIO20 of the protocol chip; a second MOS transistor U9008, wherein a gate G of the second MOS transistor U9008 is connected to a gate G of the first MOS transistor U9007, a source S of the second MOS transistor U9008 is connected to a source S of the first MOS transistor U9007, a drain D of the second MOS transistor U9008 is connected to a first end of a capacitor C7, and a second end of the capacitor C7 is grounded; a surge tube DU9 , wherein a first end of the surge tube DU9 is grounded, and a second end and a third end thereof are both connected to the drain D of the second MOS tube U9008 ; a polarized capacitor C9006, wherein the positive electrode of the polarized capacitor C9006 is connected to the second end of the surge tube DU9, and the negative electrode thereof is grounded; a capacitor C9005, wherein a first end of the capacitor C9005 is connected to the positive electrode of the polarized capacitor C9006, and a second end of the capacitor C9005 is grounded; Resistor R9209, a first end of the resistor R9209 is connected to the positive electrode of the polarized capacitor C9006, and a second end of the resistor R9209 is grounded.

2. The power supply circuit with a reverse output circuit and an anti-misinsertion protection circuit according to claim 1, characterized in that: The conversion chip is a LT7911D chip, and the protocol chip is a SW2505H chip.

3. The power supply circuit with a reverse output circuit and an anti-misinsertion protection circuit according to claim 2, characterized in that: The two ends of the resistor R1 are also connected to pins 27, CSPH, and 26, CSNH of the protocol chip, respectively; pin 5, VD3V3, of the protocol chip is connected to the first end of capacitor C3; pin 4, VDD1V5, of the protocol chip is connected to the first end of capacitor C4; pin 3, VCC5V, of the protocol chip is connected to the first end of capacitor C4; the second ends of capacitors C3, C4, and C5 are interconnected, then grounded and connected to the first end of capacitor C1; the second end of capacitor C1 is connected to the 5V input port of the power interface; The second end of the capacitor C1 is also connected to the 28-pin VIN of the protocol chip; The FB port of the power interface is connected to the 7-pin VD / FB / GPIO14 of the protocol chip; The OPTO port of the power interface is respectively connected to the OPTO / RFB / GPIO19 pin 1 of the protocol chip, the first end of the resistor R2, the first end of the resistor R3, and the first end of the resistor 4. The second end of the resistor R2 is grounded and connected to the first end of the capacitor C8. The second end of the capacitor C8 is connected to the IFB / GPIO16 pin 6 of the protocol chip. The second end of the resistor R3 is connected to the first end of the capacitor C2. The second end of the capacitor C2 is connected to the IFB / GPIO16 pin 6 of the protocol chip. The second end of the resistor R4 is connected to the first end of the capacitor C6. The second end of the capacitor C6 is connected to the VFB / GPIO19 pin 2 of the protocol chip.

4. The power supply circuit with a reverse output circuit and an anti-misinsertion protection circuit according to claim 2, characterized in that: Pin 22 CC1 / ID / GPIO10 of the protocol chip is connected to a first end of an ESD diode D9203, and a second end of the ESD diode D9203 is grounded; Pin 23 CC2 / GPIO11 of the protocol chip is connected to a first end of an ESD diode D9204, and a second end of the ESD diode D9204 is grounded.

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