Wireless network adapter for voice and fax dual-channel parallel communication

Abstract

The utility model discloses a wireless network adapter for voice and fax dual-channel parallel communication. The wireless network adapter comprises a voice channel, a fax channel and a wireless communication circuit, wherein the voice channel and the fax channel are parallel; the wireless communication circuit is connected with the voice channel and the fax channel; the voice channel comprises a first data processing circuit which is communicated with the analog telephone so as to transmit a voice control instruction and voice data, establish Volte voice communication at proper time and transmit uplink and downlink voice data; and the facsimile channel comprises a second data processing circuit and a protocol processing circuit which are communicated with the G3 type analog facsimile machine so as to transmit a facsimile control instruction and facsimile message data, timely establish an SIP (Session Initiation Protocol) session and transmit uplink and downlink facsimile data based on a T.38 protocol based on the SIP session. Compared with the prior art, the two channels operate independently and do not interfere with each other, the communication quality is high, a user can select the corresponding channel for communication according to the service type of voice or fax, and the flexibility is high.

Description

Technical Field

[0001] The utility model relates to the technical field of wireless network communication, in particular to a wireless network adapter for voice and fax dual-channel parallel communication. Background Art

[0002] The Public Telephone Network (PSTN) is gradually being phased out of service worldwide due to aging lines and equipment maintenance issues. However, in some countries and regions, users still need to continue using existing G3 analog fax machines for point-to-point real-time fax services that are carried on the PSTN and comply with the ITU T.30 specification due to regulatory requirements or user habits.

[0003] Technologically updated wired fiber optic networks or wireless 4G / 5G networks are all based on IP transmission technology. The International Telecommunication Union (ITU) has developed the T.38 specification for point-to-point real-time fax services in an IP network environment, introducing a type of network node called an IP fax adapter. One end of the IP fax adapter provides a two-wire SLIC interface to simulate PSTN central office access for connecting to traditional G3 analog fax machines; the other end is connected to the IP network via wired or wireless means. Within the technical architecture of the T.38 specification, the T.30 fax protocol is still used between the IP fax adapter and the G3 analog fax machine, and the encoding and decoding process from the T.30 fax analog signal to the T.38 IP data packet is implemented within the IP fax adapter. The two IP fax adapters establish a UDP or TCP network connection via the IP network gateway and transmission equipment, using the SIP protocol defined in the IETF RFC 3261 specification to establish a terminal session and transmit T.38 data packets.

[0004] Although IP fax adapters with 4G / 5G wireless transmission capabilities are quick and easy to deploy as a replacement for PSTN network connections for fax services, they still have two drawbacks:

[0005] (1) In a commercial network architecture based on the SIP protocol, widely used SIP service providers typically provide PSTN fixed-line numbers, which are allocated by an IP-PBX connected to the telecommunications backbone network on the Internet and mapped to the SIP address registered by the IP fax adapter. When this PSTN fixed-line number communicates with a large number of external mobile numbers, the charges are several times higher than those for calls between similar PSTN fixed-line numbers due to inter-network settlement. This creates a cost control problem for most fax machines used for both commercial fax and commercial voice services.

[0006] (2) Most fax machines use a single number for both business fax and business voice. When a fax is being sent or received, there is a certain probability that a voice call will come in, causing the fax process to be interrupted and disconnected. Utility Model Content

[0007] In view of this, the purpose of the present invention is to provide a wireless network adapter with dual-channel parallel communication for voice and fax, so as to provide a new circuit to solve the problems of high cross-network communication charges for numbers of different service types and probabilistic interference and interruption of fax communication caused by voice calls in IP fax adapter products based on the existing technology due to the shared communication channel and shared identity identification number for voice and fax services.

[0008] To achieve the above object, the utility model provides a wireless network adapter for voice and fax dual-channel parallel communication, comprising a parallel voice channel and a fax channel and a wireless communication circuit connected to both the voice channel and the fax channel;

[0009] The voice channel includes a first data processing circuit for communicating with an analog telephone, a first voice command recognition terminal of the first data processing circuit being electrically connected to a second voice command recognition terminal of the wireless communication circuit to implement transmission of voice control commands, and a first voice data communication terminal of the first data processing circuit being electrically connected to a second voice data communication terminal of the wireless communication circuit to implement transmission of voice data;

[0010] The fax channel includes a second data processing circuit and a protocol processing circuit for communicating with a G3 analog fax machine. A first fax instruction recognition terminal of the second data processing circuit is electrically connected to a second fax instruction recognition terminal of the protocol processing circuit to implement the transmission of T.30 fax control instructions. A first fax data communication terminal of the second data processing circuit is electrically connected to a second fax data communication terminal of the protocol processing circuit to implement the transmission of T.30 fax message data. The protocol processing circuit runs the T.30 fax protocol stack and the T.38 fax protocol stack to complete the encoding and decoding of the fax message data format, and uses a USB or UART communication interface to connect to the wireless communication circuit to implement wireless data sharing and transmission, thereby implementing T.38 fax communication with a remote destination fax device.

[0011] Furthermore, the first data processing circuit includes a voice data subcircuit connected to the analog telephone and a first power supply subcircuit electrically connected to the voice data subcircuit and supplying power to the voice data subcircuit; the input end of the voice data subcircuit is electrically connected to the analog telephone via a first two-wire SLIC interface to achieve voice analog signal transmission; the output end of the voice data subcircuit has a first SPI interface, the first SPI interface forms the first voice command recognition end to communicate with the second voice command recognition end of the wireless communication circuit, the voice control command analog signal of the analog telephone is modulated into voice control command data via the first two-wire SLIC interface and the voice data subcircuit, and then parsed by the wireless communication circuit via the first SPI interface to achieve the establishment or disconnection of the Volte voice call; the voice The output end of the voice and data subcircuit further includes a first PCM interface. The first PCM interface forms the first voice and data communication end for communication with the second voice and data communication end of the wireless communication circuit. After the Volte voice call is established, the analog uplink voice signal of the analog telephone is input into the voice and data subcircuit via the first two-wire SLIC interface. After analog-to-digital modulation is performed, the signal is converted into a PCM digital voice signal. The signal is then input into the wireless communication circuit via the first PCM interface. The wireless communication circuit encodes the signal into the uplink voice data of the Volte voice call. The downlink voice data of the Volte voice call is decoded into a PCM digital voice signal by the wireless communication circuit. The signal is then transmitted to the voice and data subcircuit via the first PCM interface. After digital-to-analog demodulation, the signal is converted into a downlink voice analog signal. The signal is then output from the analog telephone via the first two-wire SLIC interface.

[0012] Furthermore, the voice data subcircuit includes a first main control chip U2, an analog telephone connector J1, a first peripheral filtering unit electrically connected to the first main control chip U2, and a first interface filtering unit electrically connected between the first main control chip U2 and the analog telephone connector J1. The first peripheral filtering unit is used to filter signals connected to the first main control chip U2, and the first interface filtering unit is used to filter signals connected to the analog telephone connector J1 and the first main control chip U2. The model of the first main control chip U2 is SI32185.

[0013] The TIP pin and RING pin of the first main control chip U2 form the first two-wire SLIC interface and the TIP pin and RING pin of the first main control chip U2 are electrically connected to the TIP pin and RING pin of the analog telephone connector J1 via the first interface filtering unit, and the analog telephone connector J1 is connected to the analog telephone; the SCLK pin, CSB pin, SPI_MISO pin and SPI_MOSI pin of the first main control chip U2 form the first SPI interface to communicate with the second voice command recognition end of the wireless communication circuit; the PCLK pin, FSYNC pin, PCM_MISO pin and PCM_MOSI pin of the first main control chip U2 form the first PCM interface and communicate with the second voice data communication end of the wireless communication circuit via resistor R8, resistor R12, resistor R13 and resistor R15 respectively; the RESET pin and INT pin of the first main control chip U2 are both electrically connected to the wireless communication circuit.

[0014] Furthermore, the first power supply sub-circuit includes a first boost unit and a first voltage stabilizing unit, both of which are connected to the battery voltage. The first boost unit is electrically connected to the DCDRV pin, SDCH pin and SDCL pin of the first main control chip U2 and is controlled by the first main control chip U2. The first boost unit is used to boost the battery voltage to a first line voltage. The first boost unit has a first boost output end for outputting the first line voltage. The first boost output end is electrically connected to the VBAT pin of the first main control chip U2 and is electrically connected to the SVBAT pin of the first main control chip U2 via a resistor R28; the first voltage stabilizing unit is electrically connected to the wireless communication circuit and is controlled by the wireless communication circuit. The first voltage stabilizing unit is used to stabilize the battery voltage and output a first stable voltage. The first voltage stabilizing unit has a first stable output end for outputting the first stable voltage. The first stable output end is connected to the VDD pin, VDDA pin, VDDREG pin and VDDHV pin of the first main control chip U2 via the first peripheral filtering unit.

[0015] Furthermore, the wireless communication circuit includes a communication chip U3 and a fourth peripheral filtering unit connected to the communication chip U3, wherein the fourth peripheral filtering unit is used to filter the signal connected to the communication chip U3; the model of the communication chip U3 is EC25;

[0016] The VBAT0 pin, VBAT1 pin and VBAT2 pin of the communication chip U3 are connected to the battery voltage, and the USB_VBUS0 pin, USB_VBUS1 pin and USB_VBUS2 pin of the communication chip U3 are connected to the USB line voltage via the USB communication interface; the SPI_CLK pin, SPI_CS pin, SPI_MISO pin and SPI_MOSI pin of the communication chip U3 form the second voice data recognition end of the wireless communication circuit and are respectively electrically connected to the SCLK pin, CSB pin, SPI_MOSI pin and SPI_MISO pin of the first main control chip U2; the PCM_SYNC pin, The PCM_CLK pin, PCM_IN pin and PCM_OUT pin form the second voice data communication end of the wireless communication circuit and are electrically connected to the FSYNC pin, PCLK pin, PCM_MOSI pin and PCM_MISO pin of the first main control chip U2 respectively; the GPIO52 pin of the communication chip U3 is electrically connected to the first voltage stabilizing unit; the GPIO53 pin and EINT pin of the communication chip U3 are electrically connected to the RESET pin and INT pin of the first main control chip U2 respectively; the USB_DP pin and USB_DN pin of the communication chip U3 are provided to the protocol processing circuit using a USB communication interface to realize wireless data sharing and transmission.

[0017] Furthermore, the second data processing circuit includes a fax data subcircuit connected to a G3 analog fax machine and a second power supply subcircuit electrically connected to the fax data subcircuit and supplying power to the fax data subcircuit. The input end of the fax data subcircuit and the G3 analog fax machine utilize a second two-wire SLIC interface to transmit analog signals of fax control commands and fax voice. The output end of the fax data subcircuit has a second SPI interface, which forms the first fax command identification end and communicates with the second fax command identification end of the protocol processing circuit. The fax command analog signal of the G3 analog fax machine is transmitted via the second two-wire SLIC interface and modulated into fax command data by the fax data subcircuit. The signal is then parsed by the protocol processing circuit via the second SPI interface. The protocol processing circuit further runs the SIP protocol stack to extract the user identification number of the remote destination T.38 fax device contained in the fax command data, and establishes a SIP terminal session between the protocol processing circuit and the remote destination T.38 fax device via the wireless communication circuit. The fax data subcircuit also has a second PCM interface, which forms the first fax data communication end. The terminal communicates with the second fax data communication terminal of the protocol processing circuit. After the SIP terminal session is established, the uplink fax voice analog signal of the G3 analog fax machine is input through the second two-wire SLIC interface and modulated into a PCM digital voice signal by the fax data sub-circuit. The uplink fax voice analog signal is then input into the protocol processing circuit through the second PCM interface. The protocol processing circuit runs the T.30 fax protocol stack to encode the PCM digital voice signal into T.30 fax message data in HDLC data frame format. The protocol processing circuit further runs the T.38 fax protocol stack to convert the T.30 fax message data into T.30 fax message data in HDLC data frame format. The fax message is encoded as uplink fax message data in IFP format and transmitted to a remote destination T.38 fax device based on the SIP terminal session. The downlink fax data transmitted by the remote destination T.38 fax device is received by the protocol processing circuit and decoded into T.30 fax message data in HDLC data frame format by running the T.38 fax protocol stack. The downlink fax data is further decoded into PCM digital voice data by running the T.30 fax protocol stack. The downlink fax data is input through the second PCM interface, demodulated into a downlink fax voice analog signal by the fax data sub-circuit, and then output to the G3 analog fax machine through the second two-wire SLIC interface.

[0018] Furthermore, the fax data subcircuit includes a second main control chip U4, a fax connector J2, a second peripheral filter unit electrically connected to the second main control chip U4, and a second interface filter unit electrically connected between the second main control chip U4 and the fax connector J2. The second peripheral filter unit is used to filter signals connected to the second main control chip U4, and the second interface filter unit is used to filter signals connected to the fax connector J2 from the second main control chip U4. The model of the second main control chip U4 is SI32185.

[0019] The TIP pin and RING pin of the second main control chip U4 form the second two-wire SLIC interface and are electrically connected to the TIP pin and RING pin of the fax machine connector J2 via the second interface filter unit, and the fax machine connector J2 is connected to the G3 analog fax machine; the SCLK pin, CSB pin, SPI_MISO pin and SPI_MOSI pin of the second main control chip U4 form the second SPI interface and communicate with the second fax instruction recognition end of the protocol processing circuit; the PCLK pin, FSYNC pin, PCM_MISO pin and PCM_MOSI pin of the second main control chip U4 form the second PCM interface and communicate with the second fax data communication end of the protocol processing circuit via resistors R51, R52, R56 and R53 respectively; the RESET pin and INT pin of the second main control chip U4 are both electrically connected to the protocol processing circuit.

[0020] Furthermore, the second power supply sub-circuit includes a second boost unit and a second voltage stabilizing unit, both of which are connected to the battery voltage. The second boost unit is electrically connected to the DCDRV pin, SDCH pin and SDCL pin of the second main control chip U4 and is controlled by the second main control chip U4. The second boost unit is used to boost the battery voltage to a second line voltage. The second boost unit has a second boost output end for outputting the second line voltage. The second boost output end is electrically connected to the VBAT pin of the second main control chip U4 and is electrically connected to the SVBAT pin of the second main control chip U4 via a resistor R71; the second voltage stabilizing unit is electrically connected to the protocol processing circuit and is controlled by the protocol processing circuit. The second voltage stabilizing unit is used to stabilize the battery voltage and output a second stable voltage. The second voltage stabilizing unit has a second stable output end for outputting the second stable voltage. The second stable output end is connected to the VDD pin, VDDA pin, VDDREG pin and VDDHV pin of the second main control chip U4 via the second peripheral filtering unit.

[0021] Furthermore, the protocol processing circuit includes a protocol chip U8 and a third peripheral filtering unit connected to the protocol chip U8, wherein the third peripheral filtering unit is used to filter the signal connected to the protocol chip U8; the model of the protocol chip U8 is T113; the protocol processing circuit is an independent electronic component group unit, or a software unit running inside the wireless communication circuit and including a SIP protocol stack and a T.30 / T.38 fax protocol stack;

[0022] The VBAT0 pin and VBAT1 pin of the protocol chip U8 are connected to the battery voltage, the VDD1V85 pin of the protocol chip U8 is connected to the first external voltage, and the VDD2V8 pin is connected to the second external voltage; the SPI_CLK pin, SPI_CSN pin, SPI_MISO pin and SPI_MOSI pin of the protocol chip U8 form the second fax data recognition end of the protocol processing circuit and are respectively electrically connected to the SCLK pin, CSB pin, SPI_MOSI pin and SPI_MISO pin of the second main control chip U4; the PCM_SYNC pin, PCM_CLK pin, PCM_IN pin of the protocol chip U8 The PCM_OUT pin forms the second fax data communication terminal of the protocol processing circuit and is respectively electrically connected to the PCLK pin, FSYNC pin, PCM_MOSI pin and PCM_MISO pin of the second main control chip U4; the GPIO20 pin of the protocol chip U8 is electrically connected to the second voltage stabilizing unit; the GPIO26 pin and EXTING pin of the protocol chip U8 are respectively electrically connected to the RESET pin and INT pin of the second main control chip U4; the USBDP pin and USBDN pin of the protocol chip U8 are respectively electrically connected to the USB_DP pin and USB_DN pin of the communication chip U3 using a USB communication interface.

[0023] Furthermore, when the voice channel is connected to an external G3 analog fax machine, during the Volte voice call, the wireless communication circuit negotiates with the wireless network end IMS to limit the wireless transmission voice coding format to G.711, so as to establish Volte voice communication with a remote destination T.30 fax device; the fax message analog signal of the G3 analog fax machine is input into the voice data sub-circuit via the first two-wire SLIC interface, undergoes analog-to-digital modulation into a PCM digital voice signal, and is then input into the wireless communication circuit via the first PCM interface. The wireless communication circuit then encodes the signal into a G.711 format digital voice signal, which is then transmitted via the wireless network end IMS to the remote destination T.30 fax device for T.30 fax message parsing, thereby establishing a Volte voice channel in the G.711 coding format between the G3 analog fax machine and the remote destination T.30 fax device, and implementing T.30 point-to-point fax communication with G.711 passthrough based on the Volte voice channel.

[0024] The utility model is provided with a first data processing circuit having a two-wire SLIC TIP / RING interface of the FXS standard for connecting to an external analog telephone, and a second data processing circuit having a two-wire SLIC TIP / RING interface of the FXS standard for connecting to an external G3 analog fax machine. The first data processing circuit and the second data processing circuit are provided with a PCM digital voice interface and an analog / digital voice codec CODEC submodule, which are respectively connected to the wireless communication circuit and the protocol processing circuit. Independent VOLTE voice service and T.38 fax service can be run when connected to the same wireless communication circuit. The two services use different user identification numbers, which are respectively identified and analyzed by the wireless communication circuit and the protocol processing circuit. The services between the two channels do not interfere with each other, and it is beneficial for users to achieve better tariff plans by selecting appropriate service channels for communication. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is a circuit block diagram of a wireless network adapter for dual-channel parallel communication of voice and fax according to the present invention.

[0026] Figure 2 This is the circuit schematic diagram of the voice data subcircuit.

[0027] Figure 3 2 is a circuit schematic diagram of the first power supply sub-circuit.

[0028] Figure 4 This is the circuit schematic diagram of the fax data subcircuit.

[0029] Figure 5 2 is a circuit schematic diagram of the second power supply sub-circuit.

[0030] Figure 6 This is the circuit schematic diagram of the protocol processing circuit.

[0031] Figure 7 This is the circuit schematic diagram of the wireless communication circuit.

[0032] The accompanying drawings in this specification are numeraled as follows:

[0033] Voice channel A, fax channel B, first data processing circuit 10, voice data sub-circuit 11, first power sub-circuit 12, first voltage boosting unit 12A, first voltage stabilizing unit 12B, second data processing circuit 20, fax data sub-circuit 21, second power sub-circuit 22, second voltage boosting unit 22A, second voltage stabilizing unit 22B, protocol processing circuit 30, wireless communication circuit 40, analog telephone 50, G3 analog fax machine 60. DETAILED DESCRIPTION

[0034] The following is further described in detail through specific implementation methods:

[0035] Example

[0036] Please refer to Figure 1 The wireless network adapter for voice and fax dual-channel parallel communication according to an embodiment of the present invention includes a parallel voice channel A and a fax channel B and a wireless communication circuit 40 connected to both the voice channel A and the fax channel B.

[0037] Voice channel A includes a first data processing circuit 10 that communicates with an analog telephone 50. The input end of the first data processing circuit 10 communicates with the analog telephone 50 to transmit a voice analog signal; the output end of the first data processing circuit 10 communicates with the wireless communication circuit 40 to realize the transmission of uplink and downlink voice data. The first voice command recognition end of the first data processing circuit 10 is electrically connected to the second voice command recognition end of the wireless communication circuit 40 to realize the transmission of voice control command data. The first voice data communication end of the first data processing circuit 10 is electrically connected to the second voice data communication end of the wireless communication circuit 40 to realize the transmission of voice data. The first data processing circuit 10 and the wireless communication circuit 40 constitute the VOLTE voice channel A of the wireless network adapter with dual-channel parallel communication of voice and fax in this embodiment. The user identification number of the VOLTE voice communication is defined by the private identifier IMPI or the public identifier IMPU in the USIM used by the wireless communication circuit 40.

[0038] The first data processing circuit 10 includes a voice data subcircuit 11 connected to the analog telephone 50, and a first power supply subcircuit 12 electrically connected to the voice data subcircuit 11 and providing power to the voice data subcircuit 11. The first power supply subcircuit 12 is connected to the battery voltage (i.e., connected to the battery voltage terminal VBAT), and is capable of boosting the battery voltage to a first line voltage and stabilizing the battery voltage to output a first regulated voltage. The first line voltage and the first regulated voltage are used to power the voice data subcircuit 11. In this embodiment, the battery voltage is preferably 3.5-4.2V, the first line voltage is preferably 48V, and the first regulated voltage is preferably 3.3V.

[0039] The input end of the voice data sub-circuit 11 and the analog telephone 50 use a first two-wire SLIC interface to transmit voice analog signals. In this embodiment, the first two-wire SLIC interface is defined as an FXS standard two-wire SLIC TIP / RING interface.

[0040] The output end of the voice data subcircuit 11 has a first SPI interface, and the first SPI interface forms a first voice command recognition end that communicates with the second voice command recognition end of the wireless communication circuit 40. The voice control command analog signal of the analog telephone 50 is modulated by the first two-wire SLIC interface and the voice data subcircuit 11, and then parsed by the wireless communication circuit 40 through the first SPI interface to realize the transmission of the voice control command. Specifically, the voice control command of the analog telephone 50 (including but not limited to off-hook, DTMF dialing, ringing, on-hook and other commands) is output to the voice data subcircuit 11 through the first two-wire SLIC interface. The voice control command analog signal of the analog telephone 50 is modulated by the voice data subcircuit 11, and after being parsed by the wireless communication circuit 40 through the first SPI interface, the call, answer or hang-up operation of the 4G or 5G wireless VOLTE voice communication is completed to establish or disconnect the VOLTE voice communication.

[0041] The output end of the voice data subcircuit 11 also has a first PCM interface, which forms a first voice data communication end and communicates with the second voice data communication end of the wireless communication circuit 40. The uplink voice analog signal of the analog telephone 50 is input through the first two-wire SLIC interface, subjected to analog-to-digital modulation by the voice data subcircuit 11, and then input into the wireless communication circuit 40 through the first PCM interface. The downlink voice data of the wireless communication circuit 40 is demodulated by the voice data subcircuit 11 through the first PCM interface and then output to the analog telephone 50 through the first two-wire SLIC interface. Specifically, when the voice data subcircuit 11 and the wireless communication circuit 40 perform VoLTE voice data transmission, both VoLTE uplink voice data transmission and VoLTE downlink voice data transmission are included. For the transmission of VOLTE uplink voice data, the uplink analog voice signal of the analog telephone 50 is input into the voice data sub-circuit 11 via the first two-wire SLIC interface. The voice data sub-circuit 11 modulates the uplink analog voice signal into a 16-bit PCM digital voice signal and inputs it into the wireless communication circuit 40 via the first PCM interface. The wireless communication circuit 40 encodes the 16-bit PCM digital voice signal into the uplink voice data of the VOLTE voice call in AMR-WB format. For the transmission of downlink voice data, the downlink digital voice data of the VOLTE voice call in AMR-WB format of the wireless communication circuit 40 is decoded into a 16-bit PCM digital voice signal by the wireless communication circuit 40. The signal is further input into the voice data sub-circuit 11 via the first PCM interface. The voice data sub-circuit 11 demodulates the 16-bit PCM digital voice signal into a voice analog signal and then outputs it to the analog telephone 50 via the first two-wire SLIC interface to achieve downlink voice data transmission. In specific implementation, the VOLTE voice channel can be a direct connection between the first data processing circuit 10 and the wireless communication circuit 40 using a PCM digital voice interface, or the first data processing circuit 10 can demodulate the 16-bit PCM digital voice signal into an analog voice signal via the digital-to-analog decoding converter ADC, and then input it into the analog voice interface of the wireless communication circuit 40.

[0042] Please refer to Figure 2The voice data subcircuit 11 includes a first main control chip U2, an analog telephone connector J1, a first peripheral filter unit electrically connected to the first main control chip U2, and a first interface filter unit electrically connected between the first main control chip U2 and the analog telephone connector J1. In this embodiment, the first main control chip U2 preferably employs a voice control chip model SI32185. The first main control chip U2 implements the input of analog voice signals and performs analog-to-digital modulation and digital-to-analog demodulation on the analog voice signals. Since this embodiment only involves the circuit architecture related to data transmission and does not involve program processing, the specific processes of the first main control chip U2 for inputting analog voice signals and performing analog-to-digital modulation and digital-to-analog demodulation on the voice signals are prior art. The first main control chip U2 can be purchased directly and is not described in detail in this embodiment.

[0043] Specifically, the TIP and RING pins of the first main control chip U2 form a first two-wire SLIC interface and are electrically connected to the TIP and RING pins of the analog phone connector J1 via a first interface filter unit. The analog phone connector J1 is connected to the analog phone 50 to communicate analog signals with the analog phone 50. The SCLK, CSB, SPI_MISO, and SPI_MOSI pins of the first main control chip U2 form a first SPI interface that communicates with the second voice command recognition terminal of the wireless communication circuit 40 to transmit voice command data and establish or terminate a voice call according to voice control commands. The PCLK, FSYNC, PCM_MISO, and PCM_MOSI pins of the first master control chip U2 form a first PCM interface and communicate with the second voice and data communication terminal of the wireless communication circuit 40 via resistors R8, R12, R13, and R15, respectively, to transmit uplink and downlink voice data. Resistors R8, R12, R13, and R15 act as current-limiting resistors to prevent excessive current from damaging components. The PCLK pin of the first master control chip U2 is also connected to ground via capacitor C13, which acts as a filter. The RESET pin of the first master control chip U2 is connected to the wireless communication circuit 40 and is also grounded via resistor R31 to provide a reset signal for the first master control chip U2. The INT pin of the first master control chip U2 is also connected to the wireless communication circuit 40 and is also connected to a third external voltage, preferably 1.8V, via resistor R29 to provide an interrupt signal for the first master control chip U2. The CAPP pin of the first main control chip U2 is electrically connected to its CAPM pin via a capacitor C25. The IREF pin of the first main control chip U2 is grounded via a resistor R30.

[0044] The VDD, VDDA, VDDREG, and VDDHV pins of the first master control chip U2 are connected to a first stable voltage via a first peripheral filtering unit. The SVBAT and VBAT pins of the first master control chip U2 are connected to a first line voltage via the first peripheral filtering unit. The VDDIO pin of the first master control chip U2 is connected to a third external voltage via the first peripheral filtering unit. The GND0, GND1, and GND2 pins of the first master control chip U2 are grounded to form a power supply circuit, ensuring the normal operation of the first master control chip U2. The first peripheral filtering unit is used to filter the signals (primarily the power supply signals) connected to the first master control chip U2.

[0045] In this embodiment, the first peripheral filtering unit includes a resistor R2, a resistor R4, a resistor R6, a resistor R28, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C8, a capacitor C9, a capacitor C10, a capacitor C11 and a capacitor C32.

[0046] Specifically, the VDD pin of the first master control chip U2 is connected to the first stable voltage via the resistor R6, and the VDD pin of the first master control chip U2 is also grounded via capacitors C8 and C9 respectively; the VDDA pin of the first master control chip U2 is connected to the first stable voltage via the resistor R4, and the VDDA pin of the first master control chip U2 is also grounded via capacitors C4 and C5 respectively; the VDDHV pin of the first master control chip U2 is connected to the first stable voltage via the resistor R2, and the VDDHV pin of the first master chip U2 is also grounded via capacitors C6 and C7 respectively; the VDDREG pin of the first master control chip U2 is grounded via capacitor C10; the VDDIO pin of the first master chip U2 is connected to the third external voltage, and the VDDIO pin of the first master chip U2 is also grounded via capacitor C11; the SVBAT pin of the first master chip U2 is connected to the first line voltage via resistor R28; the VBAT pin of the first master chip U2 is connected to the first line voltage, and the VBAT pin of the first master chip U2 is also grounded via capacitor C32.

[0047] The first interface filter unit is used to filter the signal (mainly the analog signal of the connected analog telephone 50) connected to the first main control chip U2 via the analog telephone connector J1.

[0048] In this embodiment, the first peripheral filtering unit includes a resistor R7, a resistor R9, a resistor R10, a resistor R11, a resistor R14, a resistor R16, a resistor R17, a resistor R18, a resistor R19, a resistor R20, a resistor R21, a resistor R22, a resistor R23, a resistor R24, a resistor R25, a resistor R26, a resistor R27, a capacitor C12, a capacitor C14, a capacitor C15, a capacitor C16, a capacitor C17, a capacitor C22, a capacitor C23, a capacitor C24, a rectifier diode DB1, a bidirectional diode TVS1 and a bidirectional diode TVS2.

[0049] Specifically, resistor R17, resistor R18, resistor R19 and resistor R20 are connected in series in sequence between the TIP pin of the first main control chip U2 and the TIP pin of the analog telephone connector J1, the TIP pin of the first main control chip U2 is grounded via capacitor C22, resistor R21, resistor R22, resistor R23 and resistor R24 are connected in series in sequence between the RING pin of the first main control chip U2 and the RING pin of the analog telephone connector J1, the RING pin of the first main control chip U2 is grounded via capacitor C23 to form a communication loop between the first main control chip U2 and the analog telephone connector J1. The TIP pin of the first master control chip U2 is also connected to the STIPDC pin of the first master control chip U2 via the resistor R14. The TIP pin of the first master control chip U2 is also connected to the STIPAC pin of the first master control chip U2 via the resistor R7 and the capacitor C12 in sequence. The RING pin of the first master control chip U2 is also connected to the SRINGDC pin of the first master control chip U2 via the resistor R16. The RING pin of the first master control chip U2 is also connected to the SRINGAC pin of the first master control chip U2 via the resistor R11 and the capacitor C15 in sequence. One end of the resistor R9 is connected between the resistor R7 and the capacitor C12, and the other end is connected between the resistor R11 and the capacitor C15 to form a power supply circuit.

[0050] One end of capacitor R16 is connected between resistor R17 and resistor R18, and the other end is connected between resistor R21 and resistor R22; one end of capacitor R17 is connected between resistor R18 and resistor R19, and the other end is connected between resistor R22 and resistor R23; one end of resistor R10 is connected between resistor R17 and resistor R18, and the other end is connected to the STIPC pin of the first main control chip U2 via resistor R25; one end of resistor R26 is connected between resistor R21 and resistor R22, and the other end is connected to the SRINGC pin of the first main control chip U2 via resistor R27; one end of capacitor C14 is connected between resistor R18 and resistor R19, and the other end is grounded; one end of capacitor C24 is connected between resistor R22 and resistor R23, and the other end is grounded.

[0051] Terminal A1 of rectifier diode DB1 is connected between resistors R23 and R24, terminal A2 is connected between resistors R19 and R20, and terminal K is grounded. In this embodiment, the preferred model of rectifier diode DB1 is BAV70. Pin 1 of bidirectional diode TVS1 is connected between resistor R20 and the TIP pin of analog phone connector J1, and pin 2 is grounded. Pin 1 of bidirectional diode TVS2 is connected between resistor R24 and the RING pin of analog phone connector J1, and pin 2 is grounded.

[0052] Please refer to Figure 3 The first power supply subcircuit 12 includes a first boost unit 12A and a first voltage stabilizing unit 12B. The first boost unit 12A and the first voltage stabilizing unit 12B are both connected to the battery voltage. The first boost unit 12A is used to boost the battery voltage into a first line voltage. The first regulated power supply is used to stabilize the battery voltage and output a first stable voltage to power the voice data subcircuit 11.

[0053] The first boost unit 12A is electrically connected to the DCDRV, SDCH, and SDCL pins of the first master chip U2. These pins serve as a first line voltage driver, allowing the first boost unit 12A to be controlled by the first master chip U2. The first master chip U2 then controls the first boost unit 12A to boost the battery voltage to the first line voltage at the appropriate time. The first boost unit 12A has a first boost output terminal (i.e., LINE_48V_1) that outputs the first line voltage. This first boost output terminal is electrically connected to the VBAT pin of the first master chip U2 and, via resistor R28, to the SVBAT pin of the first master chip U2.

[0054] In this embodiment, the first boost unit 12A includes a resistor R32, a resistor R33, a resistor R34, a resistor R35, a resistor R36, a resistor R37, a resistor R38, a resistor R39, a resistor R40, a resistor R41, a resistor R42, a capacitor C30, a capacitor C31, a capacitor C33, a capacitor C34, a capacitor C35, a capacitor C36, a capacitor C37, a capacitor C38, a capacitor C39, a capacitor C40, a capacitor C41, a capacitor C42, a capacitor C43, an inductor L1, a transistor Q1, a rectifier diode DB2, a rectifier diode DB3, a rectifier diode DB4, and a rectifier diode DB5. In this embodiment, the transistor Q1 is preferably NTR5198, and the rectifier diodes DB2, DB3, DB4, and DB5 are preferably BAV70.

[0055] Specifically, a voltage battery is connected via the battery voltage input terminal (ie, VBAT), and the battery voltage input terminal is grounded via capacitors C36, C37, C38, and C40, respectively, to filter the connected battery voltage. The battery voltage input terminal is connected to the drain of the transistor Q1 via the inductor L1. A resistor R34 and a capacitor C39 are connected in series and connected to both ends of the inductor L1. The gate of the transistor Q1 is connected to the DCDRV pin of the first master control chip U2 and is also grounded via a resistor R35. The source of the transistor Q1 is grounded via resistors R37, R38, R39, R40, and R41, respectively. The source of the transistor Q1 is also connected to the SDCH pin of the first master control chip U2 via a resistor R36. The SDCL pin of the first master chip U2 is grounded via a resistor R42. The SDCL pin of the first master chip U2 is also connected to the SDCH pin of the first master chip U2 via a capacitor C30. The DCFF pin of the first master chip U2 is grounded via a capacitor C31. The first master chip U2 sends a drive signal to drive the transistor Q1 on and off to achieve control of the first boost unit 12A. The drain of transistor Q1 is also connected to one end of capacitor C41, the other end of capacitor C41 is connected to the K end of rectifier diode DB4 and the A1 and A2 ends of rectifier diode DB5, the K end of rectifier diode DB5 is connected to the source of transistor Q1, the A1 and A2 ends of rectifier diode DB4 are connected and then grounded through capacitor C42, and the A1 and A2 ends of rectifier diode DB4 are connected and then connected to the K end of rectifier diode DB3; the drain of transistor Q1 is connected to one end of capacitor C33, the other end of capacitor C33 is connected to the K end of rectifier diode DB2 The A1 and A2 ends of the rectifier diode DB3 are both connected. The A1 end of the rectifier diode DB2 is connected to its A2 end and then connected to the K end of the rectifier diode DB3 through capacitors C34 and C35 respectively. The A1 end of the rectifier diode DB2 is connected to its A2 end and then outputs the first line voltage in sequence through resistors R32 and R33 to form a first boost output end connected to the first main control chip U2; one end of the capacitor C43 is connected between the resistor R32 and the resistor R33, and the other end is grounded; the battery voltage is boosted by cooperating with multiple rectifier diodes to output the first line voltage.

[0056] The first voltage stabilizing unit 12B is electrically connected to and controlled by the wireless communication circuit 40. The wireless communication circuit 40 can timely control the first voltage stabilizing unit 12B to stabilize the battery voltage and stably output a first stable voltage. The first voltage stabilizing unit 12B has a first regulated output terminal (i.e., SLIC_3V3) that outputs the first stable voltage. The first regulated output terminal is connected to the VDD pin, VDDA pin, VDDREG pin, and VDDHV pin of the first main control chip U2 via a first peripheral filtering unit.

[0057] In this embodiment, the first voltage stabilizing unit 12B includes a voltage stabilizing chip U1, a resistor R1, a resistor R3, a resistor R5, a capacitor C1, a capacitor C2, and a capacitor C3. Specifically, the VIN pin of the voltage stabilizing chip U1 is connected to the battery voltage, and the VIN pin of the voltage stabilizing chip U1 is grounded via a capacitor C3, which is a filter capacitor; the GND pin of the voltage stabilizing chip U1 is grounded to form a loop to ensure the normal operation of the voltage stabilizing chip U1. The EN pin of the voltage stabilizing chip U1 is connected to the wireless communication circuit 40 to receive the enable signal sent by the wireless communication circuit 40, thereby enabling the wireless communication circuit 40 to control the first voltage stabilizing unit 12B and output a first stable voltage; the EN pin of the voltage stabilizing chip U1 is also grounded via a resistor R3, which is a current limiting resistor. The VOUT pin of voltage regulator chip U1 is connected to ground via resistors R1 and R2, respectively. The FB / BP pin of voltage regulator chip U1 is connected between resistors R1 and R2. The FB / BP pin of voltage regulator chip U1 collects the voltage divider between resistors R1 and R2 and provides feedback on the first stable voltage output by voltage regulator chip U1, ensuring stable voltage output. The VOUT pin of voltage regulator chip U1 is also connected to ground via capacitors C1 and C2, forming a first regulated output terminal that outputs the first stable voltage. Capacitors C1 and C2 serve as filter capacitors.

[0058] Please refer to Figure 1 Fax channel B includes a protocol processing circuit 30 that communicates with a G3 analog fax machine 60 and a second data processing circuit 20 electrically connected to the protocol processing circuit 30. One end of the second data processing circuit 20 communicates with the G3 analog fax machine 60; the other end of the second data processing circuit 20 communicates with the protocol processing circuit 30. A first fax command recognition end of the second data processing circuit 20 is electrically connected to a second fax command recognition end of the protocol processing circuit 30 to enable transmission of fax command data. A first fax data communication end of the second data processing circuit 20 is electrically connected to a second fax data communication end of the protocol processing circuit 30 to enable transmission of fax data. The protocol processing circuit 30 uses a communication interface, such as a USB interface or a UART interface, to communicate with the wireless communication circuit 40 for fax data transmission. This communication interface provides wireless data sharing (TETHERING) for the protocol processing circuit 30. The protocol processing circuit 30, the second data processing circuit 20, and the wireless communication circuit 40 constitute the T.38 fax channel B of the wireless network adapter for dual-channel parallel voice and fax communication in this embodiment. The T.38 fax user identification number is a SIP address assigned by an IP-PBX registered on the Internet based on the SIP protocol stack running in the protocol processing circuit 30, and is mapped and recognized by the IP-PBX to an E.164 public telephone number.

[0059] The second data processing circuit 20 includes a fax data subcircuit 21 connected to the G3 analog fax machine 60, and a second power supply subcircuit 22 electrically connected to and providing power to the fax data subcircuit 21. The second power supply subcircuit 22 is connected to the battery voltage (i.e., connected to the battery voltage terminal VBAT), and is capable of boosting the battery voltage to a second line voltage and stabilizing the battery voltage to output a second stable voltage. The second line voltage and the second stable voltage are used to power the voice data 11. In this embodiment, the battery voltage is preferably 3.5-4.2V, the second line voltage is preferably 48V, and the second stable voltage is preferably 3.3V.

[0060] The input end of the fax data subcircuit 21 and the G3 analog fax machine 60 use a second two-wire SLIC interface to implement fax analog signal transmission. In this embodiment, the second two-wire SLIC interface is limited to a central office FXS standard two-wire SLIC TIP / RING interface.

[0061] The output terminal of the fax data subcircuit 21 has a first SPI interface. The first SPI interface forms a first fax command recognition terminal for communication with a second fax command recognition terminal of the protocol processing circuit 30. Fax control commands from the G3 analog fax machine 60 are input as analog signals via the second two-wire SLIC interface. After analog-to-digital modulation is performed by the fax data subcircuit 21, they are parsed by the protocol processing circuit 30 via the second SPI interface. The protocol processing circuit 30 then runs the SIP protocol stack to establish a SIP session connection with the destination T.38 fax device. Specifically, fax command analog signals (including but not limited to off-hook, DTMF dialing, ringing, and on-hook control commands) from the G3 analog fax machine 60 are input to the fax data sub-circuit 21 via the second two-wire SLIC interface. The fax command analog signals from the G3 analog fax machine 60 are modulated by the fax data sub-circuit 21 and parsed by the protocol processing circuit 30 via the second SPI interface. The protocol processing circuit 30 then runs the SIP protocol stack, resolves the SIP call destination number through its registered IP-PBX connected to the telecommunications backbone network, initiates a SIP session to the destination T.38 fax device, or answers a SIP call from the destination T.38 fax device, thereby establishing a SIP session.

[0062] The output end of the fax data subcircuit 21 further includes a second PCM interface. The second PCM interface forms a first fax data communication end for communication with a second fax data communication end of the protocol processing circuit 30. After the SIP session is established, an analog signal representing a fax message is input from the G3 analog fax machine 60 via the second two-wire SLIC interface to the fax data subcircuit 21 for analog-to-digital modulation into a PCM digital voice signal. The signal is then input via the second PCM interface to the protocol processing circuit 30. The protocol processing circuit 30 then runs the T.30 fax protocol stack to parse the signal into an HDLC data frame (including but not limited to digital identification signals DIS, DCS, TCF, CFR, and fax content message), thereby establishing a point-to-point T.30 fax communication between the protocol processing circuit 30 and the G3 analog fax machine 60. The protocol processing circuit 30 then runs the T.38 fax protocol stack to transmit uplink fax data in the form of IFP fax data packets based on the SIP session with the destination T.38 fax device in FAX RELAY mode. The protocol processing circuit 30 runs the T.38 fax protocol stack to transmit fax data in the form of FAX packets based on the SIP session. In the RELAY mode, downlink fax data in the form of IFP fax packets transmitted by the T.38 fax device at the destination is received and parsed into binary HDLC data frames by the T.38 fax protocol stack. The data frames are further decoded into PCM digital voice signals by the T.30 fax protocol stack. The signals are then demodulated via the second PCM interface and the fax data sub-circuit 21 into fax analog signals, which are then output to the G3 analog fax machine 60 via the second two-wire SLIC interface.

[0063] Please refer to Figure 4 The fax data subcircuit 21 includes a second main control chip U4, a fax machine connector J2, a second peripheral filter unit electrically connected to the second main control chip U4, and a second interface filter unit electrically connected between the second main control chip U4 and the fax machine connector J2. In this embodiment, the second main control chip U4 preferably employs a voice control chip model SI32185. The second main control chip U4 provides fax analog signal input and implements analog-to-digital modulation and digital-to-analog demodulation of the fax analog signal. Since this embodiment only involves the circuit architecture related to data transmission and does not involve program processing, the specific processes of the second main control chip U4 for inputting fax analog signals and implementing analog-to-digital modulation and digital-to-analog demodulation of the fax analog signal are known from the prior art. The second main control chip U4 is readily available and will not be described in detail in this embodiment.

[0064] Specifically, the TIP and RING pins of the second main control chip U4 form a second two-wire SLIC interface and are electrically connected to the TIP and RING pins of the fax machine connector J2 via a second interface filter unit. The fax machine connector J2 is connected to the G3 analog fax machine 60 for communication with the G3 analog fax machine 60. The SCLK, CSB, SPI_MISO, and SPI_MOSI pins of the second main control chip U4 form a second SPI interface for communication with the second fax command recognition terminal of the protocol processing circuit 30 to transmit fax command data and establish a SIP session when appropriate. The PCLK, FSYNC, PCM_MISO, and PCM_MOSI pins of the second master control chip U4 form a second PCM interface and communicate with the second fax data communication port of the protocol processing circuit 30 via resistors R51, R52, R56, and R53, respectively, to transmit uplink and downlink fax data. Resistors R51, R52, R56, and R53 act as current-limiting resistors to prevent excessive current from damaging components. The PCLK pin of the second master control chip U4 is also connected to ground via capacitor C54, which provides filtering. The RESET pin of the second master control chip U4 is connected to the protocol processing circuit 30 and is also grounded via resistor R81 to provide a reset signal for the second master control chip U4. The INT pin of the second master control chip U4 is also connected to the protocol processing circuit 30 and is also connected to a first external voltage, preferably 1.85V, via resistor R79 to provide an interrupt signal for the second master control chip U4. The CAPP pin of the second main control chip U4 is electrically connected to its CAPM pin via capacitor C72. The IREF pin of the second main control chip U4 is grounded via resistor R80.

[0065] The VDD, VDDA, VDDREG, and VDDHV pins of the second master chip U4 are connected to a second stable voltage via a second peripheral filtering unit. The SVBAT and VBAT pins of the second master chip U4 are connected to a second line voltage via a second peripheral filtering unit. The VDDIO pin of the second master chip U4 is connected to a first external voltage via a second peripheral filtering unit. The GND0, GND1, and GND2 pins of the second master chip U4 are grounded to form a power supply circuit, ensuring the normal operation of the second master chip U4. The second peripheral filtering unit is used to filter the signals (primarily the power supply signals) connected to the second master chip U4.

[0066] In this embodiment, the second peripheral filtering unit includes a resistor R43, a resistor R44, a resistor R45, a resistor R71, a capacitor C44, a capacitor C45, a capacitor C46, a capacitor C47, a capacitor C48, a capacitor C49, a capacitor C50, a capacitor C51 and a capacitor C75. Specifically, the VDD pin of the second main control chip U4 is connected to the second stable voltage via the resistor R45, and the VDD pin of the second main control chip U4 is also grounded via the capacitors C48 and C49 respectively; the VDDA pin of the second main control chip U4 is connected to the second stable voltage via the resistor R44, and the VDDA pin of the second main control chip U4 is also grounded via the capacitors C44 and C45 respectively; the VDDHV pin of the second main control chip U4 is connected to the second stable voltage via the resistor R43, and the VDDHV pin of the second main control chip U4 is connected to the second stable voltage. They are also grounded via capacitors C46 and C47 respectively; the VDDREG pin of the second master control chip U4 is grounded via capacitor C50; the VDDIO pin of the second master control chip U4 is connected to the first external voltage, and the VDDIO pin of the second master control chip U4 is also grounded via capacitor C51; the SVBAT pin of the second master control chip U4 is connected to the second line voltage via resistor R71; the VBAT pin of the second master chip U4 is connected to the second line voltage, and the VBAT pin of the second master chip U4 is also grounded via capacitor C75.

[0067] The second interface filter unit is used to filter the signal (mainly the signal of the connected G3 type analog fax machine 60) connected to the second main control chip U4 via the fax machine connector J2.

[0068] In this embodiment, the second peripheral filtering unit includes resistor R46, resistor R49, resistor R50, resistor R55, resistor R57, resistor R58, resistor R59, resistor R60, resistor R61, resistor R62, resistor R64, resistor R65, resistor R66, resistor R67, resistor R68, resistor R69, resistor R70, capacitor C52, capacitor C57, capacitor C61, capacitor C65, capacitor C66, capacitor C67, capacitor C68, capacitor C71, rectifier diode DB8, bidirectional diode TVS3 and bidirectional diode TVS4.

[0069] Specifically, resistors R59, R60, R61, and R62 are sequentially connected in series between the TIP pin of the second main control chip U4 and the TIP pin of the fax machine connector J2. The TIP pin of the second main control chip U4 is grounded via capacitor C67. Resistors R66, R64, R67, and R65 are sequentially connected in series between the RING pin of the second main control chip U4 and the RING pin of the fax machine connector J2. The RING pin of the second main control chip U4 is grounded via capacitor C68 to form a communication loop between the second main control chip U4 and the fax machine connector J2. The TIP pin of the second master control chip U4 is also connected to the STIPDC pin of the second master control chip U4 via the resistor R57. The TIP pin of the second master control chip U4 is also connected to the STIPAC pin of the second master control chip U4 via the resistor R46 and the capacitor C52 in sequence. The RING pin of the second master control chip U4 is also connected to the SRINGDC pin of the second master control chip U4 via the resistor R58. The RING pin of the second master control chip U4 is also connected to the SRINGAC pin of the second master control chip U4 via the resistor R55 and the capacitor C57 in sequence. One end of the resistor R49 is connected between the resistor R46 and the capacitor C52, and the other end is connected between the resistor R55 and the capacitor C57 to form a power supply circuit.

[0070] One end of capacitor R65 is connected between resistor R59 and resistor R60, and the other end is connected between resistor R66 and resistor R64; one end of capacitor R66 is connected between resistor R60 and resistor R61, and the other end is connected between resistor R64 and resistor R67; one end of resistor R50 is connected between resistor R59 and resistor R60, and the other end is connected to the STIPC pin of the second main control chip U4 via resistor R69; one end of resistor R68 is connected between resistor R66 and resistor R64, and the other end is connected to the SRINGC pin of the second main control chip U4 via resistor R70; one end of capacitor C61 is connected between resistor R60 and resistor R61, and the other end is grounded; one end of capacitor C71 is connected between resistor R64 and resistor R67, and the other end is grounded.

[0071] Terminal A1 of rectifier diode DB8 is connected between resistors R67 and R65, terminal A2 is connected between resistors R61 and R62, and terminal K is grounded. In this embodiment, the preferred model of rectifier diode DB8 is BAV70. Pin 1 of bidirectional diode TVS3 is connected between resistor R62 and the TIP pin of fax connector J2, and pin 2 is grounded. Pin 1 of bidirectional diode TVS2 is connected between resistor R65 and the RING pin of fax connector J2, and pin 2 is grounded.

[0072] Please refer to Figure 5The second power supply sub-circuit 22 includes a second boost unit 22A and a second voltage stabilizing unit 22B. The second boost unit 22A and the second voltage stabilizing unit 22B are both connected to the battery voltage. The second boost unit 22A is used to boost the battery voltage to a second line voltage. The second regulated power supply is used to stabilize the battery voltage and output a second regulated voltage to power the fax data sub-circuit 21.

[0073] The second boost unit 22A is electrically connected to the DCDRV, SDCH, and SDCL pins of the second master chip U4. These pins function as a second line voltage driver, allowing the second boost unit 22A to be controlled by the second master chip U4. The second master chip U4 then controls the second boost unit 22A to boost the battery voltage to the second line voltage at the appropriate time. The second boost unit 22A has a second boost output terminal (i.e., LINE_48V_F) for outputting the second line voltage. This second boost output terminal is electrically connected to the VBAT pin of the second master chip U4 and, via resistor R71, to the SVBAT pin of the second master chip U4.

[0074] In this embodiment, the second boost unit 22A includes a resistor R47, a resistor R48, a resistor R54, a resistor R63, a resistor R72, a resistor R73, a resistor R74, a resistor R75, a resistor R76, a resistor R77, a resistor R78, a capacitor C53, a capacitor C55, a capacitor C56, a capacitor C58, a capacitor C59, a capacitor C60, a capacitor C62, a capacitor C63, a capacitor C64, a capacitor C69, a capacitor C70, a capacitor C73, a capacitor C74, an inductor L2, a transistor Q2, a rectifier diode DB6, a rectifier diode DB7, a rectifier diode DB9, and a rectifier diode DB10. In this embodiment, the transistor Q2 is preferably NTR5198, and the rectifier diodes DB6, DB7, DB9, and DB10 are preferably BAV70.

[0075] Specifically, a voltage battery is connected via the battery voltage input terminal (ie, VBAT), and the battery voltage input terminal is grounded via capacitors C59, C56, C60, and C62, respectively, to filter the connected battery voltage. The battery voltage input terminal is connected to the drain of the transistor Q2 via the inductor L2. A resistor R54 and a capacitor C55 are connected in series and connected to both ends of the inductor L2. The gate of the transistor Q2 is connected to the DCDRV pin of the second master control chip U4 and is also grounded via a resistor R63. The source of the transistor Q2 is grounded via resistors R73, R74, R75, R76, and R77, respectively. The source of the transistor Q2 is also connected to the SDCH pin of the second master control chip U4 via a resistor R72. The SDCL pin of the second master chip U4 is grounded via a resistor R78. The SDCL pin of the second master chip U4 is also connected to the SDCH pin of the second master chip U4 via a capacitor C73. The DCFF pin of the second master chip U4 is grounded via a capacitor C74. The second master chip U4 sends a drive signal to drive the transistor Q2 on and off to achieve control of the second boost unit 22A. The drain of transistor Q2 is also connected to one end of capacitor C64, the other end of capacitor C64 is connected to the K end of rectifier diode DB9 and the A1 and A2 ends of rectifier diode DB10, the K end of rectifier diode DB10 is connected to the source of transistor Q2, the A1 and A2 ends of rectifier diode DB94 are connected and then grounded through capacitor C69, and the A1 and A2 ends of rectifier diode DB9 are connected and then connected to the K end of rectifier diode DB7; the drain of transistor Q2 is connected to one end of capacitor C53, the other end of capacitor C53 is connected to the K end of rectifier diode DB6 The A1 end of the rectifier diode DB6 is connected to its A2 end, and then connected to the K end of the rectifier diode DB7 through capacitors C63 and C58 respectively. After the A1 end of the rectifier diode DB6 is connected to its A2 end, it also outputs the second line voltage in sequence through resistors R48 and R47 to form a second boost output end connected to the second main control chip U4; one end of the capacitor C70 is connected between the resistor R48 and the resistor R47, and the other end is grounded; the battery voltage is boosted by the cooperation of multiple rectifier diodes to output the second line voltage.

[0076] The second voltage stabilizing unit 22B is electrically connected to and controlled by the protocol processing circuit 30. The protocol processing circuit 30 can timely control the second voltage stabilizing unit 22B to stabilize the battery voltage and stably output a second stable voltage. The second voltage stabilizing unit 22B has a second regulated voltage output terminal (i.e., SLIC_3V3_F) that outputs the second stable voltage. The second regulated voltage output terminal is connected to the VDD pin, VDDA pin, VDDREG pin, and VDDHV pin of the second main control chip U4 through a second peripheral filtering unit.

[0077] In this embodiment, the second voltage stabilizing unit 22B includes a voltage stabilizing chip U5 , a resistor R83 , a resistor R84 , a resistor R85 , a capacitor C78 , a capacitor C79 , and a capacitor C80 .

[0078] Specifically, the VIN pin of the voltage regulator chip U5 is connected to the battery voltage, and the VIN pin of the voltage regulator chip U5 is grounded via capacitor C78, which is a filter capacitor; the GND pin of the voltage regulator chip U5 is grounded to form a loop to ensure the normal operation of the voltage regulator chip U5. The EN pin of the voltage regulator chip U5 is connected to the protocol processing circuit 30 to receive the enable signal sent by the protocol processing circuit 30, so as to realize the control of the second voltage stabilizing unit 22B by the protocol circuit, and then output the second stable voltage; the EN pin of the voltage regulator chip U5 is also grounded via resistor R84, which is a current limiting resistor. The VOUT pin of the voltage regulator chip U5 is grounded via resistor R83 and resistor R85 in turn, and the FB / BP pin of the voltage regulator chip U5 is connected between resistor R83 and resistor R85. The FB / BP pin of the voltage regulator chip U5 collects the voltage division between resistor R83 and resistor R85 and provides feedback on the second stable voltage output by the voltage regulator chip U5 to ensure stable voltage output. The VOUT pin of the voltage stabilizing chip U5 is also grounded via capacitors C79 and C80 respectively. The VOUT pin of the voltage stabilizing chip U5 forms a second voltage stabilizing output terminal to output a second stable voltage. Capacitors C79 and C80 are filter capacitors.

[0079] The protocol processing circuit 30 connects to the wireless communication circuit 40 via a USB or UART interface, providing wireless data sharing and transmission (TETHERING) for the protocol processing circuit 30, allowing it to access the wireless internet. The protocol processing circuit 30 runs the SIP protocol stack, the T.30 fax protocol stack, and the T.38 fax protocol stack. In a specific implementation, the protocol processing circuit 30 can be a standalone electronic component unit or a software unit running within the wireless communication circuit 40 that includes the SIP protocol stack and the T.30 / T.38 fax protocol stack.

[0080] Please refer to Figure 6 The protocol processing circuit 30 includes a protocol chip U8 and a third peripheral filtering unit connected to the protocol chip U8. In this embodiment, the model of the protocol chip U8 is preferably T113. Since this embodiment only involves the circuit architecture related to data transmission and does not involve program processing, the specific process of data processing by the protocol chip U8 is existing technology and can be directly purchased, so this embodiment will not be described in detail.

[0081] The VBAT0 and VBAT1 pins of protocol chip U8 are connected to a battery voltage. The VDD1V85 pin of protocol chip U8 is connected to a first external voltage, and the VDD2V8 pin of protocol chip U8 is connected to a second external voltage. In this embodiment, the first external voltage is preferably 1.85V, and the second external voltage is preferably 2.8V. The GND, GND1, and GND2 pins of protocol chip U8 are all grounded to form a power supply circuit, ensuring the normal operation of protocol chip U8. The SPI_CLK, SPI_CSN, SPI_MISO, and SPI_MOSI pins of protocol chip U8 form the second fax data identification terminal of protocol processing circuit 30 and are electrically connected to the SCLK, CSB, SPI_MOSI, and SPI_MISO pins of the second main control chip U4, respectively, to transmit fax command data and establish a SIP session when appropriate. The PCM_SYNC, PCM_CLK, PCM_IN, and PCM_OUT pins of the protocol chip U8 form the second fax data communication terminal of the protocol processing circuit 30 and are electrically connected to the PCLK, FSYNC, PCM_MOSI, and PCM_MISO pins of the second main control chip U4, respectively, to transmit uplink and downlink fax data. The GPIO20 pin of the protocol chip U8 is electrically connected to the second voltage regulator unit 22B, and specifically to the EN pin of the voltage regulator chip U5, to send an enable signal to the second voltage regulator unit 22B. The GPIO26 pin of the protocol chip U8 is connected to the RESET pin of the second main control chip U4 to provide a reset signal to the second main control chip U4. The EXTING pin of the protocol chip U8 is electrically connected to the INT pin of the second main control chip U4 to provide an interrupt signal to the second main control chip U4. The USBDP and USBDN pins of the protocol chip U8 are connected to the wireless communication circuit 40 using a USB communication interface to access the wireless internet.

[0082] The third peripheral filtering unit is used to filter the signal input to the protocol chip U8. In this embodiment, the third peripheral filtering unit includes capacitors C102, C103, C104, and C108. The VBAT0 and VBAT1 pins of the protocol chip U8 are connected to ground via capacitor C104, the VDD1V85 pins of the protocol chip U8 are grounded via capacitor C102, the VDD2V8 pins of the protocol chip U8 are grounded via capacitor C103, and the VCORE pin of the protocol chip U8 is grounded via capacitor C108 to smooth the power signal input to the protocol chip U8.

[0083] In this embodiment, the wireless communication circuit 40 provides 4G or 5G wireless network access capability, provides wireless data sharing transmission (TETHERING) through a USB or UART peripheral interface, and has a PCM digital voice interface and an SPI interface to provide corresponding transmission of voice / fax data and control commands.

[0084] Please refer to Figure 7 The wireless communication circuit 40 includes a communication chip U3 and a fourth peripheral filtering unit connected to the communication chip U3. In this embodiment, the communication chip U3 is preferably an EC25. Since this embodiment only involves the circuit architecture related to data transmission and does not involve program processing, the specific data processing process of the communication chip U3 is conventional and can be purchased directly, so this embodiment will not be described in detail.

[0085] The VBAT0, VBAT1, and VBAT2 pins of communication chip U3 are connected to the battery voltage. The USB_VBUS0, USB_VBUS1, and USB_VBUS2 pins of communication chip U3 are connected to the USB line voltage via the USB communication interface. The VDD1V8 pin of communication chip U3 is a third external voltage. The BAT_P and BAT_M pins of communication chip U3 are connected to the battery voltage control signal. The GND1, GND2, and GND3 pins of communication chip U3 are all grounded to form a power supply circuit to ensure the normal operation of communication chip U3. The SPI_CLK, SPI_CS, SPI_MISO, and SPI_MOSI pins of communication chip U3 form the second voice data recognition terminal of wireless communication circuit 40 and are respectively electrically connected to the SCLK, CSB, SPI_MOSI, and SPI_MISO pins of the first main control chip U2 to transmit voice control command data and establish voice calls in a timely manner. The PCM_SYNC, PCM_CLK, PCM_IN, and PCM_OUT pins of the communication chip U3 form the second voice data communication terminal of the wireless communication circuit 40 and are electrically connected to the FSYNC, PCLK, PCM_MOSI, and PCM_MISO pins of the first master control chip U2, respectively, to transmit uplink and downlink voice data. The GPIO52 pin of the communication chip U3 is electrically connected to the first voltage stabilizing unit 12B and is specifically connected to the EN pin of the voltage stabilizing chip U1 to send an enable signal to the first voltage stabilizing unit 12B. The GPIO53 pin of the communication chip U3 is connected to the RESET pin of the first master control chip U2 to provide a reset signal to the first master control chip U2. The EINT pin of the communication chip U3 is connected to the INT pin to provide an interrupt signal to the first master control chip U2. The USB_DP and USB_DN pins of communication chip U3 utilize a USB communication interface and protocol processing for fax data transmission. Specifically, the USB_DP pin of communication chip U3 is connected to the USBDP pin of protocol chip U8, and the USB_DN pin of communication chip U3 is connected to the USBDN pin of protocol chip U8, enabling protocol processing circuit 30 to access the wireless internet. Furthermore, the ANT0, ANT1, and ANT2 pins of communication chip U3 function as wireless signal transceivers, transmitting wireless signals via an antenna to achieve wireless communication with the network.

[0086] The fourth peripheral filtering unit is used to filter signals input to the communication chip U3. In this embodiment, the fourth peripheral filtering unit includes capacitors C18, C19, C20, C21, C26, C27, C28, C29, and C107. The VBAT0, VBAT1, and VBAT2 pins of the communication chip U3 are connected to ground via capacitors C18, C19, C20, and C21, respectively. The USB_VBUS0, USB_VBUS1, and USB_VBUS2 pins of the communication chip U3 are connected to ground via capacitors C26, C27, C28, and C29, respectively. The VDD1V8 pins of the communication chip U3 are grounded via capacitor C107 to smooth the power signals input to the communication chip U3.

[0087] In this embodiment, when voice channel A is connected to an external G3 analog fax machine 60, during the Volte voice call, the wireless communication circuit 40 negotiates with the wireless network IMS to limit the wireless transmission voice coding format to G.711, thereby establishing Volte voice communication with a remote T.30 fax device. The fax message analog signal from the G3 analog fax machine 60 is input via the first two-wire SLIC interface to the voice data subcircuit 11, where it undergoes analog-to-digital modulation (A / D) into a PCM digital voice signal. The signal is then input via the first PCM interface to the wireless communication circuit 40, where it is further encoded into a G.711 digital voice signal. The signal is then transmitted via the wireless network IMS to the remote T.30 fax device for T.30 fax message parsing, thereby establishing a G.711-encoded Volte voice channel between the G3 analog fax machine 60 and the remote T.30 fax device. Furthermore, T.30 point-to-point fax communication using G.711 passthrough is implemented over the Volte voice channel.

[0088] The utility model discloses a wireless network adapter for dual-channel parallel communication of voice and fax, which is provided with a first data processing circuit 10 having a two-wire FXS standard TIP / RING interface for connecting to an external analog telephone 50 and a second data processing circuit 20 having a two-wire PSTN FXS standard TIP / RING interface for connecting to an external G3 analog fax machine 60. The first data processing circuit 10 and the second data processing circuit 20 are provided with a PCM digital voice interface and an analog / digital voice codec CODEC submodule, which are respectively connected to a wireless communication circuit 40 and a protocol processing circuit 30. The independent channel VOLTE voice service and T.38 fax service can be run in parallel based on the wireless network. The services of the two channels do not interfere with each other, and it is beneficial for users to achieve better tariff plans by selecting appropriate service channels for communication.

Claims

1. A wireless network adapter with dual-channel parallel communication for voice and fax, characterized in that: It includes a parallel voice channel and a fax channel and a wireless communication circuit connected to both the voice channel and the fax channel; The voice channel includes a first data processing circuit for communicating with an analog telephone, a first voice command recognition terminal of the first data processing circuit being electrically connected to a second voice command recognition terminal of the wireless communication circuit to implement transmission of voice control commands, and a first voice data communication terminal of the first data processing circuit being electrically connected to a second voice data communication terminal of the wireless communication circuit to implement transmission of voice data; The fax channel includes a second data processing circuit and a protocol processing circuit for communicating with a G3 analog fax machine. A first fax instruction recognition terminal of the second data processing circuit is electrically connected to a second fax instruction recognition terminal of the protocol processing circuit to implement the transmission of T.30 fax control instructions. A first fax data communication terminal of the second data processing circuit is electrically connected to a second fax data communication terminal of the protocol processing circuit to implement the transmission of T.30 fax message data. The protocol processing circuit runs the T.30 fax protocol stack and the T.38 fax protocol stack to complete the encoding and decoding of the fax message data format, and uses a USB or UART communication interface to connect to the wireless communication circuit to implement wireless data sharing and transmission, thereby implementing T.38 fax communication with a remote destination fax device.

2. The wireless network adapter for voice and fax dual-channel parallel communication according to claim 1, characterized in that: The first data processing circuit includes a voice data subcircuit connected to the analog telephone and a first power supply subcircuit electrically connected to the voice data subcircuit and supplying power to the voice data subcircuit; the input end of the voice data subcircuit is electrically connected to the analog telephone via a first two-wire SLIC interface to achieve voice analog signal transmission; the output end of the voice data subcircuit has a first SPI interface, the first SPI interface forms the first voice command recognition end to communicate with the second voice command recognition end of the wireless communication circuit, the voice control command analog signal of the analog telephone is modulated into voice control command data via the first two-wire SLIC interface and the voice data subcircuit, and then parsed by the wireless communication circuit via the first SPI interface to achieve establishment or disconnection of a Volte voice call; the voice data subcircuit is electrically connected to the analog telephone via a first two-wire SLIC interface to achieve transmission of voice analog signals; the output end of the voice data subcircuit has a first SPI interface, the first SPI interface forms the first voice command recognition end to communicate with the second voice command recognition end of the wireless communication circuit, the voice control command analog signal of the analog telephone is modulated into voice control command data via the first two-wire SLIC interface and the voice data subcircuit, and then parsed by the wireless communication circuit via the first SPI interface to achieve establishment or disconnection of a Volte voice call; The output end of the data subcircuit further includes a first PCM interface. The first PCM interface forms the first voice data communication end for communication with the second voice data communication end of the wireless communication circuit. After the Volte voice call is established, the analog uplink voice analog signal of the analog telephone is input into the voice data subcircuit via the first two-wire SLIC interface, undergoes analog-to-digital modulation to be converted into a PCM digital voice signal, and then is input into the wireless communication circuit via the first PCM interface. The wireless communication circuit encodes the signal into the uplink voice data of the Volte voice call. The downlink voice data of the Volte voice call is decoded into a PCM digital voice signal by the wireless communication circuit, transmitted to the voice data subcircuit via the first PCM interface, undergoes digital-to-analog demodulation to be converted into a downlink voice analog signal, and then is output from the analog telephone via the first two-wire SLIC interface.

3. The wireless network adapter for voice and fax dual-channel parallel communication according to claim 2, characterized in that: The voice data subcircuit includes a first main control chip U2, an analog telephone connector J1, a first peripheral filter unit electrically connected to the first main control chip U2, and a first interface filter unit electrically connected between the first main control chip U2 and the analog telephone connector J1. The first peripheral filter unit is used to filter signals connected to the first main control chip U2, and the first interface filter unit is used to filter signals connected to the analog telephone connector J1 to the first main control chip U2. The model of the first main control chip U2 is SI32185. The TIP pin and RING pin of the first main control chip U2 form the first two-wire SLIC interface and the TIP pin and RING pin of the first main control chip U2 are electrically connected to the TIP pin and RING pin of the analog telephone connector J1 via the first interface filtering unit, and the analog telephone connector J1 is connected to the analog telephone; the SCLK pin, CSB pin, SPI_MISO pin and SPI_MOSI pin of the first main control chip U2 form the first SPI interface to communicate with the second voice command recognition end of the wireless communication circuit; the PCLK pin, FSYNC pin, PCM_MISO pin and PCM_MOSI pin of the first main control chip U2 form the first PCM interface and communicate with the second voice data communication end of the wireless communication circuit via resistor R8, resistor R12, resistor R13 and resistor R15 respectively.

4. The wireless network adapter for voice and fax dual-channel parallel communication according to claim 3, characterized in that: The first power supply sub-circuit includes a first boost unit and a first voltage stabilizing unit, the first boost unit and the first voltage stabilizing unit are both connected to the battery voltage, the first boost unit is electrically connected to the DCDRV pin, SDCH pin and SDCL pin of the first main control chip U2 and is controlled by the first main control chip U2, the first boost unit is used to boost the battery voltage to a first line voltage, the first boost unit has a first boost output end for outputting the first line voltage, the first boost output end is electrically connected to the VBAT pin of the first main control chip U2 and is connected to the first main control chip via a resistor R28. The first voltage stabilizing unit is electrically connected to the SVBAT pin of the first main control chip U2; the first voltage stabilizing unit is electrically connected to the wireless communication circuit and is controlled by the wireless communication circuit, the first voltage stabilizing unit is used to stabilize the battery voltage and output a first stable voltage, the first voltage stabilizing unit has a first voltage stabilizing output end that outputs the first stable voltage, the first voltage stabilizing output end is connected to the VDD pin, VDDA pin, VDDREG pin and VDDHV pin of the first main control chip U2 through the first peripheral filtering unit; the RESET pin and INT pin of the first main control chip U2 are both electrically connected to the wireless communication circuit.

5. The wireless network adapter for voice and fax dual-channel parallel communication according to claim 4, characterized in that: The wireless communication circuit includes a communication chip U3 and a fourth peripheral filtering unit connected to the communication chip U3, wherein the fourth peripheral filtering unit is used to filter the signal connected to the communication chip U3; the model of the communication chip U3 is EC25; The VBAT0 pin, VBAT1 pin and VBAT2 pin of the communication chip U3 are connected to the battery voltage, and the USB_VBUS0 pin, USB_VBUS1 pin and USB_VBUS2 pin of the communication chip U3 are connected to the USB line voltage via the USB communication interface; the SPI_CLK pin, SPI_CS pin, SPI_MISO pin and SPI_MOSI pin of the communication chip U3 form the second voice data recognition end of the wireless communication circuit and are respectively electrically connected to the SCLK pin, CSB pin, SPI_MOSI pin and SPI_MISO pin of the first main control chip U2; the PCM_SYNC pin, The PCM_CLK pin, PCM_IN pin and PCM_OUT pin form the second voice data communication end of the wireless communication circuit and are electrically connected to the FSYNC pin, PCLK pin, PCM_MOSI pin and PCM_MISO pin of the first main control chip U2 respectively; the GPIO52 pin of the communication chip U3 is electrically connected to the first voltage stabilizing unit; the GPIO53 pin and EINT pin of the communication chip U3 are electrically connected to the RESET pin and INT pin of the first main control chip U2 respectively; the USB_DP pin and USB_DN pin of the communication chip U3 are provided to the protocol processing circuit using a USB communication interface to realize wireless data sharing and transmission.

6. The wireless network adapter for voice and fax dual-channel parallel communication according to claim 5, characterized in that: The second data processing circuit includes a fax data subcircuit connected to a G3 analog fax machine and a second power supply subcircuit electrically connected to the fax data subcircuit and providing power to the fax data subcircuit. The input end of the fax data subcircuit transmits analog signals of fax control commands and fax voice to the G3 analog fax machine via a second two-wire SLIC interface. The output end of the fax data subcircuit has a second SPI interface, which forms the first fax command recognition end for communication with the second fax command recognition end of the protocol processing circuit. The fax command analog signal from the G3 analog fax machine is transmitted via the second two-wire SLIC interface and modulated into fax command data by the fax data subcircuit. The signal is then parsed by the protocol processing circuit via the second SPI interface. The protocol processing circuit then runs a SIP protocol stack to extract the user identification number of the remote destination T.38 fax device contained in the fax command data. A SIP terminal session is then established between the protocol processing circuit and the remote destination T.38 fax device via the wireless communication circuit. The fax data subcircuit also has a second PCM interface, which forms the first fax data communication end for communication with the remote destination T.38 fax device. The second fax data communication end of the protocol processing circuit communicates with the second fax data communication end of the protocol processing circuit. After the SIP terminal session is established, the uplink fax voice analog signal of the G3 analog fax machine is input through the second two-wire SLIC interface and modulated into a PCM digital voice signal by the fax data sub-circuit. The uplink fax voice analog signal is then input into the protocol processing circuit through the second PCM interface. The protocol processing circuit runs the T.30 fax protocol stack to encode the PCM digital voice signal into T.30 fax message data in HDLC data frame format. The protocol processing circuit further runs the T.38 fax protocol stack to convert the T.30 fax message data into T.30 fax message data in HDLC data frame format. The message is encoded as uplink fax message data in IFP format and transmitted to a remote destination T.38 fax device based on the SIP terminal session; the downlink fax data transmitted by the remote destination T.38 fax device is received by the protocol processing circuit and decoded into T.30 fax message data in HDLC data frame format by running the T.38 fax protocol stack, and further decoded into PCM digital voice signal by running the T.30 fax protocol stack. The signal is input through the second PCM interface, demodulated into a downlink fax voice analog signal by the fax data sub-circuit, and then output to the G3 analog fax machine through the second two-wire SLIC interface.

7. The wireless network adapter for voice and fax dual-channel parallel communication according to claim 6, characterized in that: The fax data subcircuit includes a second main control chip U4, a fax connector J2, a second peripheral filter unit electrically connected to the second main control chip U4, and a second interface filter unit electrically connected between the second main control chip U4 and the fax connector J2. The second peripheral filter unit is used to filter signals connected to the second main control chip U4, and the second interface filter unit is used to filter signals connected to the fax connector J2 from the second main control chip U4. The model of the second main control chip U4 is SI32185. The TIP pin and RING pin of the second main control chip U4 form a second two-wire SLIC interface and are electrically connected to the TIP pin and RING pin of the fax machine connector J2 via the second interface filter unit, and the fax machine connector J2 is connected to the G3 analog fax machine; the SCLK pin, CSB pin, SPI_MISO pin and SPI_MOSI pin of the second main control chip U4 form a second SPI interface that communicates with the second fax instruction recognition end of the protocol processing circuit; the PCLK pin, FSYNC pin, PCM_MISO pin and PCM_MOSI pin of the second main control chip U4 form a second PCM interface and communicate with the second fax data communication end of the protocol processing circuit via resistors R51, R52, R56 and R53 respectively.

8. The wireless network adapter for voice and fax dual-channel parallel communication according to claim 7, characterized in that: The second power supply sub-circuit includes a second boost unit and a second voltage stabilizing unit, the second boost unit and the second voltage stabilizing unit are both connected to the battery voltage, the second boost unit is electrically connected to the DCDRV pin, SDCH pin and SDCL pin of the second main control chip U4 and is controlled by the second main control chip U4, the second boost unit is used to boost the battery voltage to a second line voltage, the second boost unit has a second boost output end that outputs the second line voltage, the second boost output end is electrically connected to the VBAT pin of the second main control chip U4 and is connected to the second main control chip through a resistor R71. The second voltage stabilizing unit is electrically connected to the SVBAT pin of the second main control chip U4; the second voltage stabilizing unit is electrically connected to the protocol processing circuit and is controlled by the protocol processing circuit, the second voltage stabilizing unit is used to stabilize the battery voltage and output a second stable voltage, the second voltage stabilizing unit has a second voltage stabilizing output end that outputs the second stable voltage, the second voltage stabilizing output end is connected to the VDD pin, VDDA pin, VDDREG pin and VDDHV pin of the second main control chip U4 through the second peripheral filtering unit; the RESET pin and INT pin of the second main control chip U4 are both electrically connected to the protocol processing circuit.

9. The wireless network adapter for voice and fax dual-channel parallel communication according to claim 8, characterized in that: The protocol processing circuit includes a protocol chip U8 and a third peripheral filtering unit connected to the protocol chip U8, the third peripheral filtering unit being configured to filter signals input to the protocol chip U8; the model of the protocol chip U8 is T113; the protocol processing circuit is defined as an independent electronic component assembly unit, or as a software unit running within the wireless communication circuit and including a SIP protocol stack and a T.30 / T.38 fax protocol stack; The VBAT0 pin and VBAT1 pin of the protocol chip U8 are connected to the battery voltage, the VDD1V85 pin of the protocol chip U8 is connected to the first external voltage, and the VDD2V8 pin is connected to the second external voltage; the SPI_CLK pin, SPI_CSN pin, SPI_MISO pin and SPI_MOSI pin of the protocol chip U8 form the second fax data recognition end of the protocol processing circuit and are respectively electrically connected to the SCLK pin, CSB pin, SPI_MOSI pin and SPI_MISO pin of the second main control chip U4; the PCM_SYNC pin, PCM_CLK pin, PCM_IN pin of the protocol chip U8 The PCM_OUT pin forms the second fax data communication terminal of the protocol processing circuit and is respectively electrically connected to the PCLK pin, FSYNC pin, PCM_MOSI pin and PCM_MISO pin of the second main control chip U4; the GPIO20 pin of the protocol chip U8 is electrically connected to the second voltage stabilizing unit; the GPIO26 pin and EXTING pin of the protocol chip U8 are respectively electrically connected to the RESET pin and INT pin of the second main control chip U4; the USBDP pin and USBDN pin of the protocol chip U8 are respectively electrically connected to the USB_DP pin and USB_DN pin of the communication chip U3 using a USB communication interface.

10. The wireless network adapter for voice and fax dual-channel parallel communication according to any one of claims 2 to 9, characterized in that: When the voice channel is connected to an external G3 analog fax machine, during the Volte voice call, the wireless communication circuit negotiates with the wireless network end IMS to limit the wireless transmission voice coding format to G.711, thereby establishing Volte voice communication with a remote destination T.30 fax device. The fax message analog signal of the G3 analog fax machine is input into the voice data subcircuit via the first two-wire SLIC interface, undergoes analog-to-digital modulation into a PCM digital voice signal, and is then input into the wireless communication circuit via the first PCM interface. The wireless communication circuit then encodes the signal into a G.711 format digital voice signal, which is then transmitted via the wireless network end IMS to the remote destination T.30 fax device for T.30 fax message parsing. This establishes a Volte voice channel in the G.711 coding format between the G3 analog fax machine and the remote destination T.30 fax device, and implements T.30 point-to-point fax communication using G.711 passthrough based on the Volte voice channel.

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