Clock management chip, chip management system and electronic device

Abstract

The application provides a clock management chip, a chip management system and electronic equipment, and the chip comprises: an antenna signal processing module; a protocol processing module connected with the antenna signal processing module, used for receiving an Ethernet synchronization source clock signal, a PTP clock signal, a 1PPS clock signal and an external clock source signal, and outputting a transition clock signal according to the Ethernet synchronization source clock signal, the PTP clock signal, the 1PPS clock signal and the external clock source signal; and a clock generation module connected with the PTP protocol processing module, used for processing the clock signal and outputting a target clock signal correspondingly. The application adopts the same chip and architecture to select and process the Ethernet synchronization source clock signal and the external clock source signal, avoids the problem that there is a large delay in signal transmission caused by processing different clock source signals in different chips, reduces the error probability of signal transmission and improves the accuracy of signal transmission.

Description

Clock management chips, chip management systems and electronic devices Technical Field

[0001] This invention relates to the field of mobile communication technology, and in particular to a clock management chip, a chip management system, and an electronic device. Background Technology

[0002] Fifth-generation mobile communication technology, or 5G, is a new generation of broadband mobile communication technology characterized by high speed, low latency, and massive connectivity, enabling the network infrastructure for interconnecting people, machines, and things. However, since 5G mostly uses the mmW band, which has a shorter wavelength, its signal coverage is limited. 5G networks rely solely on macro base stations for coverage, resulting in low adaptability. 5G small cells (5G low-power wireless access nodes), with their relative advantages, can achieve continuous and wide-area 5G signal coverage.

[0003] However, the clock module in the small base station is mostly composed of discrete components. Too many discrete components and discrete signals will greatly reduce the stability of the entire base station communication during communication. For example, when transmitting and processing synchronization source clock signals, different synchronization source clock signals need to be processed by different chips and architectures, which will cause a certain delay in the signal transmission process, thereby increasing the probability of signal transmission errors. Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art.

[0005] Therefore, the first objective of this invention is to provide a clock management chip that integrates an antenna signal processing module and a protocol processing module within the clock management chip. This enables the clock management chip to perform gating processing on Ethernet synchronization source clock signals and external clock source signals. In other words, it uses the same chip and architecture to perform gating processing on Ethernet synchronization source clock signals and external clock source signals, avoiding the problem of large signal transmission delays caused by processing different clock source signals in different chips. This reduces the probability of signal transmission errors and improves the accuracy of signal transmission.

[0006] Therefore, a second objective of this invention is to provide a chip management system.

[0007] Therefore, a third objective of the present invention is to provide an electronic device.

[0008] To achieve the above objectives, an embodiment of the first aspect of the present invention provides a clock management chip, which includes: an antenna signal processing module for receiving a radio frequency synchronization source clock signal and outputting a 1PPS clock signal according to the radio frequency synchronization source clock signal; a protocol processing module connected to the antenna signal processing module for receiving an Ethernet synchronization source clock signal, a PTP clock signal, the 1PPS clock signal, and an external clock source signal, and outputting a transition clock signal according to the Ethernet synchronization source clock signal, the PTP clock signal, the 1PPS clock signal, and the external clock source signal; and a clock generation module connected to the protocol processing module for processing the clock signal and outputting a target clock signal accordingly.

[0009] According to the clock management chip of the present invention, by setting the antenna signal processing module and the protocol processing module in the clock management chip, the clock management chip can perform gating processing on the Ethernet synchronization source clock signal and the external clock source signal. That is, the same chip and architecture are used to perform gating processing on the Ethernet synchronization source clock signal and the external clock source signal, avoiding the problem of large delay in signal transmission caused by processing different clock source signals in different chips, thereby reducing the probability of signal transmission errors and improving the accuracy of signal transmission.

[0010] In some embodiments, the target clock signal includes a target adjustment clock signal, and the clock generation module includes: a plurality of clock channels, one of which is connected to a clock processing chip for sending the target adjustment clock signal to the clock processing chip to form a clock synchronization closed loop.

[0011] In some embodiments, the target clock signal further includes a target synchronization clock signal, and the remaining clock channels are respectively connected to the clock processing chip and the system chip, for synchronously sending the target synchronization clock signal to the clock processing chip and the system chip.

[0012] In some embodiments, the clock signal includes a synchronization clock signal and an adjustment clock signal. The protocol processing module includes: a synchronization source signal receiving unit for receiving the Ethernet synchronization source clock signal and the PTP clock signal; and a gating processing unit connected to the synchronization source signal receiving unit for gating the Ethernet synchronization source clock signal and the external clock source signal, and outputting the synchronization clock signal and the adjustment clock signal.

[0013] In some embodiments, the synchronization source signal receiving unit includes: a numerically controlled oscillator, configured to receive the Ethernet synchronization source clock signal and the PTP clock signal, determine a delay signal based on the Ethernet synchronization source clock signal and the PTP clock signal, and optimize the delay signal to obtain an optimized delay signal.

[0014] In some embodiments, the gating processing unit includes: a clock signal processor, configured to receive the external clock source signal and the 1PPS clock signal, and output a valid clock source signal according to the external clock source signal and the 1PPS clock signal; a data selector, connected to the numerically controlled oscillator and the clock signal processor respectively, configured to receive the optimized delay signal and / or the valid clock source signal, and gating the optimized delay signal and / or the valid clock source signal to output an initial synchronization clock signal and an initial adjustment clock signal; and a low-power filter, connected to the data selector, configured to filter the initial synchronization clock signal and the initial adjustment clock signal to output the synchronization clock signal and the adjustment clock signal.

[0015] In some embodiments, the antenna signal processing module includes: an analog signal processing unit for receiving the radio frequency synchronization source clock signal and outputting a digital signal; and a digital signal processing unit connected to the analog signal processing unit for receiving the digital signal and outputting a 1PPS clock signal based on the digital signal.

[0016] In some embodiments, the analog signal processing unit includes: a low-noise amplifier, which receives the radio frequency synchronization source clock signal, amplifies the radio frequency synchronization source clock signal, and outputs an initial radio frequency synchronization source clock amplified signal; and a front-end processor, connected to the low-noise amplifier, which processes the initial radio frequency synchronization source clock amplified signal and outputs a digital signal.

[0017] In some embodiments, the digital signal processing unit includes: a digital filter connected to the analog signal processing unit for processing the digital signal and outputting a filtered digital signal; and a GNSS processor connected to the digital filter for generating the 1PPS clock signal based on the filtered digital signal.

[0018] In some embodiments, the clock signal includes a synchronous clock signal and an adjustable clock signal. The clock generation module further includes: a plurality of phase-locked loop subunits for receiving the synchronous clock signal and the adjustable clock signal, and generating a set frequency synchronous clock signal and an adjustable clock signal; and a differential numerator unit connected to the plurality of phase-locked loop subunits for receiving the set frequency synchronous clock signal and the adjustable clock signal, and outputting the target synchronous clock signal and the target adjustable clock signal.

[0019] In some embodiments, the protocol processing module and the antenna signal processing module are integrated in the clock management chip.

[0020] To achieve the above objectives, a second aspect of the present invention provides a chip management system comprising: an Ethernet clock synchronization transmitter for transmitting an Ethernet synchronization source clock signal; an antenna clock synchronization transmitter for transmitting an radio frequency synchronization source clock signal; a clock management chip as described in the above embodiments, connected to both the Ethernet clock synchronization transmitter and the antenna clock synchronization transmitter, for receiving the Ethernet synchronization source clock signal and the radio frequency synchronization source clock signal, and outputting a 1PPS clock signal and a target clock signal accordingly based on the Ethernet synchronization source clock signal and the radio frequency synchronization source clock signal; an embedded neural network processing chip, connected to both the Ethernet clock synchronization transmitter and the clock management chip, for receiving the target clock signal and the 1PPS clock signal, and adjusting the internal clock signal of the embedded neural network processing chip according to the target clock signal to form a clock synchronization closed loop; and a baseband system chip, connected to both the embedded neural network processing chip and the clock management chip, for receiving the target clock signal and the 1PPS clock signal emitted by the embedded neural network processing chip.

[0021] According to the chip management system of the present invention, by setting the antenna signal processing module and the protocol processing module in the clock management chip, the clock management chip can perform gating processing on the Ethernet synchronization source clock signal and the external clock source signal. That is, the same chip and architecture are used to perform gating processing on the Ethernet synchronization source clock signal and the external clock source signal, avoiding the problem of large delay in signal transmission caused by processing different clock source signals in different chips, thereby reducing the probability of signal transmission errors and improving the accuracy of signal transmission.

[0022] To achieve the above objectives, a third aspect of the present invention provides an electronic device comprising: the chip management system described in the above embodiments.

[0023] According to the electronic device of the present invention, by setting the antenna signal processing module and the protocol processing module in the clock management chip, the clock management chip can perform gating processing on the Ethernet synchronization source clock signal and the external clock source signal. That is, the same chip and architecture are used to perform gating processing on the Ethernet synchronization source clock signal and the external clock source signal, avoiding the problem of large delay in signal transmission caused by processing different clock source signals in different chips, thereby reducing the probability of signal transmission errors and improving the accuracy of signal transmission.

[0024] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0025] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0026] Figure 1 is a block diagram of a chip management system according to an embodiment of the present invention;

[0027] Figure 2 is a block diagram of a clock management chip according to an embodiment of the present invention;

[0028] Figure 3 is a schematic diagram of the chip architecture of a clock management chip according to an embodiment of the present invention;

[0029] Figure 4 is a block diagram of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0030] The embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. The embodiments of the present invention are described in detail below.

[0031] 5G low-power wireless access nodes can alleviate the conflict between network coverage and cost. Their low deployment cost allows them to address the issue of limited coverage in high-frequency spectrum areas through large-scale deployment, achieving continuous wide coverage while effectively controlling construction costs. Furthermore, they improve 5G indoor coverage. Low-power wireless access nodes have lower power consumption and stronger optimization, self-configuration, self-interference management, and backhaul capabilities, typically preventing serious interference issues even when deployed in large numbers in densely populated areas.

[0032] Therefore, based on the deployment of macro base stations, 5G low-power wireless access nodes can cover areas with insufficient network signal coverage or even blind spots, enabling indoor digital 5G coverage, enhancing indoor signals, and bringing users a better indoor 5G network experience.

[0033] The L1 layer of a low-power wireless access node mainly consists of an embedded neural network processing chip, a baseband system chip, an RF front-end chip (RFIC), a clock synchronization module, and a clock management chip.

[0034] In related technologies, the use of discrete components for construction has several problems. In this embodiment of the invention, the above problems are explained from three aspects.

[0035] First, since there are two main clock synchronization sources for 5G, namely the Ethernet clock synchronization transmitter and the antenna clock synchronization transmitter, the two clock sources still need to be processed by different chips and architectures. For example, the Ethernet clock synchronization transmitter needs to be processed in the clock management chip, while the antenna clock synchronization source is processed in the GPS (Global Positioning System) module. Signal processing in different chips increases communication latency and the instability of information output.

[0036] Furthermore, after the clock management chip outputs the target adjustment clock signal, the closed-loop circuit for feeding back the adjustment clock signal will have different paths due to different architectures, increasing the complexity of signal transmission. For example, the closed-loop circuit can be: from the embedded neural network processing chip to the clock management chip and then to the embedded neural network processing chip, or the closed-loop circuit can also be: from the embedded neural network processing chip to the baseband system chip, then to the clock management chip, and finally to the embedded neural network processing chip.

[0037] Finally, low-power wireless access nodes have a variety of clock types and high frequencies. The clock management chips in related technologies provide a limited number of output clocks, which is insufficient to support the design requirements of low-power wireless access nodes. Introducing additional clock generators would increase the complexity of the architecture, and the presence of more interference on the output path would degrade the clock quality.

[0038] Therefore, by incorporating the antenna signal processing module and protocol processing module into the clock management chip of this invention, signal transmission delay is reduced, thereby improving the stability of chip operation.

[0039] To explain the working process of the clock management chip, the chip management system of this embodiment of the invention will be described first.

[0040] Referring to Figure 1, an example of the chip management system of an embodiment of the present invention will be described.

[0041] As shown in Figure 1, the chip management system 1 of this embodiment includes: an Ethernet clock synchronization source transmitter 10, an antenna clock synchronization source transmitter 11, a clock management chip 12, an embedded neural network processing chip 13, and a baseband system chip 14.

[0042] The system comprises the following components: an Ethernet clock synchronization transmitter 10 for transmitting an Ethernet synchronization source clock signal; an antenna clock synchronization transmitter 11 for transmitting an RF synchronization source clock signal; a clock management chip 12 connected to both the Ethernet clock synchronization transmitter 10 and the antenna clock synchronization transmitter 11 for receiving the Ethernet synchronization source clock signal and the RF synchronization source clock signal, and outputting a target synchronization clock signal, a 1PPS clock signal, and a target adjustment clock signal accordingly; an embedded neural network processing chip 13 connected to both the Ethernet clock synchronization transmitter and the clock management chip 12 for receiving the target clock signal and the 1PPS clock signal, and adjusting the internal clock signal of the embedded neural network processing chip according to the target clock signal to form a clock synchronization closed-loop loop and output a PTP clock signal; and a baseband system chip 14 connected to both the embedded neural network processing chip and the clock management chip for receiving the target clock signal and the 1PPS clock signal emitted by the embedded neural network processing chip. It is understood that the target clock signal includes a target adjustment clock signal and a target synchronization clock signal.

[0043] In this embodiment, when the chip management system 1 uses the Ethernet synchronization source clock signal as the synchronization clock source, the clock management chip 12 receives the Ethernet synchronization source clock signal and the PTP clock signal recovered from the embedded neural network processing chip 13, and processes the Ethernet synchronization source clock signal and the PTP clock signal to obtain the target synchronization clock signal and the target adjustment clock signal. The target adjustment clock signal is, for example, 1588CLK, and the target synchronization clock signal is, for example, the target synchronization clock signal sent to the embedded neural network processing chip 13 and the target synchronization clock signal sent to the baseband system chip 14. When the chip management system 1 uses the radio frequency synchronization source clock signal as the synchronization clock source, an external clock source signal is required, i.e., an external clock source signal. The clock management chip 12 receives the radio frequency synchronization source clock signal and outputs a 1PPS clock signal.

[0044] When the clock management chip 12 outputs the target synchronization clock signal and the target adjustment clock signal, it sends the target synchronization clock signal to the embedded neural network processing chip 13 and the baseband system chip 14 respectively. At the same time, it sends the target adjustment clock signal to the embedded neural network processing chip 13. After receiving the target adjustment clock signal, the embedded neural network processing chip 13 adjusts the clock signal inside the embedded neural network processing chip 13 to form a clock synchronization closed loop. After the adjustment is completed, it outputs the PTP clock signal.

[0045] It is understandable that both the Ethernet synchronization source clock signal and the external clock source signal can be processed by the clock management chip 12, without the need to use different chips and architectures to process different signals. Furthermore, the clock management chip 12 can synchronously send the output target synchronization clock signal to the embedded neural network processing chip and the baseband system chip, thereby achieving clock signal synchronization. This reduces clock signal delay and signal errors caused by different chip processing, thereby improving the stability of the chip management system.

[0046] The clock management chip 12 is illustrated below based on the aforementioned chip management system 1.

[0047] As shown in Figure 2, the clock management chip 12 of this embodiment is used in the chip management system 1. The clock management chip 12 includes: an antenna signal processing module 120, a protocol processing module 121, and a clock generation module 122. The antenna signal processing module is used to receive the radio frequency synchronization source clock signal and output a 1PPS clock signal according to the radio frequency synchronization source clock signal. The protocol processing module, for example, a PTP protocol processing module connected to the antenna signal processing module, is used to receive the Ethernet synchronization source clock signal, the PTP clock signal emitted by the embedded neural network processing chip, the 1PPS clock signal, and the external clock source signal, and output a transition clock signal according to the Ethernet synchronization source clock signal, the PTP clock signal, the 1PPS clock signal, and the external clock source signal. The clock generation module is connected to the PTP protocol processing module and is used to process the synchronization clock signal and the adjustment clock signal, and output the target synchronization clock signal and the target adjustment clock signal accordingly. The 1PPS clock signal is used to detect whether the external clock source signal is a clock source signal that meets the requirements, and performs subsequent processing when it is determined that the external clock source signal meets the requirements.

[0048] In this embodiment, the PTP protocol processing module 121 can perform corresponding signal processing according to the different synchronization source clock signals used. When selecting the radio frequency synchronization source clock signal, the radio frequency synchronization source clock signal is processed by the antenna signal processing module 120 to generate a 1PPS clock signal. When selecting the radio frequency synchronization source clock signal, it is necessary to receive an external clock source signal, perform gating and filtering processing based on the external clock source signal and / or the Ethernet synchronization source clock signal, and send the clock signal after gating and filtering processing to the clock generation module 122. The clock generation module 122 processes the received clock signal and outputs the target synchronization clock signal and the target adjustment clock signal.

[0049] When selecting the Ethernet synchronization source clock signal, the PTP protocol processing module 121 receives the Ethernet synchronization source clock signal and the PTP clock signal, determines the delay signal based on the received clock signal, and performs frequency optimization processing on the delay signal. The clock generation module 122 processes the received clock signal after frequency optimization and outputs the target synchronization clock signal and the target adjustment clock signal.

[0050] It is understandable that by integrating the PTP protocol processing module 121 and the antenna signal processing module 120 into the clock management chip 12, the RF synchronization source clock signal and the Ethernet synchronization source clock signal can be processed in the clock management chip 12 without the need for different chip architectures. This reduces signal delay and signal transmission errors caused by processing signals in different modules, thereby improving the accuracy of signal transmission while reducing signal transmission delay.

[0051] According to the clock management chip 12 of the present invention, by setting the antenna signal processing module and the protocol processing module in the clock management chip, the clock management chip can perform gating processing on the Ethernet synchronization source clock signal and the external clock source signal. That is, the same chip and architecture are used to perform gating processing on the Ethernet synchronization source clock signal and the external clock source signal, avoiding the problem of large delay in signal transmission caused by processing different synchronization source signals in different chips, thereby reducing the probability of signal transmission errors and improving the accuracy of signal transmission.

[0052] After the clock management chip 12 outputs the target adjustment clock signal, the closed-loop circuit for feeding back the adjustment clock signal may have different paths due to different architectures, increasing the complexity and instability of signal transmission. Therefore, by sending the target adjustment clock signal to the embedded neural network processing chip 13 to form a clock synchronization closed-loop circuit, the transmission path of the synchronization clock signal is simplified.

[0053] In some embodiments, as shown in FIG3, it is a schematic diagram of the chip architecture of a clock management chip according to an embodiment of the present invention. Referring to FIG1 and FIG3, the clock generation module 122 includes: multiple clock channels, one of which is connected to the embedded neural network processing chip 13 and is used to send a target adjustment clock signal to the embedded neural network processing chip 13 to form a clock synchronization closed loop.

[0054] In this embodiment, the clock generation module 122 includes multiple clock channels. The clock generation module 122 distributes the input synchronization clock signal and adjustment clock signal to different clock channels. Different clock channels are used to transmit different clock signals. One of the clock channels is fixed to generate a target adjustment clock signal, such as an IEEE 1588 CLK adjustment clock signal. This channel is connected to the embedded neural network processing chip 13 to form a clock synchronization closed-loop circuit. The embedded neural network processing chip 13 adjusts its internal clock signal according to the received target adjustment clock signal, and then performs AC correction. Other clock channels can be connected to the embedded neural network processing chip 13 and the baseband system chip 14 respectively to output the target synchronization clock signal. It is understood that by setting up the PTP protocol processing module, the clock management chip 12 and the embedded neural network processing chip 13 form a clock synchronization closed-loop circuit, thereby adjusting the internal clock signal of the embedded neural network processing chip. This simplifies the transmission path of the synchronization clock signal, reducing signal delay and transmission errors caused by the complex transmission path of the target synchronization clock signal, thus improving the accuracy and stability of the clock signal transmission.

[0055] In some embodiments, as shown in Figures 1 and 3, the remaining clock channels are connected to the embedded neural network processing chip 13 and the baseband system chip 14, respectively, for synchronously sending the target synchronization clock signal to the embedded neural network processing chip 13 and the baseband system chip 14. It can be understood that after the clock management chip 12 outputs the target synchronization clock signal, it outputs the target synchronization clock signal to the embedded neural network processing chip 13 and the baseband system chip 14, thus fixing the target synchronization clock signal path, reducing the clock signal transmission delay, and thereby improving the accuracy of signal transmission.

[0056] In some embodiments, as shown in FIG3, the PTP protocol processing module 121 includes: a synchronization source signal receiving unit for receiving an Ethernet synchronization source clock signal and a PTP clock signal; and a gating processing unit connected to the synchronization source signal receiving unit for comparing and gating the Ethernet synchronization source clock signal and an external clock source signal, and for outputting a synchronization clock signal and an adjustment clock signal.

[0057] In this embodiment, the synchronization source signal receiving unit receives the Ethernet clock source signal and the PTP clock signal. The gating processing unit receives the external clock source signal and the 1PPS clock signal, as well as the Ethernet clock source signal and the PTP clock signal output after processing by the synchronization source signal receiving unit. The gating processing unit compares and performs gating processing on the received Ethernet synchronization source clock signal and the external clock source signal, selecting different synchronization clock signals to adjust the clock signal based on different clock source signals. It can be understood that the 1PPS clock signal is used to detect whether the external clock source signal meets the requirements, and when it is determined that the external clock source signal meets the requirements, subsequent gating and filtering processing is performed. The PTP clock signal is connected to an external clock processing chip to achieve feedback adjustment of the clock signal.

[0058] In some embodiments, as shown in FIG3, the synchronization source signal receiving unit includes: a digitally controlled oscillator (DCO), which is used to receive the Ethernet synchronization source clock signal and the PTP clock signal, determine the delay signal based on the Ethernet synchronization source clock signal and the PTP clock signal, and optimize the delay signal to obtain an optimized delay signal.

[0059] In some embodiments, as shown in FIG3, the gating processing unit includes a clock signal processor, a data selector MUX, and a low-power filter. The clock signal processor is used to receive an external clock source signal and output a valid clock source signal according to the external clock source signal and the 1PPS clock signal. The data selector MUX is connected to the numerically controlled oscillator DCO and the clock signal processor respectively, and is used to receive the optimized delay signal and / or the valid clock source signal, and to select the optimized delay signal and / or the valid clock source signal to output an initial synchronization clock signal and an initial adjustment clock signal. The low-power filter is connected to the data selector and is used to filter the initial synchronization clock signal and the initial adjustment clock signal to output a synchronization clock signal and an adjustment clock signal.

[0060] In this embodiment, when the clock management chip 1 selects the Ethernet synchronization source clock signal as the synchronization clock source, the Ethernet synchronization source clock signal from the Ethernet clock synchronization source transmitter enters and communicates with the PTP clock signal recovered by the embedded neural network processing chip 13 to determine the delay signal. After determining the delay signal, it is processed by the digitally controlled oscillator (DCO) to optimize and adjust its frequency, thereby obtaining the optimized delay signal.

[0061] When the clock management chip 1 selects the radio frequency synchronization source clock signal as the synchronization clock source, it needs to form an external clock with the external clock source signal to receive the external clock source signal. When processing the external clock source signal, it needs to receive the 1PPS clock signal. After receiving the external clock source signal, the clock signal processor processes and judges it, and outputs the valid clock source signal.

[0062] After the data selector receives the valid clock source signal from the data oscillator and the clock signal processor and / or the optimized delay signal from the numerically controlled oscillator, it performs gating processing on the valid clock source signal and / or the optimized delay signal from the numerically controlled oscillator. After gating, it outputs the initial synchronization clock signal and the initial adjustment clock signal. After filtering the initial synchronization clock signal and the initial adjustment clock signal through the low-power filter LPF, the synchronization clock signal and the adjustment clock signal are generated and enter the clock generation module.

[0063] It is understandable that when the clock management chip 1 receives one of the radio frequency synchronization source clock signal and the Ethernet synchronization source clock signal, it receives the radio frequency synchronization source clock signal and the Ethernet synchronization source clock signal through the corresponding clock signal processor or digitally controlled oscillator (DCO), and performs gating and filtering on one of the radio frequency synchronization source clock signal and the Ethernet synchronization source clock signal, and outputs the corresponding synchronization clock signal and the adjustment clock signal.

[0064] When the clock management chip 1 receives the synchronization source clock signal and the Ethernet synchronization source clock signal, it can receive the RF synchronization source clock signal and the Ethernet synchronization source clock signal according to the clock signal processor or the numerically controlled oscillator, select the output with better clock quality through the data selector, filter it, and output the synchronization clock signal and the adjustment clock signal.

[0065] In some embodiments, as shown in FIG3, the antenna signal processing module 120 includes: an analog signal processing unit and a digital signal processing unit. The analog signal processing unit is used to receive a radio frequency synchronization source clock signal and output a digital signal. The digital signal processing unit is connected to the analog signal processing unit and is used to receive the digital signal and output a 1PPS clock signal according to the digital signal.

[0066] For example, as shown in Figure 3, the analog signal processing unit includes a low-noise amplifier (LNA) and a front-end processor (RFFE). The LNA receives the radio frequency synchronization source clock signal, amplifies the radio frequency synchronization source clock signal, and outputs the initial radio frequency synchronization source clock amplified signal. The RFFE is connected to the LNA and processes the initial radio frequency synchronization source clock amplified signal to output a digital signal.

[0067] The digital signal processing unit includes a digital filter and a GNSS processor. The digital filter is connected to the front-end processor RFFE and is used to process digital signals and output filtered digital signals. The GNSS processor is connected to the digital filter and is used to generate a 1PPS clock signal based on the filtered digital signal.

[0068] In this embodiment, after the radio frequency synchronization source clock signal enters the antenna signal processing module, it is first amplified by a low-noise amplifier to generate an initial radio frequency synchronization source clock amplified signal. The initial radio frequency synchronization source clock amplified signal is then sent to the front-end processor RFFE. After the front-end processor RFFE processes the initial radio frequency synchronization source clock amplified signal, it forms a digital signal. After the digital signal is processed by the GNSS processor, a 1PPS clock signal is generated, and the 1PPS clock signal is synchronously output to the embedded neural network processing chip and the baseband system chip.

[0069] In some embodiments, as shown in FIG3, the clock generation module 12 further includes: a plurality of phase-locked loop subunits for receiving a synchronous clock signal and an adjustment clock signal, and generating a set frequency synchronous clock signal and an adjustment clock signal; and a differential numerator unit connected to the plurality of phase-locked loop units for receiving the set frequency synchronous clock signal and the adjustment clock signal, and outputting a target synchronous clock signal and a target adjustment clock signal.

[0070] In this embodiment, multiple phase-locked loop (PLL) sub-units and corresponding differential numerator units are set in the clock generation module to process the optimized clock signal and output the target synchronization clock signal and the target adjustment clock signal. By setting multiple clock generation modules, the processed clock signal is directly filtered, divided, and loaded internally before being output. There is no need to introduce an additional clock generator or use an external clock source. This simplifies the internal architecture and reduces the impact of output path interference signals on the clock signal quality, thereby improving the clock signal quality.

[0071] According to the clock management chip 1 of the present invention, by setting the antenna signal processing module and the protocol processing module in the clock management chip, the clock management chip can perform gating processing on the Ethernet synchronization source clock signal and the external clock source signal. That is, the same chip and architecture are used to perform gating processing on the Ethernet synchronization source clock signal and the external clock source signal, avoiding the problem of large delay in signal transmission caused by processing different clock source signals in different chips, thereby reducing the probability of signal transmission errors and improving the accuracy of signal transmission.

[0072] The electronic device according to embodiments of the present invention is described below.

[0073] As shown in FIG4, the electronic device 2 of this invention includes the chip management system 1 of the above embodiment.

[0074] According to the present invention, the electronic device 2, by setting the antenna signal processing module and the protocol processing module in the clock management chip, enables the clock management chip to perform gating processing on the Ethernet synchronization source clock signal and the external clock source signal. That is, the same chip and architecture are used to perform gating processing on the Ethernet synchronization source clock signal and the external clock source signal, avoiding the problem of large delay in signal transmission caused by processing different clock source signals in different chips, thereby reducing the probability of signal transmission errors and improving the accuracy of signal transmission.

[0075] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.

[0076] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A clock management chip, characterized in that, include: The antenna signal processing module is used to receive the radio frequency synchronization source clock signal and output a 1PPS clock signal according to the radio frequency synchronization source clock signal. A protocol processing module, connected to the antenna signal processing module, is used to receive an Ethernet synchronization source clock signal, a PTP clock signal, a 1PPS clock signal, and an external clock source signal, and output a transition clock signal based on the Ethernet synchronization source clock signal, the PTP clock signal, the 1PPS clock signal, and the external clock source signal. A clock generation module, connected to the protocol processing module, is used to process the transition clock signal and output a target clock signal accordingly. The target clock signal includes a target adjustment clock signal. The clock generation module includes multiple clock channels, one of which is connected to a clock processing chip and is used to send the target adjustment clock signal to the clock processing chip to form a clock synchronization closed loop. By setting the PTP protocol processing module, the clock management chip and the clock processing chip form a clock synchronization closed loop.

2. The clock management chip according to claim 1, characterized in that, The target clock signal also includes a target synchronization clock signal. The remaining clock channels are connected to the clock processing chip and the system chip respectively, and are used to synchronously send the target synchronization clock signal to the clock processing chip and the system chip.

3. The clock management chip according to claim 1, characterized in that, The transition clock signal includes a synchronization clock signal and an adjustment clock signal. The protocol processing module includes: a synchronization source signal receiving unit for receiving the Ethernet synchronization source clock signal and the PTP clock signal; and a gating processing unit connected to the synchronization source signal receiving unit for gating the Ethernet synchronization source clock signal and the external clock source signal, and outputting the synchronization clock signal and the adjustment clock signal.

4. The clock management chip according to claim 3, characterized in that, The synchronization source signal receiving unit includes a numerically controlled oscillator, used to receive the Ethernet synchronization source clock signal and the PTP clock signal, determine the delay signal based on the Ethernet synchronization source clock signal and the PTP clock signal, and optimize the delay signal to obtain an optimized delay signal.

5. The clock management chip according to claim 4, characterized in that, The gating processing unit includes: a clock signal processor, used to receive the external clock source signal and the 1PPS clock signal, and output a valid clock source signal according to the external clock source signal and the 1PPS clock signal; a data selector, connected to the numerically controlled oscillator and the clock signal processor respectively, used to receive the optimized delay signal and / or the valid clock source signal, and gating the optimized delay signal and / or the valid clock source signal to output an initial synchronization clock signal and an initial adjustment clock signal; and a low-power filter, connected to the data selector, used to filter the initial synchronization clock signal and the initial adjustment clock signal to output the synchronization clock signal and the adjustment clock signal.

6. The clock management chip according to claim 1, characterized in that, The antenna signal processing module includes: an analog signal processing unit for receiving the radio frequency synchronization source clock signal and outputting a digital signal; and a digital signal processing unit connected to the analog signal processing unit for receiving the digital signal and outputting the 1PPS clock signal according to the digital signal.

7. The clock management chip according to claim 6, characterized in that, The analog signal processing unit includes: a low-noise amplifier, which receives the radio frequency synchronization source clock signal, amplifies the radio frequency synchronization source clock signal, and outputs an initial radio frequency synchronization source clock amplified signal; and a front-end processor, connected to the low-noise amplifier, which processes the initial radio frequency synchronization source clock amplified signal and outputs the digital signal.

8. The clock management chip according to claim 6, characterized in that, The digital signal processing unit includes: a digital filter connected to the analog signal processing unit for processing the digital signal and outputting a filtered digital signal; and a GNSS processor connected to the digital filter for generating the 1PPS clock signal based on the filtered digital signal.

9. The clock management chip according to claim 2, characterized in that, The transition clock signal includes a synchronous clock signal and an adjustment clock signal. The clock generation module further includes: multiple phase-locked loop sub-units for receiving the synchronous clock signal and the adjustment clock signal, and generating a set frequency synchronous clock signal and an adjustment clock signal; and a differential numerator unit connected to the multiple phase-locked loop sub-units for receiving the set frequency synchronous clock signal and the adjustment clock signal, and outputting the target synchronous clock signal and the target adjustment clock signal.

10. The clock management chip according to claim 1, characterized in that, The protocol processing module and the antenna signal processing module are integrated in the clock management chip.

11. A chip management system, characterized in that, include: Ethernet clock synchronization transmitter, used to send Ethernet synchronization source clock signal; Antenna clock synchronization transmitter, used to send radio frequency synchronization source clock signal; The clock management chip as described in any one of claims 1-10 is connected to the Ethernet clock synchronization transmitter and the antenna clock synchronization transmitter respectively, and is used to receive the Ethernet synchronization source clock signal and the radio frequency synchronization source clock signal, and output a 1PPS clock signal and a target clock signal according to the Ethernet synchronization source clock signal and the radio frequency synchronization source clock signal. An embedded neural network processing chip is connected to the Ethernet clock synchronization transmitter and the clock management chip, respectively, for receiving the target clock signal and the 1PPS clock signal, and adjusting the internal clock signal of the embedded neural network processing chip according to the target clock signal to form a clock synchronization closed loop; a baseband system chip is connected to the embedded neural network processing chip and the clock management chip, respectively, for receiving the target clock signal and the 1PPS clock signal emitted by the embedded neural network processing chip.

12. An electronic device, characterized in that, include: The chip management system as described in claim 11.

Images