Back contact cell, cell assembly and photovoltaic system

Abstract

The utility model relates to the technical field of solar cells, and provides a back contact cell, a cell assembly and a photovoltaic system, the back surface of a silicon wafer of the back contact cell is provided with a first region and a second region which are alternately arranged at intervals, the first region and the second region are separated by a spacer region, and a first polarity doping layer is stacked in the first region. The second polarity doping layer is arranged in the second region in a stacked mode, and the second polarity doping layer and the first polarity doping layer are separated through a spacer region. A plurality of first isolated doping parts are arranged in the spacer region, and the first isolated doping parts are not in contact with the first polarity doping layer and the second polarity doping layer. Therefore, the plurality of independent first isolated doping parts are arranged in the spacer region, and the first isolated doping parts can form floating junction passivation in the spacer region, so that the passivation effect of the spacer region can be improved, the collection rate of carriers can be improved, and the efficiency of the back contact battery is improved.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to a back-contact cell, a cell assembly, and a photovoltaic system. Background Art

[0002] At present, among solar cells, the back-contact cell is a cell in which both the emitter and the base are arranged on the back side of the cell (non-light-receiving side). The light-receiving side of the cell is not blocked by any metal electrode, thereby effectively increasing the short-circuit current of the cell.

[0003] In related art, back-contact cells have a P-type doped layer and an N-type doped layer on the back side, separated by an isolation region (e.g., a trench) to prevent short circuits and leakage. However, in related art, carriers easily recombine in the isolation region, resulting in a low carrier collection rate and a need for further improvement in the efficiency of back-contact cells. Utility Model Content

[0004] The present application provides a back-contact cell, a cell assembly, and a photovoltaic system.

[0005] The present application is implemented as follows: the back contact battery of the embodiment of the present application includes:

[0006] A silicon wafer having a front side and a back side facing each other, the back side comprising first and second regions alternately arranged in sequence along a first direction, the first and second regions both extending along a second direction, a spacing region being defined between adjacent first and second regions, and the second direction intersecting the first direction;

[0007] a first polarity doped layer stacked on the first region;

[0008] a second polarity doping layer stacked on the second region, wherein the polarity of the second polarity doping layer is opposite to that of the first polarity doping layer; and

[0009] A plurality of first isolated doped portions are independently arranged in the spacing region and spaced apart from the first polarity doped layer and the second polarity doped layer. The polarity of the first isolated doped portion is the same as that of the first polarity doped layer.

[0010] In some embodiments, in the first direction, a distance between the first isolated doped region and the first polarity doped layer is greater than or equal to 300 nm.

[0011] In some embodiments, in the first direction, a distance between the first isolated doped region and the second polarity doped layer is greater than or equal to 300 nm.

[0012] In some embodiments, a plurality of the first isolated doped portions are randomly distributed on the spacer region; or

[0013] A plurality of the first isolated doped portions are arranged at intervals along the second direction on the spacing region.

[0014] In some embodiments, a plurality of the first isolated doped portions are arranged in the spacing region at intervals along the second direction, and a distance between two adjacent first isolated doped portions in the second direction is 30 um-380 um.

[0015] In some embodiments, a ratio of an orthographic projection area of all the first isolated doped portions in a single spacer in the thickness direction of the silicon wafer to an orthographic projection area of the single spacer in the thickness direction of the silicon wafer is 0.0001-0.5.

[0016] In some embodiments, a ratio of an orthographic projection area of all the first isolated doped portions in a single spacer in the thickness direction of the silicon wafer to an orthographic projection area of the single spacer in the thickness direction of the silicon wafer is 0.001-0.1.

[0017] In some embodiments, the thickness of the first isolated doped portion is 20 nm-450 nm.

[0018] In some embodiments, a plurality of first arc-shaped recessed regions are formed on the sidewall surface adjacent to the first polarity doping layer and the spacer region, and the plurality of first arc-shaped recessed regions are arranged along the second direction. Two adjacent first arc-shaped recessed regions intersect with each other, and the first isolated doping portion is arranged near the junction of the two adjacent first arc-shaped recessed regions.

[0019] In some embodiments, the silicon wafer has a first isolated protrusion in the spacer region, and the first isolated doped portion is disposed on the first isolated protrusion and covers at least a portion of the first isolated protrusion.

[0020] In some embodiments, the first isolated doping portion completely covers the first isolated protrusion, and the first isolated doping portion has a first suspended segment extending beyond the first isolated protrusion and suspended within the spacer.

[0021] In some embodiments, a second isolated doped portion is provided on a surface of the first suspended segment facing the silicon wafer, wherein the second isolated doped portion has a polarity opposite to that of the first polarity doped layer and the same as that of the second polarity doped layer.

[0022] In some embodiments, the second isolated doped portion is insulated and isolated from the first suspended segment.

[0023] In some embodiments, the second isolated doped portion further extends along a side surface of the first isolated protrusion to an area of the silicon wafer blocked by the first suspended segment.

[0024] In some embodiments, a third isolated doped portion is formed on a side surface of the first isolated protrusion, and the third isolated doped portion is spaced apart from the first isolated doped portion.

[0025] In some embodiments, a fourth isolated doped portion is provided on the area of the silicon wafer blocked by the first suspended segment, the polarity of the fourth isolated doped portion is the same as the polarity of the second polarity doped layer, and the fourth isolated doped portion is spaced apart from the first polarity doped layer and the second polarity doped layer.

[0026] In some embodiments, the fourth isolated doped portion is spaced apart from the first isolated protrusion and the first isolated doped portion.

[0027] In some embodiments, in the first direction, a distance between the fourth isolated doped portion and the first isolated protrusion is 0.1 um-200 um.

[0028] In some embodiments, the back contact battery further includes a plurality of fifth isolated doped portions, and the plurality of fifth isolated doped portions are all arranged in the spacing area, and the fifth isolated doped portions are spaced apart from the first polarity doped layer and the second polarity doped layer, and the fifth isolated doped portion has the same polarity as the second polarity doped layer.

[0029] In some embodiments, the fifth isolated doped region and the first isolated doped region are spaced apart in the spacer region.

[0030] In some embodiments, a distance between any one of the fifth isolated doped regions and any one of the first isolated doped regions is greater than or equal to 0.1 um-200 um.

[0031] In some embodiments, in the first direction, a distance between the fifth isolated doped region and the second polarity doped layer is greater than or equal to 300 nm.

[0032] In some embodiments, in the first direction, a distance between the fifth isolated doped region and the first polarity doped layer is greater than or equal to 300 nm.

[0033] In some embodiments, a plurality of the fifth isolated doped portions are randomly distributed on the spacer region; or

[0034] A plurality of the fifth isolated doped portions are arranged at intervals along the second direction on the spacing region.

[0035] In some embodiments, a plurality of the fifth isolated doped portions are arranged at intervals along the second direction on the spacing region, and a distance between two adjacent fifth isolated doped portions is 30 um-380 um.

[0036] In some embodiments, a ratio of an orthographic projection area of all the fifth isolated doped portions in a single spacer in the thickness direction of the silicon wafer to an orthographic projection area of the single spacer in the thickness direction of the silicon wafer is 0.0001-0.5.

[0037] In some embodiments, a ratio of an orthographic projection area of all the fifth isolated doped portions in a single spacer in the thickness direction of the silicon wafer to an orthographic projection area of the single spacer in the thickness direction of the silicon wafer is 0.001-0.1.

[0038] In some embodiments, the fifth isolated doped portion has a thickness of 20 nm-450 nm.

[0039] In some embodiments, a plurality of second arc-shaped recessed regions are formed on the sidewall surface of the second polarity doping layer adjacent to the spacer region, and the plurality of second arc-shaped recessed regions are arranged along the second direction. Two adjacent second arc-shaped recessed regions intersect with each other, and the fifth isolated doping portion is arranged near the junction of two adjacent second arc-shaped recessed regions.

[0040] In some embodiments, a trench is formed in the spacer region, a second isolated protrusion is formed in the trench, and the fifth isolated doped portion is disposed on the second isolated protrusion and covers at least a portion of the second isolated protrusion.

[0041] In some embodiments, the fifth isolated doped portion only covers a portion of the second isolated protrusion; or

[0042] The fifth isolated doped portion completely covers the second isolated protrusion, and the fifth isolated doped portion has a second suspended segment extending beyond the second isolated protrusion and suspended within the spacer.

[0043] In some embodiments, at at least a portion of the first polarity doped layer, the first polarity doped layer has a third suspended segment extending above the spacer region, the third suspended segment is suspended on a portion of the spacer region, and the first isolated doped portion is arranged on an area of the spacer region that is not blocked by the third suspended segment.

[0044] In some embodiments, a sixth isolated doped portion is provided on a surface of the third suspended segment facing the silicon wafer, and the polarity of the sixth isolated doped portion is the same as the polarity of the second polarity doped layer.

[0045] In some embodiments, a seventh isolated doped portion is provided on the area of the silicon wafer blocked by the third suspended segment, the seventh isolated doped portion is spaced apart from the first polarity doped layer and the second polarity doped layer, and the polarity of the seventh isolated doped portion is the same as the polarity of the second polarity doped layer.

[0046] In some embodiments, the seventh isolated doped region is spaced apart from the first isolated doped region.

[0047] In some embodiments, the silicon wafer has a silicon wafer extension portion extending onto the spacer and suspended within the spacer, and at least a portion of the third suspended segment is stacked on the silicon wafer extension portion.

[0048] In some embodiments, an eighth isolated doped portion is formed on a surface of the silicon extension portion facing away from the third suspended segment, and the polarity of the eighth isolated doped portion is the same as the polarity of the second polarity doped layer.

[0049] In some embodiments, the eighth isolated doped region is spaced apart from the first isolated doped region.

[0050] The present application also provides a battery assembly, which includes several back-contact batteries as described in any one of the above items.

[0051] The present application also provides a photovoltaic system, which includes the above-mentioned battery assembly.

[0052] In the back-contact cell, cell assembly, and photovoltaic system of the embodiments of the present application, the back side of the silicon wafer has a first region and a second region arranged alternately at intervals, the first region and the second region being separated by a spacer. A first polarity doped layer is stacked in the first region, and a second polarity doped layer is stacked in the second region, with the second polarity doped layer and the first polarity doped layer being separated by the spacer. Within the spacer, a number of first isolated doped portions are provided that are independent of both the first polarity doped layer and the second polarity doped layer, and none of the first isolated doped portions is in contact with the first polarity doped layer and the second polarity doped layer. Thus, the provision of the spacer ensures electrical isolation between the first polarity doped layer and the second polarity doped layer, thereby avoiding short circuits. At the same time, by providing a number of independent first isolated doped portions within the spacer, the first isolated doped portions can form a floating junction passivation within the spacer, thereby enhancing the passivation effect of the spacer, thereby improving the efficiency of the back-contact cell. Furthermore, providing independent first isolated doped portions within the spacer can enhance the carrier collection rate.

[0053] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 This is a module schematic diagram of a photovoltaic system provided by an embodiment of the present application;

[0055] Figure 2 Schematic diagram of a module of a battery assembly provided in an embodiment of the present application;

[0056] Figure 3 Schematic diagram of the planar structure of a back-contact battery provided in an embodiment of the present application;

[0057] Figure 4 is a schematic cross-sectional view of a back-contact battery provided in an embodiment of the present application;

[0058] Figure 5 1 is another schematic planar structural diagram of a back-contact battery provided in an embodiment of the present application;

[0059] Figure 6 1 is another schematic cross-sectional structure diagram of a back-contact battery provided in an embodiment of the present application;

[0060] Figure 7 is another schematic cross-sectional structure diagram of a back-contact battery provided in an embodiment of the present application;

[0061] Figure 8 1 is another schematic cross-sectional view of a back-contact battery provided in an embodiment of the present application;

[0062] Figure 9 1 is another schematic planar structural diagram of a back-contact battery provided in an embodiment of the present application;

[0063] Figure 10 1 is another schematic cross-sectional view of a back-contact battery provided in an embodiment of the present application;

[0064] Figure 11 1 is another schematic planar structural diagram of a back-contact battery provided in an embodiment of the present application;

[0065] Figure 12 1 is another schematic cross-sectional view of a back-contact battery provided in an embodiment of the present application;

[0066] Figure 13 1 is another schematic cross-sectional view of a back-contact battery provided in an embodiment of the present application;

[0067] Figure 14 1 is another schematic cross-sectional view of a back-contact battery provided in an embodiment of the present application;

[0068] Figure 15 1 is another schematic cross-sectional view of a back-contact battery provided in an embodiment of the present application;

[0069] Figure 16 1 is another schematic cross-sectional view of a back-contact battery provided in an embodiment of the present application;

[0070] Figure 17 This is another schematic cross-sectional structure diagram of the back-contact battery provided in an embodiment of the present application.

[0071] Description of main component symbols:

[0072] Photovoltaic system 1000, battery assembly 200, back contact battery 100, silicon wafer 10, front side 11, back side 12, first area 121, second area 122, spacer area 123, first isolated protrusion 1231, groove 1232, second isolated protrusion 1233, first polarity doping layer 20, first arc-shaped recessed area 21, second polarity doping layer 30, first isolated doping part 40, first suspended section 41, back side passivation film layer 50, first electrode 60, second electrode 70, second isolated doping part 80, third isolated doping part 90, fourth isolated doping part 110, fifth isolated doping part 120, second suspended section 1201. DETAILED DESCRIPTION

[0073] In order to make the purpose, technical solutions and advantages of the present application more clear, the present application is further described in detail below with reference to the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application. In addition, it should be understood that the specific embodiments described herein are merely used to explain the present application and are not intended to limit the present application.

[0074] In the description of this application, it should be understood that the terms "length", "width", "up", "down", "horizontal", "longitudinal", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on this application.

[0075] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the described features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0076] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections, electrical connections, or mutual communication; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal communication between two components or the interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0077] In this application, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Moreover, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0078] The disclosure below provides many different embodiments or examples for realizing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. In addition, the present application may repeat reference numbers and / or reference letters in different examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present application provides examples of various specific processes and materials, but those skilled in the art will appreciate the application of other processes and / or the use scenarios of other materials.

[0079] See also Figure 1-Figure 2 The photovoltaic system 1000 in the embodiment of the present application may include the battery assembly 200 in the embodiment of the present application, and the battery assembly 200 in the embodiment of the present application may include multiple back-contact batteries 100 in the embodiment of the present application.

[0080] The multiple back-contact cells 100 in the battery assembly 200 can be connected in series to form multiple battery strings. Each battery string can be connected in series, in parallel, or in a combination of series and parallel to achieve current bus output. For example, the connection between the individual cells in the battery string can be achieved by welding welding ribbons, and the connection between the individual battery strings can be achieved by bus bars. In some embodiments, the individual battery strings can be formed into a battery cell array, which is then packaged together with a front plate, a front film, a rear film, and a back plate to form the battery assembly 200.

[0081] See also Figure 3 and Figure 4 The back contact cell 100 in the embodiment of the present application may include a silicon wafer 10 , a plurality of first polarity doped layers 20 , a plurality of second polarity doped layers 30 and a plurality of first isolated doped portions 40 .

[0082] Silicon wafer 10 has opposite front sides 11 (i.e., the light-receiving side) and back sides 12 (i.e., the light-receiving side). Back sides 12 of silicon wafer 10 include first regions 121 and second regions 122 alternately arranged along a first direction. Both first regions 121 and second regions 122 extend along a second direction. Spacers 123 are located between adjacent first regions 121 and second regions 122. The second direction intersects the first direction. Specifically, first regions 121 and second regions 122 are separated by spacers 123, which also extend along the second direction.

[0083] Specifically, if Figure 3 As shown, the first regions 121 and the second regions 122 may be arranged alternately along the lateral direction of the silicon wafer 10 and both extend along the longitudinal direction. That is, the first direction may be the lateral direction of the back-contact cell 100, and the second direction may be the longitudinal direction of the back-contact cell 100, with the two directions being perpendicular to each other. Of course, in other embodiments, the first direction and the second direction may also be other directions, for example, both may be diagonal directions of the silicon wafer 10, and this is not limited here.

[0084] In the embodiment of the present application, a first polarity doped layer 20 is stacked on the first region 121, and a second polarity doped layer 30 is stacked on the second region 122. The first polarity doped layer 20 and the second polarity doped layer 30 have opposite polarities, that is, they have opposite doping types. A first polarity doped layer 20 is stacked on each first region 121, and a second polarity doped layer 30 is stacked on each second region 122. The first polarity doped layer 20 and the second polarity doped layer 30 are separated by a spacer 123.

[0085] like Figure 3 and Figure 4 As shown, the plurality of first isolated doped regions 40 are independently disposed within the spacer region 123 (i.e., the plurality of first isolated doped regions 40 are spaced apart from one another within the spacer region 123), and the first isolated doped regions 40 are spaced apart from the first polarity doped layer 20 and the second polarity doped layer 30. In other words, the plurality of first isolated doped regions 40 may be spaced apart within the spacer region 123, and the first isolated doped regions 40 do not contact either the first polarity doped layer 20 or the second polarity doped layer 30, and each of the first isolated doped regions 40 is an isolated doping site.

[0086] It should be noted that, in this article, a certain film layer is stacked on a certain area or a certain film layer. It can be that the film layer is directly stacked on the surface area or film layer, or other film layers are arranged between the film layer and the surface area or film layer. The stacked arrangement is only used to define the stacking arrangement of the film layers. For example, in some embodiments, in the back contact battery 100, a tunneling layer (not shown) can be further provided between the first polarity doped layer 20 and the silicon wafer 10, and a tunneling layer can also be provided between the second polarity doped layer 30 and the silicon wafer 10. The tunneling layer includes but is not limited to a tunneling oxide layer (such as a silicon dioxide tunneling layer), an intrinsic amorphous silicon layer, and other film layers. For another example, in some embodiments, a tunneling layer (such as a silicon dioxide tunneling layer) can also be provided between the first isolated doped portion 40 and the surface of the spacer 123.

[0087] In addition, in this article, the spacing between two structures or film layers means that the two are independent of each other and have no contact. For example, the spacing between the first isolated doped portion 40 and the first polarity doped layer 20 and the second polarity doped layer 30 means that the first isolated doped portion 40 has no contact with both the first polarity doped layer 20 and the second polarity doped layer 30. If similar descriptions appear below, please refer to this for understanding.

[0088] In the back-contact cell 100, cell assembly 200, and photovoltaic system 1000 of the embodiments of the present application, the back side 12 of the silicon wafer 10 has first regions 121 and second regions 122 arranged alternately at intervals. The first regions 121 and the second regions 122 are separated by a spacer 123. The first polarity doped layer 20 is stacked in the first region 121, and the second polarity doped layer 30 is stacked in the second region 122. The second polarity doped layer 30 and the first polarity doped layer 20 are separated by the spacer 123. Disposed within the spacer 123 are a number of first isolated doped portions 40 that are independent of the first polarity doped layer 20 and the second polarity doped layer 30. None of the first isolated doped portions 40 contact the first polarity doped layer 20 and the second polarity doped layer 30. Thus, the provision of the spacer 123 ensures electrical isolation between the first polarity doped layer 20 and the second polarity doped layer 30, preventing short circuits. Furthermore, by providing a plurality of independent first isolated doped portions 40 within the spacer 123, the first isolated doped portions 40 can form floating junction passivation within the spacer 123, thereby improving the passivation effect of the spacer 123 and reducing the probability of surface recombination at the spacer 123, thereby improving the carrier collection rate (i.e., the probability of photogenerated carriers being collected and participating in the current flow), and improving the efficiency of the back-contact cell 100. In other words, in the embodiments of the present application, by providing the first isolated doped portions 40, while ensuring the isolation effect of the first polarity doped layer 20 and the second polarity doped layer 30, a better passivation effect can be achieved, the probability of surface recombination at the spacer 123 can be reduced, and the efficiency of the back-contact cell 100 can be improved.

[0089] Specifically, in the embodiments of the present application, the silicon wafer 10 may be an N-type silicon wafer 10 or a P-type silicon wafer 10, and the specific details are not limited here. The polarities of the first polarity doping layer 20 and the second polarity doping layer 30 are opposite, one of which is a P-type doping layer and the other is an N-type doping layer. When the first polarity doping layer 20 is a P-type doping layer and collects holes, the second polarity doping layer 30 is an N-type doping layer and collects electrons. When the first polarity doping layer 20 is an N-type doping layer and collects electrons, the second polarity doping layer 30 is a P-type doping layer and collects holes, and the specific details are not limited here, as long as the polarities of the two are opposite.

[0090] In some embodiments, the first polarity doping layer 20 may be a P-type doping layer, the second polarity doping layer 30 may be an N-type doping layer, and the first isolated doping portion 40 may be a P-type doping portion. In this case, when the back contact battery 100 is working, the first polarity doping layer 20 collects holes, and the second polarity doping layer 30 collects electrons. Holes and electrons are prone to surface recombination in the spacer 123. By setting a P-type first isolated doping portion 40 in the spacer 123, a floating junction passivation will be formed at the first isolated doping portion 40, thereby improving the passivation effect. At the same time, the holes will be saturated in the first isolated doping portion 40, and then the area will repel the holes, thereby reducing the probability of holes occurring surface recombination in the spacer 123, so that the holes can be quickly and efficiently collected by the first polarity doping layer 20, thereby improving the collection rate of hole carriers and thereby improving the conversion efficiency of the back contact battery 100.

[0091] In some embodiments, the first polarity doped layer 20 may be an N-type doped layer, the second polarity doped layer 30 may be a P-type doped layer, and the first isolated doped portion 40 may be an N-type doped portion. In this case, when the back contact battery 100 is working, the second polarity doped layer 30 collects electrons and the second polarity doped layer 30 collects holes. Holes and electrons are prone to surface recombination in the spacer 123. By setting an N-type first isolated doped portion 40 in the spacer 123, a floating junction passivation will be formed in the first isolated doped portion 40, thereby improving the passivation effect. At the same time, electrons will be saturated in the first isolated doped portion 40, and then the region will repel electrons, reducing the probability of electron recombination in the spacer 123, that is, effectively avoiding large surface recombination of electrons and holes in the spacer 123, so that electrons can be quickly and efficiently collected by the first polarity doped layer 20, thereby improving the collection rate of electron carriers and thereby improving the conversion efficiency of the back contact battery 100.

[0092] It can be understood that surface recombination is a continuous loss. If the first isolated doping portion 40 is not set in the spacer region 123, continuous surface recombination will occur in the spacer region 123. In the present application, by setting the first isolated doping portion 40, the carriers (holes or electrons) at the first isolated doping portion 40 will quickly reach filling saturation. After saturation, at this position, the carriers are repelled, and the probability of recombination on the surface is reduced, which improves the carrier collection rate and thus improves efficiency.

[0093] In addition, if Figure 4 As shown, in the back contact battery 100 of the present application, a back passivation film layer 50 is also provided on the back side 12 , and the back passivation film layer 50 covers the first polarity doping layer 20 , the second polarity doping layer 30 and the spacer 123 , that is, the back passivation film layer 50 can cover the entire back side 12 .

[0094] A first electrode 60 and a second electrode 70 are provided on the back passivation film layer 50. The first electrode 60 is provided on the back passivation film layer 50 and is located in the first area 121. The first electrode 60 is conductively connected to the first polarity doping layer 20. For example, in some embodiments, the first electrode 60 may penetrate the back passivation film layer 50 to be conductively contacted with the first polarity doping layer 20.

[0095] The second electrode 70 is disposed on the back passivation layer 50 and located in the second region 122. The second electrode 70 is electrically connected to the second polarity doped layer 30. For example, in some embodiments, the second electrode 70 may also penetrate the back passivation layer 50 to be in electrically conductive contact with the second polarity doped layer 30. The first isolated doped portion 40 does not have an electrode. That is, the first electrode 60 and the second electrode 70 are physically separated from and do not contact the first isolated doped portion 40 to prevent carriers from reaching saturation at the first isolated doped portion 40.

[0096] In the embodiments of the present application, the specific shape of the first isolated doped portion 40 can be a regular shape or an irregular shape. For example, in some embodiments, the shape of the first isolated doped portion 40 can be one or more of a square, a cone, a pyramid, a prism, and a truncated cone, which is not specifically limited here.

[0097] See also Figure 4 In some embodiments, in the first direction, a distance L1 between the first isolated doped portion 40 and the first polarity doped layer 20 is greater than or equal to 300 nm.

[0098] In this way, it is possible to avoid the spacing between the first isolated doped portion 40 and the first polarity doped layer 20 being too small, which would result in poor isolation effect between the first isolated doped portion 40 and the first polarity doped layer 20. That is, such a setting can improve the isolation effect between the first isolated doped portion 40 and the first polarity doped layer 20, thereby making the carrier collection rate reach a better state, and at the same time, it can also improve the passivation effect of the spacer region 123.

[0099] Specifically, it is not difficult to understand that if the distance L1 between the two is too small (i.e., less than 300 nm), the electrical isolation effect between the first isolated doping portion 40 and the first polarity doping layer 20 is poor, which is equivalent to the first isolated doping portion 40 being connected to the first polarity doping layer 20, which easily leads to the carriers at the first isolated doping portion 40 being directly collected by the first polarity doping layer 20, and the corresponding carriers cannot reach saturation filling at the first isolated doping portion 40, thereby failing to achieve the function of repelling holes or electrons at the first isolated doping portion 40, resulting in a significant decrease in the effect of reducing surface recombination.

[0100] That is, in the present application, by setting the distance L1 between the first isolated doped portion 40 and the first polarity doped layer 20 to be greater than or equal to 300 nm, the surface recombination of the spacer region 123 can be significantly reduced, so that the carrier collection rate reaches a better state.

[0101] Specifically, in such an embodiment, the size of the spacing L1 between the first isolated doping portion 40 and the first polarity doping layer 20 may be, for example, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1um, 2um, 3um, 4um, 5um, 6um, 7um, 8um, 9um, 10um, 11um, 12um, 13um, 14um, 15um, 16um, 17um, 18um, 19um, 20um and other values.

[0102] Among them, such as Figure 4 As shown, in the embodiment of the present application, the width L2 of the spacer 123 in the first direction can be 50 μm-300 μm. The maximum spacing between the first isolated doped portion 40 and the first polarity doped layer 20 is preferably the width L2 of the spacer 123 in the first direction minus 6 μm, that is, 300 nm ≤ L1 ≤ L2-6 μm. Through research, it has been found that L1 is most preferably greater than or equal to 3 μm and less than or equal to L2-6 μm. In this case, the performance of the back contact cell 100 can be optimized.

[0103] Please continue reading Figure 4 In some embodiments, in the first direction, the distance L3 between the first isolated doped portion 40 and the second polarity doped layer 30 may be greater than or equal to 300 nm.

[0104] In this way, by setting the spacing L3 between the first isolated doping portion 40 and the second polarity doping layer 30 to be greater than 300 nm, the isolation effect of the first isolated doping portion 40 and the second polarity doping layer 30 can be ensured, and it is avoided that part of the carriers at the first isolated doping portion 40 directly recombine with the carriers at the second polarity doping layer 30, resulting in the inability of the carriers in the first isolated doping portion 40 to reach saturation, thereby significantly reducing the effect of reducing surface recombination.

[0105] Specifically, it is not difficult to understand that if the distance between the two is too small (i.e., less than 300 nm), it is equivalent to the first isolated doping portion 40 being connected to the second polarity doping layer 30, which easily causes the carriers (such as holes) at the first isolated doping portion 40 to directly recombine with the carriers (such as electrons) of the second polarity doping layer 30, and the corresponding carriers (such as holes) cannot be saturated at the first isolated doping portion 40, thereby failing to achieve the function of repelling holes or electrons at the first isolated doping portion 40, resulting in a significant reduction in the effect of reducing surface recombination.

[0106] That is to say, in the present application, by setting the distance L3 between the first isolated doped portion 40 and the second polarity doped layer 30 to be greater than or equal to 300m, the surface recombination of the spacer region 123 can be significantly reduced, so that the carrier collection rate reaches a better state.

[0107] Specifically, in such an embodiment, the spacing L3 between the first isolated doped portion 40 and the second polarity doped layer 30 may be, for example, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1 um, 2 um, 3 um, 4 um, 5 um, 6 um, 7 um, 8 um, 9 um, 10 um, 11 um, 12 um, 13 um, 14 um, 15 um, 16 um, 17 um, 18 um, 19 um, 20 um, etc. The maximum spacing between the first isolated doped portion 40 and the second polarity doped layer 30 may preferably be the width of the spacer 123 in the first direction minus 6 um, i.e., 300 nm ≤ L3 ≤ L2-6 um. Studies have shown that L3 is most preferably greater than or equal to 3 um and less than or equal to L2-6 um. In this case, the performance of the back contact cell 100 can be optimized.

[0108] In an embodiment of the present application, the spacing between the first isolated doped portion 40 and the first polarity doped layer 20 is preferably greater than or equal to 3um and less than the width of the spacer region 123 minus 6um, and the spacing between the first isolated doped portion 40 and the second polarity doped layer 30 is also greater than or equal to 3um and less than the width of the spacer region 123 minus 6um. In this way, the surface recombination of the spacer region 123 can be greatly reduced, so that the carrier collection rate reaches an optimal state.

[0109] In some embodiments, the plurality of first isolated doped portions 40 may be randomly distributed on the spacer 123 , or the plurality of first isolated doped portions 40 may be arranged at intervals along the second direction on the spacer 123 , which is not specifically limited herein.

[0110] When a plurality of first isolated doped portions 40 are randomly distributed on the spacing region 123 , the distance between any two first isolated doped portions 40 (ie, the length of the connection between any two first isolated doped portions 40 ) is 30 um-380 um.

[0111] See also Figure 3 In some embodiments, a plurality of the first isolated doped portions 40 are arranged on the spacing region 123 at intervals along the second direction, and a distance L4 between two adjacent first isolated doped portions 40 may be 30 um-380 um.

[0112] In this way, it is possible to avoid the first isolated doped regions 40 being too densely packed due to the spacing between the first isolated doped regions 40 being too small.

[0113] Specifically, when several first isolated doped portions 40 are randomly distributed on the spacing area 123, the spacing between any two first isolated doped portions 40 may be, for example, 30um, 35um, 40um, 45um, 50um, 55um, 60um, 65um, 70um, 75um, 80um, 85um, 90um, 95um, 100um, 120um, 140um, 160um, 180um, 200um, 220um, 240um, 260um, 280um, 300um, 320um, 340um, 360um, 380um or any value between 30um-380um.

[0114] When a plurality of first isolated doped portions 40 may also be arranged in the spacing area 123 at intervals along the second direction, the spacing L4 between two adjacent first isolated doped portions 40 may be, for example, 30um, 35um, 40um, 45um, 50um, 55um, 60um, 65um, 70um, 75um, 80um, 85um, 90um, 95um, 100um, 120um, 140um, 160um, 180um, 200um, 220um, 240um, 260um, 280um, 300um, 320um, 340um, 360um, 380um or any value between 30um and 380um.

[0115] See also Figure 4 In some embodiments, the thickness H1 of the first isolated doped portion 40 may be 20 nm-450 nm.

[0116] Thus, by setting the thickness of the first isolated doped portion 40 within this range, it is possible to avoid the first isolated doped portion 40 being too thin to achieve an efficient floating junction passivation effect, and it is also possible to avoid the first isolated doped portion 40 being too thick to increase costs.

[0117] Specifically, the thickness H1 of the first isolated doped portion 40 may be, for example, 20 nm, 22 nm, 24 nm, 26 nm, 28 nm, 30 nm, 32 nm, 34 nm, 36 nm, 38 nm, 40 nm, 42 nm, 44 nm, 46 nm, 48 nm, 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, or any value between 20 nm and 450 nm.

[0118] In some embodiments, the ratio of the orthographic projection area of all the first isolated doped portions 40 in a single spacer 123 in the thickness direction of the silicon wafer 10 to the orthographic projection area of a single spacer 123 in the thickness direction of the silicon wafer 10 is 0.0001-0.5.

[0119] In this way, it is possible to avoid the area of the first isolated doped portion 40 being too small, which would result in the area of the floating junction passivation region being too small and failing to achieve the expected effect. It is also possible to avoid the area of the first isolated doped portion 40 being too large, which would result in excessive saturation of carriers in the first isolated doped portion 40 and, in turn, a reduction in the number of carriers collected by the first polarity doped layer 20. At the same time, it is also possible to avoid the area of the first isolated doped portion 40 being too large, which would result in excessive parasitic absorption of back light and a significant reduction in the double-sidedness.

[0120] That is to say, in such an embodiment, setting the area ratio of the two within this reasonable range can improve the carrier collection rate while ensuring the number of carriers collected. Through such an optimized design, the relationship between the carrier collection rate and the collection number can be balanced, thereby optimizing the conversion efficiency of the back contact battery 100.

[0121] In such an embodiment, the area ratio of the two can be preferably 0.001-0.1. In this way, through this optimized design, the relationship between bifaciality and efficiency can be balanced, and the conversion efficiency of the back-contact cell 100 can be improved while also achieving a better bifaciality of the back-contact cell 100.

[0122] See also Figure 5 In some embodiments, a plurality of first arc-shaped recessed regions 21 are formed on the sidewall surface of the first polarity doped layer 20 adjacent to the spacer region. The plurality of first arc-shaped recessed regions 21 are arranged along the second direction. Two adjacent first arc-shaped recessed regions 21 intersect with each other. The first isolated doping portion 40 is arranged near the junction of the two adjacent first arc-shaped recessed regions 21.

[0123] Thus, the provision of the first curved recessed region 21 helps reduce the carrier recombination rate in the first polarity doped layer 20 near the spacer region 123, thereby improving the carrier collection rate. Furthermore, the preparation process of the first curved recessed region 21 is simple, causing minimal damage to the first polarity doped layer 20, facilitating the subsequent deposition of the back passivation film 50, thereby improving the passivation performance of the back-contact cell 100. Furthermore, positioning the first isolated doped portion 40 near the junction of two first curved recessed regions 21 can further enhance the field passivation effect.

[0124] Specifically, in this embodiment, the shape of the first arc-shaped recessed region 21 can be a regular arc shape, such as a circular arc, or an irregular arc shape with different curvatures at different locations, without limitation. The intersection of two adjacent first arc-shaped recessed regions 21 means that the sidewall surface of the first polarity doped layer 20 adjacent to the spacer region is composed of multiple first arc-shaped recessed regions 21. In other words, the profile of the sidewall surface of the first polarity doped layer 20 adjacent to the spacer region is substantially a wavy curve.

[0125] In such an embodiment, the distance between the first isolated doped portion 40 and the intersection of two adjacent first arc-shaped recessed regions 21 is greater than or equal to 300 nm.

[0126] See also Figure 4 In some embodiments, within the spacer region 123, the silicon wafer 10 has a first isolated protrusion 1231. The first isolated doped portion 40 is disposed on the first isolated protrusion 1231 and covers at least a portion of the first isolated protrusion 1231. Thus, the provision of the first isolated protrusion 1231 can enhance the passivation effect of the subsequent back-surface passivation film 50.

[0127] Specifically, in such an embodiment, in the embodiment of the present application, the spacer region 123 and the second region 122 are more recessed into the silicon wafer 10 than the first region 121 , and the surface of the first isolated protrusion 1231 can be flush with the surface of the stacked first polarity doped layer 20 .

[0128] In one possible embodiment, during the manufacturing process, the first polarity doping layer 20 can be first deposited on the entire back surface 12 of the silicon wafer 10, and then the first polarity doping layer 20 on a part of the area can be removed by etching (laser etching, wet etching), etc., thereby forming a plurality of first polarity doping layers 20 arranged along the first direction, and retaining some independent first isolated doping parts 40. It can be understood that during the removal process, a groove will be formed on the silicon wafer 10, and a first isolated doping part 40 with a protrusion relative to the groove will be formed below the first isolated doping part 40. The convex portion 1231 is formed. Subsequently, a second polarity doped layer 30 can be formed in the groove. The second polarity doped layer 30 is spaced apart from the first polarity doped layer 20. In this way, the region corresponding to the first polarity doped layer 20 is the first region 121, and the region corresponding to the second polarity doped layer 30 is the second region 122. The region where the first polarity doped layer 20 and the second polarity doped layer 30 are located is the spacer region 123. The silicon wafer 10 has a first isolated convex portion 1231 in the spacer region 123, and the first isolated doped portion 40 is disposed on the first isolated convex portion 1231. Of course, it is understood that in other embodiments, other methods can also be used to prepare the back-contact cell 100. The specific method is not limited here, and it only needs to be able to form the structure corresponding to the present application.

[0129] See also Figure 6 In some embodiments, the first isolated doping portion completely covers the first isolated protrusion 1231 , and the first isolated doping portion 40 has a first suspended segment 41 extending beyond the first isolated protrusion 1231 and suspended in the spacer 123 .

[0130] In this way, by providing the first isolated doped portion 40 with a first suspended section 41 extending and suspended above the spacer 123, a deposition region is provided between the first suspended section 41 and the silicon wafer 10. During the subsequent deposition of the back passivation film 50, the provision of such a deposition region can suppress the sufficient exchange of plasma components in the region with plasma components outside the region, thereby achieving a localized distribution of the mobile hydrogen content of the back passivation film 50 on the back surface 12, resulting in a lower mobile hydrogen content in the back passivation film 50 within the deposition region and a higher mobile hydrogen content in the remaining regions, thereby achieving optimal passivation and anti-attenuation effects. At the same time, the direct bombardment of the plasma on the silicon wafer can be reduced, reducing bombardment damage.

[0131] Specifically, in such an embodiment, the first suspended section 41 may extend in any direction and be suspended on the spacer 123 , and there is no restriction on the extending direction of the first suspended section 41 .

[0132] The extension length of the first suspended section 41 relative to the first isolated protrusion 1231 may be 0.2um-50um, for example, 0.2um, 0.4um, 0.6um, 0.8um, 1um, 2um, 3um, 4um, 5um, 6um, 7um, 8um, 9um, 10um, 20um, 30um, 40um, 50um or any value between 0.2um-50um.

[0133] Please continue reading Figure 6 In some embodiments, a second isolated doped portion 80 is provided on the surface of the first suspended section 41 facing the silicon wafer 10. The second isolated doped portion 80 has a polarity opposite to that of the first polarity doped layer 20 and the same polarity as that of the second polarity doped layer 30. The second isolated doped portion 80 is spaced apart from and does not contact the first polarity doped layer 20 and the second polarity doped layer 30.

[0134] Thus, by disposing the second isolated doped portion 80 with different polarities on the surface of the first suspended segment 41 facing the silicon wafer 10 , the passivation effect on the first suspended segment 41 can be enhanced, thereby enhancing the passivation effect of the entire spacer region 123 .

[0135] Specifically, in such an embodiment, the second isolated doped portion 80 located on the first suspended segment 41 may be a single, continuous doped portion, or may include a plurality of mutually independent second isolated doped portions 80 on the first suspended segment 41. In such an embodiment, the second isolated doped portion 80 may directly contact the first suspended segment 41 or be insulated and isolated from the first suspended segment 41.

[0136] Further, see Figure 6 In some embodiments, the second isolated doped portion 80 further extends along the side surface of the first isolated protrusion 1231 to the area of the silicon wafer 10 blocked by the first suspended section 41 .

[0137] In this way, the provision of the second isolated doped portion 80 can further enhance the passivation effect on the side surfaces of the first isolated protrusion 1231 and the area blocked by the first suspended section 41 , further enhancing the passivation effect at the spacer 123 .

[0138] See also Figure 7 In some embodiments, a third isolated doping portion 90 may be provided on the side of the first isolated protrusion 1231, and the third isolated doping portion 90 is spaced apart from the first isolated doping portion 40 (i.e., the third isolated doping portion 90 is not in contact with the first isolated doping portion 40), thereby achieving the purpose of improving the passivation effect of the first isolated protrusion 1231.

[0139] See also Figure 8In some embodiments, a fourth isolated doped portion 110 is provided in the area of the silicon wafer 10 blocked by the first suspended section 41 . The polarity of the fourth isolated doped portion 110 is the same as that of the second polarity doped layer 30 . The fourth isolated doped portion 110 is spaced apart from the first polarity doped layer 20 and the second polarity doped layer 30 , that is, the fourth isolated doped portion 110 is not in contact with either the first polarity doped layer 20 or the second polarity doped layer 30 .

[0140] In this way, the fourth isolated doping portion 110 is in contact with the silicon wafer 10 and is not in contact with the first polarity doping layer 20 and the second polarity doping layer 30. In this way, the fourth isolated doping portion 110 of different polarity is set while the first isolated doping portion 40 is set. The first isolated doping portion 40 and the fourth isolated doping portion 110 can both form field passivation in the spacing region 123, thereby improving the passivation effect. Moreover, through the setting of the first isolated doping portion 40 and the fourth isolated doping portion 110, it can improve the collection rate of holes and electrons.

[0141] Specifically, when the doping type of the first isolated doping portion 40 is P-type doping and the doping type of the fourth isolated doping portion 110 is N-type doping, the hole carriers are saturated at the first isolated doping portion 40, which will generate a repulsive force on subsequent hole carriers, so that the hole carriers can be collected more quickly by the first polarity doping layer 20; at the fourth isolated doping portion 110, the electron carriers are saturated, which will generate a repulsive force on subsequent electrons, so that the electrons can be collected more quickly by the second polarity doping layer 30, reducing the probability of holes and electrons recombining in the spacer region 123, thereby improving the carrier collection rate and further improving the efficiency of the back contact battery 100.

[0142] Similarly, when the doping type of the first isolated doping portion 40 is N-type doping and the doping type of the fourth isolated doping portion 110 is P-type doping, at the first isolated doping portion 40, the electron carriers are saturated and filled, which will generate a repulsive force on the subsequent electron carriers, so that the electron carriers can be collected more quickly by the first polarity doping layer 20. At the fourth isolated doping portion 110, the hole carriers are saturated and filled, which will generate a repulsive force on the subsequent holes, so that the holes can be collected more quickly by the second polarity doping layer 30, and there will be no large recombination of holes and electrons in the spacer region 123, thereby improving the carrier collection rate and further improving the efficiency of the back contact battery 100.

[0143] That is, by disposing the first isolated doped portion 40 and the fourth isolated doped portion 110 , the collection rate of holes and electrons at the spacer 123 can be improved, thereby improving the efficiency of the back contact cell 100 .

[0144] Furthermore, in such an embodiment, the fourth isolated doped region 110 is preferably spaced apart from the first isolated convex region 1231 and the first isolated doped region 40, that is, the fourth isolated doped region 110 is preferably not in contact with the first isolated convex region 1231. Thus, by disposing the fourth isolated doped region 110 so as not to be in contact with either the first isolated convex region 1231 or the first isolated doped region 40, the collection rate of holes and electrons can be further improved, thereby further improving the efficiency of the back-contact cell 100.

[0145] See also Figure 8 In some embodiments, in the first direction, a distance between the fourth isolated doped portion 110 and the first isolated protrusion 1231 is 0.1 um-200 um.

[0146] In this way, by setting the distance between the fourth isolated doped portion 110 and the first isolated protrusion 1231 to 0.1 um-200 um, the carrier collection rate can be further optimized and the surface recombination can be further reduced.

[0147] Specifically, in such an embodiment, the spacing between the fourth isolated doping portion 110 and the first isolated protrusion 1231 may be, for example, 0.1um, 0.2um, 0.4um, 0.6um, 0.8um, 1um, 2um, 3um, 4um, 5um, 6um, 7um, 8um, 9um, 10um, 20um, 30um, 40um, 50um, 60um, 70um, 80um, 90um, 100um, 120um, 140um, 160um, 180um, 200um or any value between 0.1um-200um.

[0148] See also Figure 9 and Figure 10 In some embodiments, the back contact cell 100 may include a plurality of fifth isolated doped portions 120, and the plurality of fifth isolated doped portions 120 are all arranged in the spacing area 123. The fifth isolated doped portion 120 is spaced apart from the first polarity doped layer 20 and the second polarity doped layer 30, and the polarity of the fifth isolated doped portion 120 is the same as that of the second polarity doped layer 30.

[0149] In this way, by simultaneously arranging several first isolated doped portions 40 and second fifth isolated doped portions of different polarities in the spacing region 123, both the first isolated doped portion 40 and the fifth isolated doped portion 120 can form field passivation in the spacing region 123, thereby improving the passivation effect and improving the collection rate of holes and electrons.

[0150] Specifically, when the doping type of the first isolated doping portion 40 is P-type doping and the doping type of the fifth isolated doping portion 120 is N-type doping, the hole carriers are saturated at the first isolated doping portion 40, which will generate a repulsive force on subsequent hole carriers, so that the hole carriers can be collected more quickly by the first polarity doping layer 20; at the fifth isolated doping portion 120, the electron carriers are saturated, which will generate a repulsive force on subsequent electrons, so that the electrons can be collected more quickly by the second polarity doping layer 30, reducing the probability of holes and electrons recombining in the spacer region 123, thereby improving the carrier collection rate and further improving the efficiency of the back contact battery 100.

[0151] Similarly, when the doping type of the first isolated doping portion 40 is N-type doping and the doping type of the fifth isolated doping portion 120 is P-type doping, at the first isolated doping portion 40, the electron carriers are saturated, which will generate a repulsive force on subsequent electron carriers, so that the electron carriers can be collected more quickly by the first polarity doping layer 20. At the fifth isolated doping portion 120, the hole carriers are saturated, which will generate a repulsive force on subsequent holes, so that the holes can be collected more quickly by the second polarity doping layer 30, and there will be no large recombination of holes and electrons in the spacer region 123, thereby improving the carrier collection rate and further improving the efficiency of the back contact battery 100.

[0152] That is, by providing the first isolated doped portion 40 and the fifth isolated doped portion 120 , the collection rate of holes and electrons at the spacer 123 can be improved, thereby improving the efficiency of the back contact cell 100 .

[0153] In such an embodiment, no electrode is provided on the fifth isolated doped region 120 , that is, the first electrode 60 and the second electrode 70 are physically separated from and do not contact the fifth isolated doped region 120 .

[0154] In an embodiment of the present application, the specific shape of the fifth isolated doping portion 120 can be a regular shape or an irregular shape. For example, in some embodiments, the shape of the first isolated doping portion 40 can be one or more of a cone, a pyramid, a prism, and a truncated cone, which is not specifically limited here.

[0155] Furthermore, in such an embodiment, the fifth isolated doped region 120 and the first isolated doped region 40 are spaced apart in the spacer region 123 , that is, the fifth isolated doped region 120 and the first isolated doped region 40 are independent of each other and do not contact each other.

[0156] In this way, by disposing the fifth isolated doped portion 120 to be independent of and not in contact with the first isolated doped portion 40 , the collection rate of holes and electrons can be further improved, thereby further improving the efficiency of the back-contact cell 100 .

[0157] Furthermore, in some embodiments, the distance between any one of the fifth isolated doping portions 120 and any one of the first isolated doping portions 40 (ie, the length of the connection between any one of the first isolated doping portions 40 and any one of the fifth doping portions) is greater than or equal to 0.1 um-200 um.

[0158] In this way, by setting the distance between the fifth isolated doped portion 120 and the first isolated protrusion 1231 to 0.1 um-200 um, the carrier collection rate can be further optimized and the surface recombination can be further reduced.

[0159] Specifically, the spacing between any one of the fifth isolated doping portions 120 and any one of the first isolated doping portions 40 may be, for example, 0.1um, 0.2um, 0.4um, 0.6um, 0.8um, 1um, 2um, 3um, 4um, 5um, 6um, 7um, 8um, 9um, 10um, 20um, 30um, 40um, 50um, 60um, 70um, 80um, 90um, 100um, 120um, 140um, 160um, 180um, 200um or any value between 0.1um-200um.

[0160] See also Figure 10 In some embodiments, in the first direction, a distance L5 between the fifth isolated doped portion 120 and the second polarity doped layer 30 is greater than or equal to 300 nm.

[0161] In this way, the spacing between the fifth isolated doped portion 120 and the second polarity doped layer 30 can be avoided to be too small, resulting in poor isolation effect between the fifth isolated doped portion 120 and the second polarity doped layer 30. That is, such a setting can improve the isolation effect between the fifth isolated doped portion 120 and the second polarity doped layer 30, so that the carrier collection rate reaches a better state, and at the same time, it can also improve the passivation effect of the spacer region 123.

[0162] Specifically, it is not difficult to understand that if the distance between the two is too small (i.e., less than 300 nm), the electrical isolation effect between the fifth isolated doping portion 120 and the second polarity doping layer 30 is poor, which is equivalent to the fifth isolated doping portion 120 being connected to the second polarity doping layer 30, which easily leads to the carriers at the fifth isolated doping portion 120 being directly collected by the second polarity doping layer 30, and the corresponding carriers cannot be saturated at the fifth isolated doping portion 120, thereby failing to achieve the function of repelling holes or electrons at the fifth isolated doping portion 120, resulting in a significant decrease in the effect of reducing surface recombination.

[0163] That is, in the present application, by setting the distance L5 between the fifth isolated doped portion 120 and the second polarity doped layer 30 to be greater than or equal to 300 nm, the surface recombination of the spacer region 123 can be significantly reduced, so that the carrier collection rate reaches a better state.

[0164] Specifically, in such an embodiment, the size of the spacing L5 between the fifth isolated doping portion 120 and the second polarity doping layer 30 may be, for example, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1um, 2um, 3um, 4um, 5um, 6um, 7um, 8um, 9um, 10um, 11um, 12um, 13um, 14um, 15um, 16um, 17um, 18um, 19um, 20um and other values.

[0165] The maximum distance between the fifth isolated doped portion 120 and the first polarity doped layer 20 may preferably be the width of the spacing region 123 in the first direction minus 6 um, that is, 300 nm ≤ L5 ≤ L2 −6 um.

[0166] Through research, it is found that L5 is preferably greater than or equal to 3um and less than or equal to L2-6um. In this case, the performance of the back contact battery 100 can be optimized.

[0167] Please continue reading Figure 10 In some embodiments, in the first direction, a distance L6 between the fifth isolated doped portion 120 and the first polarity doped layer 20 is greater than or equal to 300 nm.

[0168] In this way, by setting the distance between the fifth isolated doping portion 120 and the first polarity doping layer 20 to be greater than 300 nm, the isolation effect between the fifth isolated doping portion 120 and the first polarity doping layer 20 can be ensured, and it is avoided that part of the carriers at the fifth isolated doping portion 120 directly recombine with the carriers at the first polarity doping layer 20, resulting in the carriers of the fifth isolated doping portion 120 being unable to reach saturation, thereby significantly reducing the effect of reducing surface recombination.

[0169] Specifically, it is not difficult to understand that if the distance between the two is too small (i.e., less than 300 nm), it is equivalent to the fifth isolated doping portion 120 being connected to the first polarity doping layer 20, which can easily cause the carriers (such as holes) at the fifth isolated doping portion 120 to directly recombine with the carriers (such as electrons) of the first polarity doping layer 20, and the corresponding carriers (such as holes) cannot be saturated at the fifth isolated doping portion 120, thereby failing to achieve the function of repelling holes or electrons at the fifth isolated doping portion 120, resulting in a significant reduction in the effect of reducing surface recombination.

[0170] That is to say, in the present application, by setting the distance L6 between the fifth isolated doped portion 120 and the first polarity doped layer 20 to be greater than or equal to 300 nm, the surface recombination of the spacer region 123 can be significantly reduced, so that the carrier collection rate reaches a better state.

[0171] Specifically, in such an embodiment, the distance L6 between the fifth isolated doped portion 120 and the first polarity doped layer 20 may be, for example, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1 um, 2 um, 3 um, 4 um, 5 um, 6 um, 7 um, 8 um, 9 um, 10 um, 11 um, 12 um, 13 um, 14 um, 15 um, 16 um, 17 um, 18 um, 19 um, 20 um, etc. The maximum distance between the fifth isolated doped portion 120 and the first polarity doped layer 20 may preferably be the width of the spacer 123 in the first direction minus 6 um, i.e., 300 nm ≤ L6 ≤ L2-6 um. Studies have shown that L6 is most preferably greater than or equal to 3 um and less than or equal to L2-6 um. In this case, the performance of the back contact cell 100 can be optimized.

[0172] In an embodiment of the present application, it is preferred that the spacing L1 between the fifth isolated doping portion 120 and the first polarity doping layer 20 is greater than or equal to 3um, and the spacing L5 between the fifth isolated doping portion 120 and the second polarity doping layer 30 is also greater than or equal to 3um. In this way, the surface recombination of the spacer region 123 can be greatly reduced, so that the carrier collection rate reaches an optimal state.

[0173] In some embodiments, the plurality of fifth isolated doped portions 120 may be randomly distributed on the spacer 123 , or the plurality of fifth isolated doped portions 120 may be arranged on the spacer 123 at intervals along the second direction, which is not specifically limited herein.

[0174] When a plurality of fifth isolated doped portions 120 are randomly distributed on the spacing region 123 , the distance between any two fifth isolated doped portions 120 (ie, the length of the connection between any two fifth isolated doped portions 120 ) is 30 um-380 um.

[0175] See also Figure 9 In some embodiments, a plurality of the fifth isolated doped portions 120 are arranged on the spacing region 123 at intervals along the second direction, and a distance L7 between two adjacent fifth isolated doped portions 120 may be 30 um-380 um.

[0176] In this way, it is possible to avoid the fifth isolated doped regions 120 being too densely packed due to the spacing between the fifth isolated doped regions 120 being too small.

[0177] Specifically, when several fifth isolated doped portions 120 are randomly distributed on the spacing area 123, the spacing between any two fifth isolated doped portions 120 may be, for example, 30um, 35um, 40um, 45um, 50um, 55um, 60um, 65um, 70um, 75um, 80um, 85um, 90um, 95um, 100um, 120um, 140um, 160um, 180um, 200um, 220um, 240um, 260um, 280um, 300um, 320um, 340um, 360um, 380um or any value between 30um-380um.

[0178] When several fifth isolated doped portions 120 may also be arranged in the spacing area 123 at intervals along the second direction, the size of the spacing L7 between two adjacent fifth isolated doped portions 120 may be, for example, 30um, 35um, 40um, 45um, 50um, 55um, 60um, 65um, 70um, 75um, 80um, 85um, 90um, 95um, 100um, 120um, 140um, 160um, 180um, 200um, 220um, 240um, 260um, 280um, 300um, 320um, 340um, 360um, 380um or any value between 30um-380um.

[0179] See also Figure 10 In some embodiments, the thickness H2 of the fifth isolated doped portion 120 may be 20 nm-450 nm.

[0180] Thus, by setting the thickness of the fifth isolated doped portion 120 within this range, it is possible to avoid the fifth isolated doped portion 120 being too thin to achieve an efficient floating junction passivation effect, and it is also possible to avoid the fifth isolated doped portion 120 being too thick to increase costs.

[0181] Specifically, the thickness H2 of the fifth isolated doped portion 120 may be, for example, 20 nm, 22 nm, 24 nm, 26 nm, 28 nm, 30 nm, 32 nm, 34 nm, 36 nm, 38 nm, 40 nm, 42 nm, 44 nm, 46 nm, 48 nm, 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm or any value between 20 nm and 450 nm.

[0182] In some embodiments, the ratio of the orthographic projection area of all the fifth isolated doped portions 120 in a single spacer 123 in the thickness direction of the silicon wafer 10 to the orthographic projection area of a single spacer 123 in the thickness direction of the silicon wafer 10 is 0.0001-0.5.

[0183] In this way, it is possible to avoid the area of the fifth isolated doped portion 120 being too small, which would result in the area of the floating junction passivation region being too small and unable to achieve the expected effect; it is also possible to avoid the area of the fifth isolated doped portion 120 being too large, which would result in excessive saturation of carriers in the fifth isolated doped portion 120 and, in turn, a reduction in the number of carriers collected by the first polarity doping layer 20; and it is also possible to avoid the area of the fifth isolated doped portion 120 being too large, which would result in excessive parasitic absorption of back light and a significant reduction in the double-sidedness.

[0184] That is to say, in such an embodiment, setting the area ratio of the two within this reasonable range can improve the carrier collection rate while ensuring the number of carriers collected. Through such an optimized design, the relationship between the carrier collection rate and the collection number can be balanced, thereby optimizing the conversion efficiency of the back contact battery 100.

[0185] Specifically, the ratio may be, for example, 0.0001, 0.0005, 0.001, 0.0015, 0.002, 0.004, 0.006, 0.008, 0.01, 0.02, 0.03, 0.04, 0.05, 0.06, 0.07, 0.08, 0.09, 0.1, 0.15, 0.2, 0.25, 0.3, 0.35, 0.4, 0.45, or 0.5.

[0186] In such an embodiment, the area ratio of the two can be preferably 0.001-0.1. In this way, through this optimized design, the relationship between bifaciality and efficiency can be balanced, and the conversion efficiency of the back-contact cell 100 can be improved while also achieving a better bifaciality of the back-contact cell 100.

[0187] See also Figure 11 In some embodiments, a plurality of second arc-shaped recessed regions 31 are formed on the sidewall surface of the second polarity doping layer 30 adjacent to the spacer region. The plurality of second arc-shaped recessed regions 31 are arranged along the second direction. Two adjacent second arc-shaped recessed regions 31 intersect with each other. The fifth isolated doping portion 120 is arranged near the junction of the two adjacent second arc-shaped recessed regions 31.

[0188] Thus, the provision of the second curved recessed region 31 helps reduce the carrier recombination rate in the second polarity doped layer 30 near the spacer region 123, thereby improving the carrier collection rate. Furthermore, the preparation process of the second curved recessed region 31 is simple, causing minimal damage to the first polarity doped layer 20, facilitating the subsequent deposition of the back passivation film 50, thereby improving the passivation performance of the back-contact cell 100. Furthermore, placing the fifth isolated doped portion 120 near the junction of two adjacent second curved recessed regions 31 can further enhance the field passivation effect.

[0189] Specifically, in this embodiment, the shape of the second arc-shaped recessed region 31 can be a regular arc shape, such as a circular arc, or an irregular arc shape with different curvatures at different locations, without limitation. The intersection of two adjacent first arc-shaped recessed regions 31 means that the sidewall surface of the second polarity doped layer 30 adjacent to the spacer region is composed of multiple first arc-shaped recessed regions 31. In other words, the profile of the sidewall surface of the second polarity doped layer 30 adjacent to the spacer region is substantially a wavy curve.

[0190] In such an embodiment, the distance between the fifth isolated doped portion 120 and the intersection of two adjacent first arc-shaped recessed regions is greater than or equal to 300 nm.

[0191] See also Figure 12 In some embodiments, a groove 1232 is formed in the spacer region 123 , and a second isolated protrusion 1233 is provided in the groove 1232 . The fifth isolated doping portion 120 is disposed on the second isolated protrusion 1233 and covers at least a portion of the second isolated protrusion 1233 .

[0192] In this way, by providing the groove 1232 and the second isolated protrusion 1233 , the isolation effect between the first polarity doped layer 20 and the second polarity doped layer 30 can be further improved, and the passivation effect of the subsequent back passivation film layer 50 can be improved.

[0193] Specifically, in such an embodiment, in the embodiment of the present application, the spacer region and the second region 122 are more recessed into the silicon wafer 10 than the first region 121, and the surface of the first isolated protrusion 1231 can be flush with the surface of the laminated first polarity doped layer 20. In one possible embodiment, during the manufacturing process, the first polarity doped layer 20 can be first deposited on the entire back surface 12 of the silicon wafer 10, and then the first polarity doped layer 20 on some areas can be removed by etching (laser etching, wet etching), etc., thereby forming a plurality of first polarity doped layers 20 arranged along the first direction, while retaining some independent first isolated doped portions 40. It can be understood that during the removal process, a groove will be formed on the silicon wafer 10, and a first isolated protrusion 1231 protruding relative to the groove will be formed below the first isolated doped portion 40.

[0194] Subsequently, a second polarity doped layer 30 may be formed within the groove, and then the second polarity doped layer 30 may be partially removed (e.g., by laser etching or wet etching) to form a groove 1232. In addition, an independent second isolated protrusion 1233 and a fifth isolated doped portion 120 may be formed within the groove 1232. Thus, the region corresponding to the first polarity doped layer 20 is the first region 121, the region corresponding to the second polarity doped layer 30 is the second region 122, and the region where the first polarity doped layer 20 and the second polarity doped layer 30 are located is the spacer region 123. The silicon wafer 10 has a first isolated protrusion 1231 and a second isolated protrusion 1233 in the spacer region 123. The first isolated doped portion 40 is disposed on the first isolated protrusion 1231, and the fifth isolated doped portion 120 is disposed on the second isolated protrusion 1233. Of course, it is understood that in other embodiments, other methods may be used to prepare the back-contact cell 100, which are not specifically limited herein, as long as they can form the structure corresponding to the present application.

[0195] In some embodiments, the fifth isolated doped portion 120 only covers a portion of the second isolated protrusion 1233 .

[0196] In this way, the cross section of the fifth isolated doped portion 120 can be prevented from being exposed at the cross section of the trench 1232 , thereby reducing the recombination of the space charge region.

[0197] See also Figure 12 In other embodiments, the fifth isolated doping completely covers the second isolated protrusion 1233, and the fifth isolated doping portion 120 has a second suspended section 1201 extending beyond the second isolated protrusion 1233 and suspended in the spacing region 123. Specifically, the second suspended section 1201 is suspended above the groove 1232.

[0198] In this way, by providing the fifth isolated doped portion 120 with a second suspended section 1201 extending and suspended above the spacer 123, a deposition region is provided between the second suspended section 1201 and the silicon wafer 10. During the subsequent deposition of the back passivation film 50, the provision of such a deposition region can suppress the sufficient exchange of plasma components in the region with plasma components outside the region, thereby achieving a localized distribution of the mobile hydrogen content of the back passivation film 50 on the back surface 12, making the mobile hydrogen content of the back passivation film 50 in the deposition region lower and the mobile hydrogen content of the back passivation film 50 in the remaining regions higher, thereby achieving optimal passivation and anti-attenuation effects. At the same time, the direct bombardment of the plasma on the silicon wafer can be reduced, reducing bombardment damage.

[0199] Specifically, in such an embodiment, the second suspended segment 1201 can extend in any direction and be suspended above the groove 1232, and there is no particular restriction on the extension direction of the second suspended segment 1201. The extension length of the second suspended segment 1201 relative to the second isolated protrusion 1233 can be 0.2 μm-50 μm, for example, 0.2 μm, 0.4 μm, 0.6 μm, 0.8 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, or any value between 0.2 μm and 50 μm.

[0200] See also Figure 13 In some embodiments, at at least a portion of the first polarity doped layer 20, the first polarity doped layer 20 has a third suspended segment 21 extending to the spacer 123, the third suspended segment 21 is suspended on a portion of the spacer 123, and the first isolated doped portion 40 is arranged on an area of the spacer 123 that is not blocked by the third suspended segment 21.

[0201] In this way, by setting the third suspended section 21, a deposition area with a relative spacing can be provided between the third suspended section 21 and the bottom of the spacer 123. During the subsequent deposition of the back passivation film layer 50, the setting of such a deposition area can inhibit the sufficient exchange of plasma components in the area with plasma components outside the area, thereby achieving a localized distribution of the mobile hydrogen content of the back passivation film layer 50 on the back surface 12, so that the mobile hydrogen content of the back passivation film layer 50 in the deposition area is lower, and the mobile hydrogen content of the back passivation film layer 50 in the remaining areas is higher, so as to achieve the best passivation and anti-attenuation effect. At the same time, it can reduce the direct bombardment of the plasma on the silicon wafer and reduce bombardment damage.

[0202] See also Figure 14 In some embodiments, a sixth isolated doped portion 130 is provided on the surface of the third suspended segment 21 facing the silicon wafer 10 , and the polarity of the sixth isolated doped portion 130 is the same as the polarity of the second polarity doped layer 30 .

[0203] Thus, by disposing the sixth isolated doped portion 130 with different polarities on the surface of the third suspended segment 21 facing the silicon wafer 10 , the passivation effect on the third suspended segment 21 can be enhanced, thereby enhancing the passivation effect of the entire spacer region 123 .

[0204] Specifically, in such an embodiment, the sixth isolated doped portion 130 located on the third suspended segment 21 may be a single, continuous doped portion, or may include a plurality of independent sixth isolated doped portions 130 on the third suspended segment 21. In such an embodiment, the sixth isolated doped portion 130 may directly contact the third suspended segment 21 or be insulated and isolated from the third suspended segment 21.

[0205] In some embodiments, the third suspended segment 21 may further extend to the area of the silicon wafer 10 blocked by the third suspended segment 21 , thereby further enhancing the passivation effect of the spacer 123 .

[0206] See also Figure 15 In some embodiments, a seventh isolated doped portion 140 is provided in the area of the silicon wafer 10 blocked by the third suspended section 21. The polarity of the seventh isolated doped portion 140 is the same as that of the second polarity doped layer 30. The seventh isolated doped portion 140 is spaced apart from the first polarity doped layer 20 and the second polarity doped layer 30, that is, the seventh isolated doped portion 140 is not in contact with either the first polarity doped layer 20 or the second polarity doped layer 30.

[0207] In this way, the seventh isolated doping portion 140 is in contact with the silicon wafer 10 and is not in contact with the first polarity doping layer 20 and the second polarity doping layer 30. In this way, the seventh isolated doping portion 140 of different polarity is set while the first isolated doping portion 40 is set. The first isolated doping portion 40 and the seventh isolated doping portion 140 can both form field passivation in the spacing region 123, thereby improving the passivation effect. Moreover, through the setting of the first isolated doping portion 40 and the seventh isolated doping portion 140, it can improve the collection rate of holes and electrons.

[0208] Specifically, when the doping type of the first isolated doping portion 40 is P-type doping and the doping type of the seventh isolated doping portion 140 is N-type doping, the hole carriers are saturated at the first isolated doping portion 40, which will generate a repulsive force on subsequent hole carriers, so that the hole carriers can be collected more quickly by the first polarity doping layer 20; at the seventh isolated doping portion 140, the electron carriers are saturated, which will generate a repulsive force on subsequent electrons, so that the electrons can be collected more quickly by the second polarity doping layer 30, reducing the probability of holes and electrons recombining in the spacer region 123, thereby improving the carrier collection rate and further improving the efficiency of the back contact battery 100.

[0209] Similarly, when the doping type of the first isolated doping portion 40 is N-type doping and the doping type of the seventh isolated doping portion 140 is P-type doping, at the first isolated doping portion 40, the electron carriers are saturated and filled, which will generate a repulsive force on the subsequent electron carriers, so that the electron carriers can be collected more quickly by the first polarity doping layer 20. At the seventh isolated doping portion 140, the hole carriers are saturated and filled, which will generate a repulsive force on the subsequent holes, so that the holes can be collected more quickly by the second polarity doping layer 30, and there will be no large recombination of holes and electrons in the spacer region 123, thereby improving the carrier collection rate and further improving the efficiency of the back contact battery 100.

[0210] That is, by providing the first isolated doped portion 40 and the seventh isolated doped portion 140 , the collection rate of holes and electrons at the spacer 123 can be improved, thereby improving the efficiency of the back contact cell 100 .

[0211] Furthermore, in such an embodiment, the seventh isolated doped region 140 is preferably spaced apart from the first isolated doped region 40, that is, the seventh isolated doped region 140 is preferably not in contact with the first isolated doped region 40. Thus, by disposing the seventh isolated doped region 140 so as not to be in contact with the first isolated doped region 40, the collection rate of holes and electrons can be further improved, thereby further improving the efficiency of the back-contact cell 100.

[0212] See also Figure 16 In some embodiments, the silicon wafer 10 has a silicon wafer extension portion 13 extending onto the spacer 120 and suspended in the spacer 123 , and at least a portion of the third suspended segment 21 is stacked on the silicon wafer extension portion 13 .

[0213] Thus, the provision of the silicon wafer extension 13 can prevent the third suspended segment 21 from breaking during the fabrication process and falling into the spacer 123, causing defects. It can also further suppress the exchange of plasma components in this region with those outside the region, thereby achieving optimal passivation and anti-attenuation effects. Furthermore, it can further reduce direct plasma bombardment of the silicon wafer, thereby minimizing damage from such bombardment.

[0214] See also Figure 17 In some embodiments, the surface of the silicon extension portion 13 facing away from the third suspended segment 21 has an eighth isolated doped portion 150 , and the polarity of the eighth isolated doped portion 150 is the same as the polarity of the second polarity doped layer 30 .

[0215] In this way, by setting the eighth isolated doped portion 150 on the silicon wafer extension portion 13, the passivation effect on the silicon wafer extension portion 13 can be improved, thereby improving the passivation effect at the entire spacing area 123. At the same time, the setting of the eighth isolated doped portion 150 can also form a floating junction passivation, thereby further improving the carrier collection rate.

[0216] In some embodiments, the eighth isolated doped region 150 may be preferably spaced apart from the first isolated doped region 40 , so as to further optimize the carrier collection efficiency of the back-contact cell 100 .

[0217] Throughout this specification, reference to terms such as "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described herein may be combined in any suitable manner in any one or more embodiments or examples.

[0218] In addition, the above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A back contact battery, characterized in that: include: A silicon wafer having a front side and a back side facing each other, the back side comprising first and second regions alternately arranged in sequence along a first direction, the first and second regions both extending along a second direction, a spacing region being defined between adjacent first and second regions, and the second direction intersecting the first direction; a first polarity doped layer stacked on the first region; a second polarity doping layer stacked on the second region, wherein the polarity of the second polarity doping layer is opposite to that of the first polarity doping layer; and A plurality of first isolated doped portions are independently arranged in the spacing region and spaced apart from the first polarity doped layer and the second polarity doped layer. The polarity of the first isolated doped portion is the same as that of the first polarity doped layer.

2. The back contact battery according to claim 1, characterized in that In the first direction, a distance between the first isolated doped region and the first polarity doped layer is greater than or equal to 300 nm.

3. The back contact battery according to claim 1, characterized in that In the first direction, a distance between the first isolated doped region and the second polarity doped layer is greater than or equal to 300 nm.

4. The back contact battery according to claim 1, characterized in that A plurality of the first isolated doped portions are randomly distributed on the spacer region; or A plurality of the first isolated doped portions are arranged at intervals along the second direction on the spacing region.

5. The back contact battery according to claim 4, characterized in that A plurality of the first isolated doped portions are arranged at intervals along the second direction on the spacing region. In the second direction, a distance between two adjacent first isolated doped portions is 30 um-380 um.

6. The back contact battery according to claim 1, characterized in that The ratio of the orthographic projection area of all the first isolated doped portions in a single spacer in the thickness direction of the silicon wafer to the orthographic projection area of the single spacer in the thickness direction of the silicon wafer is 0.0001-0.

5.

7. The back contact battery according to claim 6, characterized in that The ratio of the orthographic projection area of all the first isolated doped portions in a single spacer in the thickness direction of the silicon wafer to the orthographic projection area of the single spacer in the thickness direction of the silicon wafer is 0.001-0.

1.

8. The back contact battery according to claim 1, characterized in that The thickness of the first isolated doped portion is 20 nm-450 nm.

9. The back contact battery according to claim 1, characterized in that Several first arc-shaped recessed areas are formed on the sidewall surface adjacent to the first polarity doping layer and the spacer area. The several first arc-shaped recessed areas are arranged along the second direction. Two adjacent first arc-shaped recessed areas intersect with each other. The first isolated doping portion is arranged near the junction of two adjacent first arc-shaped recessed areas.

10. The back contact battery according to claim 1, characterized in that In the spacer region, the silicon wafer has a first isolated protrusion, and the first isolated doped portion is disposed on the first isolated protrusion and covers at least a portion of the first isolated protrusion.

11. The back contact battery according to claim 10, characterized in that The first isolated doped portion completely covers the first isolated protrusion, and the first isolated doped portion has a first suspended segment extending beyond the first isolated protrusion and suspended within the spacer.

12. The back contact battery according to claim 11, characterized in that A second isolated doped portion is provided on a surface of the first suspended segment facing the silicon wafer. The second isolated doped portion has a polarity opposite to that of the first polarity doped layer and the same polarity as that of the second polarity doped layer.

13. The back contact battery according to claim 12, characterized in that The second isolated doped portion is insulated and isolated from the first suspended segment.

14. The back contact battery according to claim 12, characterized in that The second isolated doped portion further extends along the side surface of the first isolated protrusion to an area of the silicon wafer blocked by the first suspended segment.

15. The back contact battery according to claim 11, characterized in that A third isolated doped portion is provided on a side surface of the first isolated protrusion, and the third isolated doped portion is spaced apart from the first isolated doped portion.

16. The back contact battery according to claim 11, characterized in that A fourth isolated doped portion is provided on the area of the silicon wafer blocked by the first suspended segment. The polarity of the fourth isolated doped portion is the same as that of the second polarity doped layer, and the fourth isolated doped portion is spaced apart from the first polarity doped layer and the second polarity doped layer.

17. The back contact battery according to claim 16, characterized in that The fourth isolated doped portion is spaced apart from the first isolated protrusion and the first isolated doped portion.

18. The back contact cell according to claim 17, characterized in that In the first direction, a distance between the fourth isolated doped portion and the first isolated protrusion is 0.1 um-200 um.

19. The back contact cell according to claim 1, characterized in that The back contact battery also includes several fifth isolated doped parts, which are all arranged in the spacing area, and the fifth isolated doped parts are spaced apart from the first polarity doped layer and the second polarity doped layer, and the fifth isolated doped parts have the same polarity as the second polarity doped layer.

20. The back contact cell according to claim 19, characterized in that The fifth isolated doped region is spaced apart from the first isolated doped region in the spacer region.

21. The back contact cell according to claim 20, characterized in that A distance between any one of the fifth isolated doped regions and any one of the first isolated doped regions is greater than or equal to 0.1 um-200 um.

22. The back contact cell according to claim 19, characterized in that In the first direction, a distance between the fifth isolated doped region and the second polarity doped layer is greater than or equal to 300 nm.

23. The back contact cell according to claim 19, characterized in that In the first direction, a distance between the fifth isolated doped region and the first polarity doped layer is greater than or equal to 300 nm.

24. The back contact cell according to claim 19, characterized in that A plurality of the fifth isolated doped portions are randomly distributed on the spacer region; or A plurality of the fifth isolated doped portions are arranged at intervals along the second direction on the spacing region.

25. The back contact cell according to claim 21, characterized in that A plurality of the fifth isolated doped portions are arranged at intervals along the second direction on the spacing region, and a distance between two adjacent fifth isolated doped portions is 30 um-380 um.

26. The back contact cell according to claim 19, characterized in that The ratio of the orthographic projection area of all the fifth isolated doped portions in a single spacer in the thickness direction of the silicon wafer to the orthographic projection area of the single spacer in the thickness direction of the silicon wafer is 0.0001-0.

5.

27. The back contact cell according to claim 26, characterized in that The ratio of the orthographic projection area of all the fifth isolated doped portions in a single spacer in the thickness direction of the silicon wafer to the orthographic projection area of the single spacer in the thickness direction of the silicon wafer is 0.001-0.

1.

28. The back contact cell according to claim 19, characterized in that The thickness of the fifth isolated doped portion is 20 nm-450 nm.

29. The back contact cell according to claim 19, characterized in that Several second arc-shaped recessed areas are formed on the sidewall surface of the second polarity doped layer adjacent to the spacer area, and the several second arc-shaped recessed areas are arranged along the second direction. Two adjacent second arc-shaped recessed areas intersect with each other, and the fifth isolated doped portion is arranged near the junction of two adjacent second arc-shaped recessed areas.

30. The back contact cell according to claim 19, characterized in that A trench is formed in the spacer region, wherein a second isolated protrusion is formed in the trench, and the fifth isolated doped portion is disposed on the second isolated protrusion and covers at least a portion of the second isolated protrusion.

31. The back contact cell according to claim 30, characterized in that The fifth isolated doped portion only covers a portion of the second isolated protrusion; or The fifth isolated doped portion completely covers the second isolated protrusion, and the fifth isolated doped portion has a second suspended segment extending beyond the second isolated protrusion and suspended within the spacer.

32. The back contact cell according to claim 1, characterized in that At at least a portion of the first polarity doped layer, the first polarity doped layer has a third suspended segment extending above the spacer region, the third suspended segment is suspended above a portion of the spacer region, and the first isolated doped portion is arranged on an area of the spacer region that is not blocked by the third suspended segment.

33. The back contact cell according to claim 32, characterized in that A sixth isolated doped portion is provided on a surface of the third suspended segment facing the silicon wafer, and the polarity of the sixth isolated doped portion is the same as the polarity of the second polarity doped layer.

34. The back contact cell according to claim 32, characterized in that A seventh isolated doped portion is provided on the area of the silicon wafer blocked by the third suspended segment. The seventh isolated doped portion is spaced apart from the first polarity doped layer and the second polarity doped layer. The polarity of the seventh isolated doped portion is the same as that of the second polarity doped layer.

35. The back contact cell according to claim 34, characterized in that The seventh isolated doped region is spaced apart from the first isolated doped region.

36. The back contact cell according to claim 32, characterized in that The silicon wafer has a silicon wafer extension portion extending onto the spacer and suspended within the spacer, and at least a portion of the third suspended segment is stacked on the silicon wafer extension portion.

37. The back contact cell according to claim 36, characterized in that An eighth isolated doped portion is provided on a surface of the silicon wafer extension facing away from the third suspended segment. The polarity of the eighth isolated doped portion is the same as the polarity of the second polarity doped layer.

38. The back contact cell according to claim 37, characterized in that The eighth isolated doped region is spaced apart from the first isolated doped region.

39. A battery assembly, characterized in that: A back contact battery comprising any one of several claims 1-38.

40. A photovoltaic system, characterized in that: A battery assembly comprising the battery assembly of claim 39.

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