Level self-locking protection circuit and mobile power supply
By designing a level self-locking protection circuit, the problem that the control chip cannot control the on-off of its own power supply is solved, the controllability of the control chip power supply is realized, and the practicality of the circuit is improved.
Patent Information
- Application Number
- CN202421689680.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-16
- Publication Date
- 2025-08-15
- Estimated Expiration
- 2034-07-16
AI Technical Summary
In the prior art, the control chip cannot control the on-off of its own power supply, and its practicality is poor.
A level self-locking protection circuit is designed, including a power-on self-excitation unit, a switching unit, a self-locking unit, a control chip and a shutdown signal generation unit. By conducting or disconnecting the switching unit based on the level signal output by the power-on self-excitation unit and the shutdown level signal, the control chip power supply is turned on or off.
It improves the practicality of the control chip, realizes the controllability of the control chip power supply, and enhances the functional applicability of the circuit.
Smart Images
Figure CN223231159U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of electronic circuits, in particular to a level self-locking protection circuit and a mobile power supply. Background Art
[0002] A control chip is an integrated circuit chip. In some circuits, the control chip acts as the circuit's control component, controlling the operating states of other devices, such as turning a switch on or off.
[0003] However, the control chip cannot control the on and off of its own power supply, and its practicality is poor. Utility Model Content
[0004] The technical problem to be solved by the embodiments of the present utility model is to provide a level self-locking protection circuit and a mobile power supply to solve the problem in the prior art that the control chip in the circuit cannot control the on and off of its own power supply and has poor practicality.
[0005] The utility model discloses a level self-locking protection circuit, comprising a power-on self-excitation unit, a switch unit, a self-locking unit, a control chip and a shutdown signal generating unit, wherein the power-on self-excitation unit is connected to an external battery and the self-locking unit, the switch unit is arranged between the external battery and the power input end of the control chip, the self-locking unit is connected to the control end of the switch unit, and the shutdown signal generating unit is used to generate a shutdown level signal, wherein the self-locking unit turns on or off the switch unit based on the level signal output by the power-on self-excitation unit and the shutdown level signal.
[0006] Optionally, the self-locking unit includes a first NMOS tube and a high-level holding module, the gate of the first NMOS tube is connected to the high-level holding module, the power-on self-excitation unit, and the shutdown signal generating unit, the source is grounded, and the drain is connected to the control end of the switching unit.
[0007] Optionally, the switching unit includes a PMOS tube, and the high-level maintaining module includes a first resistor, a second resistor and a first diode, the first resistor and the second resistor are connected in series, the series node of the first resistor and the second resistor is connected to the gate of the first NMOS tube, the other end of the first resistor is connected to the negative electrode of the first diode, the other end of the second resistor is grounded, the positive electrode of the first diode is connected to the drain of the PMOS tube and the power input end of the control chip, the gate of the PMOS tube is connected to the drain of the first NMOS tube, and the source of the PMOS tube is connected to an external battery.
[0008] Optionally, the level self-locking protection circuit further includes a second NMOS transistor, the gate of the second NMOS transistor is connected to the shutdown signal generating unit to receive the shutdown level signal, the source is grounded, and the drain is connected to the gate of the first NMOS transistor.
[0009] Optionally, the shutdown signal generating unit includes a button, one end of the button is connected to the control chip, and the other end is grounded, and the control chip outputs a shutdown level signal based on a pressing signal of the button.
[0010] Optionally, the power-on self-excitation unit includes a third resistor and a first capacitor, the third resistor is connected in series with the first capacitor, the other end of the third resistor is connected to an external battery, and the other end of the first capacitor is connected to the gate of the first NMOS tube.
[0011] Optionally, the level self-locking protection circuit further includes a secondary starting unit, and the secondary starting unit is connected to the self-locking unit.
[0012] Optionally, the secondary starting unit includes a fourth resistor, a fifth resistor and a second diode, the fourth resistor and the fifth resistor are connected in series, the series node of the fourth resistor and the fifth resistor is connected to the positive electrode of the second diode, the other end of the fourth resistor is connected to an external power supply, the other end of the fifth resistor is grounded, and the negative electrode of the second diode is connected to the self-locking unit.
[0013] Optionally, the shutdown signal generating unit includes an auxiliary control chip and a charge and discharge module for charging and discharging an external battery. The input pin of the auxiliary control chip is connected to the charge and discharge module to receive a failure signal of the charge and discharge module. The output pin of the auxiliary control chip is connected to the gate of the first NMOS tube to output a shutdown level signal.
[0014] Optionally, the level self-locking protection circuit also includes a second capacitor and a third capacitor, the second capacitor and the third capacitor are connected in series, the series node of the second capacitor and the third capacitor is connected to the ground terminal of the external battery, the other end of the second capacitor is connected to the other end of the first capacitor, and the other end of the third capacitor is connected to the ground terminal of the auxiliary control chip.
[0015] The utility model also discloses a mobile power supply, comprising a battery and the level self-locking protection circuit as described above, wherein the battery is connected to a power-on self-excitation unit and a switch unit of the level self-locking protection circuit.
[0016] Compared with the prior art, the beneficial effects of the level self-locking protection circuit and mobile power supply provided by the embodiments of the present invention are: by setting a power-on self-excitation unit, a switch unit, a self-locking unit, a control chip and a shutdown signal generating unit, the switch unit is set between the external battery and the power input end of the control chip, the self-locking unit is connected to the control end of the switch unit, and the self-locking unit turns on or off the switch unit based on the level signal and the shutdown level signal output by the power-on self-excitation unit, thereby realizing the connection or disconnection of the power supply of the control chip and improving the practicality of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments, in which:
[0018] Figure 1 This is a structural block diagram of a level self-locking protection circuit provided in Example 1 of the present utility model;
[0019] Figure 2 This is a circuit diagram of a level self-locking protection circuit provided in Example 1 of the present utility model;
[0020] Figure 3 This is a structural block diagram of a level self-locking protection circuit provided in the second embodiment of the present utility model;
[0021] Figure 4 This is a circuit diagram of a level self-locking protection circuit provided in Example 2 of the present utility model.
[0022] The reference numerals in the figures are:
[0023] 10. Power-on self-excitation unit; 20. Switch unit; 30. Self-locking unit; 31. High-level holding module; 40 / U1. Control chip; 50. Shutdown signal generating unit; 51. Charge and discharge module; 60. Secondary starting unit;
[0024] Q1, first NMOS transistor; Q2, PMOS transistor; Q3, second NMOS transistor; Q4, third NMOS transistor; Q5, fourth NMOS transistor; R1, first resistor; R2, second resistor; R3, third resistor; R4, fourth resistor; R5, fifth resistor; D1, first diode; D2, second diode; K1, button; C1, first capacitor; C2, second capacitor; C3, third capacitor; U2, auxiliary control chip. DETAILED DESCRIPTION
[0025] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. Now, in conjunction with the accompanying drawings, a detailed description of the preferred embodiments of the present utility model will be given.
[0026] Example 1
[0027] The present invention provides a level self-locking protection circuit. Figure 1 and Figure 2 As shown, the level self-locking protection circuit includes a power-on self-excitation unit 10, a switch unit 20, a self-locking unit 30, a control chip 40 / U1 and a shutdown signal generating unit 50. The power-on self-excitation unit 10 is connected to the external battery and the self-locking unit 30. The switch unit 20 is arranged between the external battery and the power input end of the control chip 40 / U1. The self-locking unit 30 is connected to the control end of the switch unit 20. The shutdown signal generating unit 50 is used to generate a shutdown level signal, wherein the self-locking unit 30 turns on or off the switch unit 20 based on the level signal output by the power-on self-excitation unit 10 and the shutdown level signal.
[0028] The present application sets a power-on self-excitation unit 10, a switch unit 20, a self-locking unit 30, a control chip 40 / U1 and a shutdown signal generating unit 50, and sets the switch unit 20 between the external battery and the power input end of the control chip 40 / U1. The self-locking unit 30 is connected to the control end of the switch unit 20. The self-locking unit 30 turns on or off the switch unit 20 based on the level signal and the shutdown level signal output by the power-on self-excitation unit 10, thereby realizing the connection or disconnection of the power supply of the control chip 40 / U1 and improving the practicality of the circuit.
[0029] refer to Figure 1 and Figure 2 In this embodiment, the self-locking unit 30 includes a first NMOS transistor Q1 and a high-level holding module 31. The gate of the first NMOS transistor Q1 is connected to the high-level holding module 31, the power-on self-excitation unit 10, and the shutdown signal generating unit 50. The source is grounded, and the drain is connected to the control end of the switch unit 20.
[0030] The first NMOS transistor Q1 turns the switch unit 20 on or off based on the shutdown level signal from the power-on self-excitation unit 10 or the shutdown signal generating unit 50. The first NMOS transistor Q1, combined with the high-level holding module 31, forms the self-locking unit 30, resulting in a simple circuit structure and fast switching speed. Specifically, after the power-on self-excitation unit 10 is first connected to an external battery, the power-on self-excitation unit 10 outputs a high-level signal to the gate of the first NMOS transistor Q1, turning the first NMOS transistor Q1 on. The high-level holding module 31 is configured to maintain the high level of the gate of the first NMOS transistor Q1 after the first NMOS transistor Q1 is turned on, causing the switch unit 20 to self-lock and remain in the open state, connecting the power supply path to the power input terminal of the control chip 40 / U1 and maintaining power supply to the control chip 40 / U1. When the gate of the first NMOS transistor Q1 receives the shutdown level signal from the shutdown signal generating unit 50, the first NMOS transistor Q1 turns off, thereby turning off the switch unit 20 and cutting off the power supply to the control chip 40 / U1.
[0031] Further, refer to Figure 1 and Figure 2 The switch unit 20 includes a PMOS transistor Q2, and the high-level maintaining module 31 includes a first resistor R1, a second resistor R2, and a first diode D1. The first resistor R1 and the second resistor R2 are connected in series, and the series node between the first resistor R1 and the second resistor R2 is connected to the gate of the first NMOS transistor Q1. The other end of the first resistor R1 is connected to the cathode of the first diode D1, and the other end of the second resistor R2 is grounded. The anode of the first diode D1 is connected to the drain of the PMOS transistor Q2 and the power input terminal of the control chip 40 / U1. The gate of the PMOS transistor Q2 is connected to the drain of the first NMOS transistor Q1, and the source of the PMOS transistor Q2 is connected to the external battery.
[0032] The first resistor R1, the second resistor R2, and the first diode D1 maintain a high level on the first NMOS transistor Q1, ensuring that the first NMOS transistor Q1 remains conductive after the circuit is first connected to an external battery. This in turn keeps the PMOS transistor Q2 conductive, ensuring continuous power supply to the control chip 40 / U1. The PMOS transistor Q2, acting as a switching device, connects or disconnects the path between the power input terminal of the control chip 40 / U1 and the external battery, thereby connecting or disconnecting the power supply to the control chip 40 / U1.
[0033] In other embodiments, the switch unit 20 may also be a PNP transistor, the base of the PNP transistor is connected to the drain of the first NMOS transistor Q1 , the emitter is connected to the external power supply, and the collector is connected to the power input terminal of the control chip 40 / U1 .
[0034] In this embodiment, the level-locking protection circuit further includes a second NMOS transistor Q3. The gate of the second NMOS transistor Q3 is connected to the shutdown signal generating unit 50 to receive the shutdown level signal. The source of the second NMOS transistor Q3 is grounded, and the drain of the second NMOS transistor Q3 is connected to the gate of the first NMOS transistor Q1. The gate of the second NMOS transistor Q3 receives the shutdown level signal and, in response to the shutdown level signal, turns on, pulling down the level at the gate of the first NMOS transistor Q1. This turns off the first NMOS transistor Q1, disconnects the PMOS transistor Q2, and cuts off the power supply to the control chip 40 / U1. The PMOS transistor Q2 then shuts off and self-locks.
[0035] Among them, compared with directly turning off the first NMOS tube Q1 through a low-level signal, the present application uses the second NMOS tube Q3 to lower the voltage of the gate of the first NMOS tube Q1, thereby turning off the PMOS tube Q2, which can ensure that the first NMOS tube Q1 can be activated and turned on again.
[0036] Specifically, refer to Figure 1 and Figure 2The shutdown signal generating unit 50 includes a button K1, one end of which is connected to the control chip 40 / U1 and the other end is grounded. The control chip 40 / U1 outputs a shutdown level signal based on the pressing signal of the button K1. By triggering the control chip 40 / U1 to output the shutdown level signal by the button K1, the power supply of the control chip 40 / U1 can be shut off with one click, causing the control chip 40 / U1 to enter a dormant state. This is suitable for applications where products using level self-locking protection circuits, such as mobile power supplies, enter transport mode (dormant state).
[0037] refer to Figure 2 In this embodiment, the power-on self-excitation unit 10 includes a third resistor R3 and a first capacitor C1. The third resistor R3 is connected in series with the first capacitor C1. The other end of the third resistor R3 is connected to an external battery, and the other end of the first capacitor C1 is connected to the gate of the first NMOS transistor Q1.
[0038] By setting the third resistor R3 and the first capacitor C1 in series, when the external battery is first connected, the third resistor R3 and the first capacitor C1 complete outputting a high-level signal to the first NMOS transistor Q1, turning on the first NMOS transistor Q1, and the circuit structure is simple.
[0039] refer to Figure 1 and Figure 2 The level self-locking protection circuit further includes a secondary startup unit 60, which is connected to the self-locking unit 30. By providing the secondary startup unit 60, when the power supply to the control chip 40 / U1 is disconnected, the external power input restarts the self-locking unit 30 through the secondary startup unit 60, thereby restoring the power supply to the control chip 40 / U1.
[0040] Specifically, refer to Figure 1 and Figure 2 The secondary starting unit 60 includes a fourth resistor R4, a fifth resistor R5, and a second diode D2. The fourth resistor R4 and the fifth resistor R5 are connected in series. The series node between the fourth resistor R4 and the fifth resistor R5 is connected to the anode of the second diode D2. The other end of the fourth resistor R4 is connected to the external power supply. The other end of the fifth resistor R5 is grounded. The cathode of the second diode D2 is connected to the self-locking unit 30.
[0041] The fourth resistor R4 and the fifth resistor R5 are connected in series, and a voltage division is performed at the series node to obtain a high-level signal. The high-level signal is transmitted to the gate of the first NMOS transistor Q1 through the third diode, activating and turning on the first NMOS transistor Q1.
[0042] refer to Figure 2 The working principle of the level self-locking protection circuit of this embodiment is as follows:
[0043] When an external battery is first connected, the third resistor R3 and the first capacitor C1 output a high level to the gate of the first NMOS transistor Q1, turning on the first NMOS transistor Q1 and thereby pulling down the level at the gate of the PMOS transistor Q2, turning on the PMOS transistor Q2. The first resistor R1, the second resistor R2, and the first diode D1 maintain the high level of the first NMOS transistor Q1, causing the PMOS transistor Q2 to self-lock and turn on, thus powering the control chip 40 / U1. The self-locking shutdown process is as follows: when the button K1 is pressed, the control chip 40 / U1 outputs a high level signal, the second NMOS transistor Q3 turns on, and the level at the gate of the first NMOS transistor Q1 is pulled down, turning off the first NMOS transistor Q1 and the PMOS transistor Q2, thereby disconnecting the power supply to the control chip 40 / U1. After the PMOS tube Q2 completes power-off self-locking, the button K1 has no function at this time, and the button K1 is self-locked; the next time it is turned on, the fourth resistor R4, the fifth resistor R5 and the second diode D2 are turned on, and the first NMOS tube Q1 obtains a high-level signal from the voltage division of the circuit connected by the fourth resistor R4 and the fifth resistor R5 to turn on again.
[0044] Example 2
[0045] The difference between this embodiment and the first embodiment is that the shutdown signal generating unit 50 is different from the first embodiment. Figure 3 and Figure 4 In this embodiment, the shutdown signal generating unit 50 includes an auxiliary control chip U2 and a charge and discharge module 51 for charging and discharging an external battery. The input pin of the auxiliary control chip U2 is connected to the charge and discharge module 51 to receive a failure signal of the charge and discharge module 51. The output pin of the auxiliary control chip U2 is connected to the gate of the first NMOS tube Q1 to output a shutdown level signal.
[0046] Auxiliary control chip U2 receives a failure signal from charge / discharge module 51 and outputs a shutdown signal based on the failure signal, disconnecting first NMOS transistor Q1 and, in turn, PMOS transistor Q2, thereby shutting off the power supply to control chip 40 / U1. In a specific implementation, the shutdown signal output by auxiliary control chip U2 is a low-level signal.
[0047] Among them, the auxiliary control chip U2 can receive the failure signal of the charging and discharging module 51 through the existing chip, and output a shutdown level signal based on the failure signal. The failure signal can be a high-level signal. The auxiliary control chip U2 outputs a shutdown level signal based on the high-level signal. The software programs it runs are all existing reproducible software programs and do not constitute the innovation of this application.
[0048] The charge and discharge module 51 may be an existing charge and discharge management integrated circuit, such as a BUCK integrated circuit or a BOOST integrated circuit, or a BUCK-BOOST integrated circuit. The specific circuit structure thereof does not constitute the innovation of the present invention.
[0049] Further, refer to Figure 3 and Figure 4 The level self-locking protection circuit also includes a second capacitor C2 and a third capacitor C3, which are connected in series. The series node of the second capacitor C2 and the third capacitor C3 is connected to the ground terminal of the external battery. The other end of the second capacitor C2 is connected to the other end of the first capacitor C1, and the other end of the third capacitor C3 is connected to the ground terminal of the auxiliary control chip U2. The ground terminal of the external battery can be referenced Figure 4 The BAT- terminal in the auxiliary control chip U2 can refer to Figure 4 The GND terminal in the
[0050] By setting the second capacitor C2 and the third capacitor C3, when external charging is connected, the auxiliary control chip U2 is initialized, and the output pin of the auxiliary control chip U2 remains in a high-impedance state. The power-on high pulse returns to the ground end through the third resistor R3, the first capacitor C1, the second capacitor C2 and the third capacitor C3 loop. The gate of the first NMOS tube Q1 is turned on after receiving a power-on high pulse in the loop, thereby lowering the level of the gate of the PMOS tube Q2, and the PMOS tube Q2 is turned on. The control chip 40 / U1 obtains power supply, completing the secondary power supply of the control chip 40 / U1.
[0051] The level self-locking protection circuit of this embodiment can also realize that the control chip 40 / U1 can control the corresponding controlled components that do not share a common ground without providing an optocoupler or an isolation communication chip or a transformer, thereby simplifying the circuit structure and reducing the circuit cost.
[0052] In this embodiment, the control chip 40 / U1 can be a charge-discharge protection chip for controlling the charging and discharging of an external battery. The control chip 40 / U1 can be provided with two output pins, and a third NMOS transistor Q4 and a fourth NMOS transistor Q5 are provided between the ground terminal of the battery and the ground terminal of the auxiliary control chip U2. The gates of the third NMOS transistor Q4 and the fourth NMOS transistor Q5 are respectively connected to the two output pins of the control chip 40 / U1. The drain of the third NMOS transistor Q4 is connected to the ground terminal of the external battery, and the source is connected to the source of the fourth NMOS transistor Q5. The drain of the fourth NMOS transistor Q5 is connected to the ground terminal of the auxiliary control chip U2. When the control chip 40 / U1 is powered off, the third NMOS transistor Q4 and the fourth NMOS transistor Q5 are disconnected, the path between the ground terminal of the external battery and the ground terminal of the auxiliary control chip U2 is disconnected, and the battery charge and discharge circuit is disconnected, thus realizing the failure protection function.
[0053] refer to Figure 4 The working principle of the level self-locking protection circuit of this embodiment is as follows:
[0054] When the external battery is connected for the first time, the third resistor R3 and the first capacitor C1 complete the output of a high level to the gate of the first NMOS tube Q1, and the first NMOS tube Q1 is turned on, thereby lowering the level of the gate of the PMOS tube Q2, and the PMOS tube Q2 is turned on; the first resistor R1, the second resistor R2 and the first diode D1 complete the high level maintenance of the first NMOS tube Q1, so that the PMOS tube Q2 is self-locked and turned on, completing the power supply of the control chip 40 / U1. The shutdown self-locking process is as follows: when the charge and discharge module 51 fails, the control chip 40 / U1 has no time to respond, the auxiliary control chip U2 receives the failure signal, and outputs a low-level signal through its own output pin, turning off the first NMOS tube Q1. After the first NMOS tube Q1 is turned off, the gate of the PMOS tube Q2 is high, and the PMOS tube Q2 is also turned off, and then the PMOS tube Q2 completes the shutdown self-locking, disconnecting the power supply of the control chip 40 / U1, and the third NMOS tube Q4 and the fourth NMOS tube Q5 are turned off, and then the battery charge and discharge circuit is disconnected, completing the failure. Protection function: When the failure of the charge and discharge module 51 is resolved, the auxiliary control chip U2 is initialized through external power access, and the output pin of the auxiliary control chip U2 remains in a high-impedance state. The power-on high pulse returns to the ground end through the third resistor R3, the first capacitor C1, the second capacitor C2 and the third capacitor C3 loop. The gate of the first NMOS tube Q1 is turned on after receiving a power-on high pulse in the loop, thereby lowering the level of the gate of the PMOS tube Q2. The PMOS tube Q2 is turned on, and the control chip 40 / U1 obtains power supply, completing the secondary power supply of the control chip 40 / U1.
[0055] Example 3
[0056] This embodiment provides a mobile power supply, which includes a battery and the level self-locking protection circuit as described in the first or second embodiment. The battery is connected to the power-on self-excitation unit 10 and the switch unit 20 of the level self-locking protection circuit.
[0057] In the embodiment of the utility model, the level self-locking protection circuit of the mobile power supply is provided with a power-on self-excitation unit 10, a switch unit 20, a self-locking unit 30, a control chip 40 / U1 and a shutdown signal generating unit 50. The switch unit 20 is arranged between the battery and the power input end of the control chip 40 / U1, and the self-locking unit 30 is connected to the control end of the switch unit 20. The self-locking unit 30 turns on or off the switch unit 20 based on the level signal and the shutdown level signal output by the power-on self-excitation unit 10, thereby realizing the connection or disconnection of the power supply of the control chip 40 / U1, thereby improving the practicality of the circuit.
[0058] It should be understood that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Those skilled in the art may modify the technical solutions described in the above embodiments, or make equivalent replacements for some of the technical features therein; and all these modifications and replacements should fall within the scope of protection of the claims attached to the present invention.
Claims
1. A level self-locking protection circuit, characterized in that: It includes a power-on self-excitation unit, a switch unit, a self-locking unit, a control chip and a shutdown signal generating unit, the power-on self-excitation unit is connected to an external battery and the self-locking unit, the switch unit is arranged between the external battery and the power input end of the control chip, the self-locking unit is connected to the control end of the switch unit, and the shutdown signal generating unit is used to generate a shutdown level signal, wherein the self-locking unit turns on or off the switch unit based on the level signal output by the power-on self-excitation unit and the shutdown level signal.
2. The level self-locking protection circuit according to claim 1, characterized in that: The self-locking unit includes a first NMOS tube and a high-level holding module. The gate of the first NMOS tube is connected to the high-level holding module, the power-on self-excitation unit, and the shutdown signal generating unit. The source is grounded and the drain is connected to the control end of the switch unit.
3. The level self-locking protection circuit according to claim 2, characterized in that: The switching unit includes a PMOS tube, and the high-level maintaining module includes a first resistor, a second resistor and a first diode. The first resistor and the second resistor are connected in series, and the series node of the first resistor and the second resistor is connected to the gate of the first NMOS tube. The other end of the first resistor is connected to the cathode of the first diode, and the other end of the second resistor is grounded. The anode of the first diode is connected to the drain of the PMOS tube and the power input terminal of the control chip, the gate of the PMOS tube is connected to the drain of the first NMOS tube, and the source of the PMOS tube is connected to an external battery.
4. The level self-locking protection circuit according to claim 3, characterized in that: The level self-locking protection circuit further includes a second NMOS transistor, the gate of which is connected to the shutdown signal generating unit to receive the shutdown level signal, the source of which is grounded, and the drain of which is connected to the gate of the first NMOS transistor.
5. The level self-locking protection circuit according to claim 4, characterized in that: The shutdown signal generating unit includes a button, one end of the button is connected to the control chip, and the other end is grounded. The control chip outputs a shutdown level signal based on a pressing signal of the button.
6. The level self-locking protection circuit according to claim 3, characterized in that: The power-on self-excitation unit includes a third resistor and a first capacitor. The third resistor is connected in series with the first capacitor. The other end of the third resistor is connected to an external battery, and the other end of the first capacitor is connected to the gate of the first NMOS tube.
7. The level self-locking protection circuit according to any one of claims 1 to 6, characterized in that: The level self-locking protection circuit further includes a secondary starting unit, and the secondary starting unit is connected to the self-locking unit.
8. The level self-locking protection circuit according to claim 7, characterized in that: The secondary starting unit includes a fourth resistor, a fifth resistor and a second diode, the fourth resistor and the fifth resistor are connected in series, the series node of the fourth resistor and the fifth resistor is connected to the positive electrode of the second diode, the other end of the fourth resistor is connected to an external power supply, the other end of the fifth resistor is grounded, and the negative electrode of the second diode is connected to the self-locking unit.
9. The level self-locking protection circuit according to claim 6, characterized in that: The shutdown signal generating unit includes an auxiliary control chip and a charge and discharge module for charging and discharging an external battery. The input pin of the auxiliary control chip is connected to the charge and discharge module to receive a failure signal of the charge and discharge module. The output pin of the auxiliary control chip is connected to the gate of the first NMOS tube to output a shutdown level signal.
10. The level self-locking protection circuit according to claim 9, characterized in that: The level self-locking protection circuit also includes a second capacitor and a third capacitor, the second capacitor and the third capacitor are connected in series, the series node of the second capacitor and the third capacitor is connected to the ground terminal of the external battery, the other end of the second capacitor is connected to the other end of the first capacitor, and the other end of the third capacitor is connected to the ground terminal of the auxiliary control chip.
11. A mobile power supply, characterized in that: The invention comprises a battery and the level self-locking protection circuit according to any one of claims 1 to 10, wherein the battery is connected to a power-on self-excitation unit and a switch unit of the level self-locking protection circuit.