Data acquisition board card based on GPIB interface
Through the data acquisition board based on the GPIB interface, combined with the GPIB interface module and the CPLD module, the problem of expensive GPIB equipment and inconvenient connection is solved, and efficient and economical real-time acquisition of high-temperature superconducting parameters is achieved.
Patent Information
- Application Number
- CN202422831736.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-19
- Publication Date
- 2025-08-19
- Estimated Expiration
- 2034-11-19
AI Technical Summary
GPIB equipment is expensive and inconvenient to connect, which affects the efficiency and economicality of real-time acquisition of high-temperature superconducting parameters.
The data acquisition board based on the GPIB interface is adopted, including the GPIB interface module, the GPIB data bus driver, the GPIB control bus driver and the GPIB controller. Combined with the CPLD module, it realizes the reading, writing, parsing and conversion of GPIB instructions, reduces the cost of software development and simplifies hardware development.
It significantly reduces the cost of software development and hardware testing, improves the flexibility and compatibility of the system, and adapts to the needs of different application scenarios.
Smart Images
Figure CN223245022U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of power electronics, in particular to a data acquisition board based on a GPIB interface. Background Art
[0002] In a high-temperature superconducting fusion device, it is usually necessary to collect high-temperature superconducting parameters in real time for real-time monitoring and acquisition, so as to facilitate the analysis and prediction of the performance of the superconducting magnet to ensure the normal operation of the entire fusion device.
[0003] In related technologies, real-time acquisition of high-temperature superconductor parameters is usually achieved through the General-Purpose Interface Bus (GPIB). The bus has high reliability, supports multi-device control, and has fast parallel communication speed, making it suitable for complex testing and control environments. It is a mature standard that is widely compatible with various test and measurement equipment and supports device addressing and priority control. Its robust physical interface and good anti-interference performance ensure the stability of signal transmission and data integrity, and is therefore widely used in laboratory automation testing, industrial control and other fields.
[0004] However, GPIB devices need to be connected to the host with the help of GPIB interface boards. These GPIB interface boards are expensive and bring inconvenience to the connection between the instrument and the host.
[0005] Therefore, there is an urgent need to propose a GPIB acquisition device to solve the technical problems in the related art that GPIB devices are expensive and inconvenient to connect. Utility Model Content
[0006] In view of this, the utility model provides a data acquisition board based on the GPIB interface to solve the technical problems in the related art that the GPIB equipment is expensive and inconvenient to connect.
[0007] The utility model provides a data acquisition board based on a GPIB interface, comprising: a GPIB interface module and a CPLD module; the GPIB interface module comprises a GPIB interface, a GPIB data bus driver, a GPIB control bus driver and a GPIB controller; one end of the GPIB interface is communicatively connected to a target device, and the other end is communicatively connected to the GPIB controller via the GPIB data bus driver and the GPIB control bus driver respectively, and is used for exchanging GPIB communication data with the target device and the GPIB controller; the other end of the GPIB controller is communicatively connected to the CPLD module, and is used for exchanging GPIB instructions with the CPLD module; the CPLD module is used for sending or receiving the GPIB instructions via the GPIB interface module, and processing the sent or received GPIB instructions, so as to read, write, parse and convert the GPIB instructions.
[0008] As an exemplary embodiment, the GPIB controller is communicatively connected to the plurality of second parallel data pins of the CPLD module via a plurality of first parallel data pins to exchange the GPIB instructions in parallel.
[0009] As an exemplary embodiment, the data acquisition board also includes a level conversion module; one end of the level conversion module is connected to the first parallel data pin through a first bidirectional data pin, and the other end is connected to the second parallel data pin through a second bidirectional data pin, and is used to convert the first level at the first parallel data pin to the second level at the second parallel interface or convert the second level at the second parallel data pin to the first level at the first parallel interface.
[0010] As an exemplary embodiment, the GPIB controller is communicatively connected to the plurality of second control pins of the CPLD module through a plurality of first control pins.
[0011] As an exemplary embodiment, the data acquisition board based on the GPIB interface also includes a voltage-stabilized power supply chip; the CPLD module is connected to the power supply pin of the level conversion module through the voltage-stabilized power supply chip to power the level conversion module through the voltage-stabilized power supply chip.
[0012] As an exemplary embodiment, the GPIB data bus driver is connected to the data signal interface line of the GPIB interface through multiple first bidirectional pins, and is connected to the third bidirectional pin of the GPIB controller through multiple second bidirectional pins for transmitting the GPIB communication data.
[0013] As an exemplary embodiment, the GPIB control bus driver is connected to the fifth bidirectional pin of the GPIB controller through multiple fourth bidirectional pins, and is connected to the management signal interface line of the GPIB interface through multiple fourth bidirectional pins to transmit management signals; the GPIB control bus driver is connected to the handshake signal interface line of the GPIB interface through multiple fifth bidirectional pins to transmit handshake signals.
[0014] The utility model provides a data acquisition board based on GPIB interface, comprising: a GPIB interface module and a CPLD module; the GPIB interface module comprises a GPIB interface, a GPIB data bus driver, a GPIB control bus driver and a GPIB controller; one end of the GPIB interface is connected to a target device for communication, and the other end is connected to the GPIB controller through the GPIB data bus driver and the GPIB control bus driver respectively, for exchanging GPIB communication data with the target device and the GPIB controller; the other end of the GPIB controller is connected to the CPLD module for communication, for exchanging GPIB instructions with the CPLD module; the CPLD module is used to send or receive GPIB instructions through the GPIB interface module The GPIB interface module connects to the existing CPLD module, avoiding the need to develop new hardware modules and reducing hardware development and testing costs. Furthermore, the CPLD module can flexibly select different signal transmission protocols based on specific needs. This flexibility allows for rapid adaptation and configuration in different application scenarios to meet various system requirements and compatibility needs. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] In order to more clearly illustrate the specific implementation methods of the utility model or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0016] Figure 1This is a modular schematic diagram of a data acquisition board based on a GPIB interface according to an embodiment of the present utility model;
[0017] Figure 2 is a schematic circuit diagram of a GPIB controller according to an embodiment of the present utility model;
[0018] Figure 3 is a schematic circuit diagram of a GPIB data bus driver according to an embodiment of the present utility model;
[0019] Figure 4 This is a schematic circuit diagram of a GPIB control bus driver according to an embodiment of the present utility model;
[0020] Figure 5 This is a schematic circuit diagram of a GPIB interface according to an embodiment of the present utility model. DETAILED DESCRIPTION
[0021] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of the present invention.
[0022] In the related art, real-time acquisition of high-temperature superconducting parameters is usually achieved through a general-purpose interface bus (GPIB). In one embodiment, the connection between the GPIB interface and the external host can be achieved through a field programmable gate array (FPGA), and the FPGA is responsible for converting the GPIB interface 110 signal into and from the general bus interface signals such as PCI / PCIe. Specifically, in one or more specific standards that specify GPIB, multiple interface functions are defined, and each interface function must be executed in accordance with a specific protocol. This implementation requires that all interface functions be implemented in the FPGA, and the corresponding software development cost is relatively high.
[0023] In another embodiment, the GPIB device is connected to the host through a specific GPIB interface card. These GPIB interface cards are expensive and bring inconvenience to the connection between the instrument and the host.
[0024] Therefore, an embodiment of the present invention provides a data acquisition board based on a GPIB interface, so as to collect high-temperature superconducting parameters based on the GPIB interface while reducing costs.
[0025] According to an embodiment of the utility model, a data acquisition board based on a GPIB interface is provided; Figure 1 FIG. 1 is a modular schematic diagram of a data acquisition board based on a GPIB interface according to an embodiment of the present invention. Figure 1 As shown, the data acquisition board includes: a GPIB interface module 100 and a CPLD module 200; the GPIB interface module 100 includes a GPIB interface 110, a GPIB data bus driver 120, a GPIB control bus driver 130 and a GPIB controller 140; one end of the GPIB interface 110 is communicatively connected to a target device, and the other end is communicatively connected to the GPIB controller 140 through the GPIB data bus driver 120 and the GPIB control bus driver 130, respectively, for exchanging GPIB communication data with the target device and the GPIB controller 140; the other end of the GPIB controller 140 is communicatively connected to the CPLD module 200, for exchanging GPIB instructions with the CPLD module 200; the CPLD module 200 is used to send or receive the GPIB instructions through the GPIB interface module 100, and process the sent or received GPIB instructions to read, write, parse and convert the GPIB instructions.
[0026] In one embodiment, the GPIB controller 140 communicates with the GPIB interface 110 through the GPIB data bus driver 120 and the GPIB control bus driver 130, receives GPIB instructions communicated by the target device connected to the GPIB interface 110, and transmits the received GPIB instructions to the CPLD module 200 through a communication connection with the CPLD module 200, thereby implementing the reading, parsing or conversion of the GPIB instructions in the CPLD module 200.
[0027] In one embodiment, the GPIB controller 140 receives GPIB instructions from the CPLD module 200 through a communication connection. The GPIB controller 140 communicates with the GPIB interface 110 through the GPIB data bus driver 120 and the GPIB control bus driver 130, and transmits the received GPIB instructions to the target device to implement the writing, parsing or conversion of the GPIB instructions in the CPLD module 200.
[0028] The above connection method, on the one hand, uses a mature dedicated GPIB control chip in the GPIB interface-based data acquisition board, which simplifies the implementation process of the communication protocol and significantly reduces software development costs. Compared with the high software development costs of FPGAs and expensive GPIB interface boards, it has a low cost advantage. On the other hand, the GPIB interface module 100 is connected to the existing CPLD module 200, avoiding the development of new hardware modules, thereby reducing hardware development and testing costs. In addition, the communication connection between the GPIB interface module 100 and the CPLD module 200 allows the CPLD module 200 to flexibly select different signal transmission protocols according to specific needs. This flexibility allows for rapid adaptation and configuration in different application scenarios to meet various system requirements and compatibility needs.
[0029] In one embodiment, the GPIB controller 140 is serially connected to the CPLD module 200. This connection method has the advantages of fewer connection lines, longer transmission distance, and lower cost.
[0030] In one embodiment, the GPIB controller 140 is connected in parallel with the CPLD module 200; specifically, as an exemplary embodiment, the GPIB controller 140 is communicatively connected with the multiple second parallel data pins of the CPLD module 200 through multiple first parallel data pins to exchange the GPIB instructions in parallel; this connection method has the advantages of fast transmission speed and high efficiency.
[0031] The operating voltage of the GPIB controller 140 is typically a first level, such as 5V, while the operating voltage of the CPLD module 200 is typically a second level, such as 3.3V. Therefore, when the GPIB controller 140 is connected to the CPLD module 200, it is necessary to convert the first level at the first parallel data pin of the GPIB controller 140 into the second level at the second parallel data pin of the CPLD module 200, or to convert the second level at the second parallel data pin into the first level at the first parallel interface.
[0032] Based on this, as an exemplary embodiment, the data acquisition board also includes a level conversion module; one end of the level conversion module is connected to the first parallel data pin through a first bidirectional data pin, and the other end is connected to the second parallel data pin through a second bidirectional data pin, and is used to convert the first level at the first parallel data pin to the second level at the second parallel interface or convert the second level at the second parallel data pin to the first level at the first parallel interface.
[0033] As an exemplary embodiment, the GPIB controller 140 is communicatively connected to the plurality of second control pins of the CPLD module 200 via a plurality of first control pins.
[0034] Taking the GPIB controller 140 as the NAT9914 controller chip and the level conversion chip as the TXS0108 eight-bit bidirectional voltage level converter, the NAT9914 controller chip high level 5V is converted to 3.3V and output to the CPLD module 200 as an example to illustrate the above technical solution; illustratively, Figure 2 FIG. 1 is a schematic circuit diagram of a GPIB controller according to an embodiment of the present invention. Figure 2 As shown, pins 16 to 22 and 24 of the NAT9914 controller core, a total of 8 bidirectional data ports, are connected to pins 12 to 18 and 20 of the TXS0108 8-bit bidirectional voltage level converter. After being converted into 3.3V high-level signals, pins 1, 3 to 9 of the TXS0108 8-bit bidirectional voltage level converter, a total of 8 bidirectional data ports, are connected to the CPLD module 200 interface; pins 9 to 15, 25 and 26 of the NAT9914 controller core, a total of 9 control interfaces, are connected to the CPLD module 200 interface, so as to exchange GPIB communication data with the CPLD module 200 through the above connection method, and process the sent or received GPIB instructions through the GPIB instruction reading, writing, parsing and conversion program.
[0035] As an exemplary embodiment, the data acquisition board based on the GPIB interface includes a voltage-stabilized power supply chip; the CPLD module 200 is connected to the power supply pin of the level conversion module through the voltage-stabilized power supply chip to provide 3.3V power to the level conversion module through the voltage-stabilized power supply chip.
[0036] In this embodiment, the voltage stabilizing chip model may be an AMS1117-3.3 linear voltage regulator. The CPLD module 200 is connected to the VCCA pin of the level conversion chip through the AMS1117-3.3 linear voltage regulator to provide 3.3V power supply for the level conversion chip.
[0037] As an exemplary embodiment, the GPIB data bus driver 120 is connected to the data signal interface line of the GPIB interface 110 through multiple first bidirectional pins, and is connected to the third bidirectional pin of the GPIB controller 140 through multiple second bidirectional pins for transmitting the GPIB communication data.
[0038] In this embodiment, the GPIB data bus driver 120 may be a SN75160 eight-channel GPIB transceiver; as an exemplary embodiment, Figure 3 is a schematic circuit diagram of a GPIB data bus driver according to an embodiment of the present utility model. Figure 5 FIG. 1 is a schematic circuit diagram of a GPIB interface according to an embodiment of the present invention, as shown in FIG. Figure 3 、 Figure 5 As shown, bidirectional pins 2 to 9 of the SN75160 eight-channel GPIB transceiver are connected to the data signal interface lines of the GPIB interface 110 (pins 1 to 4 and pins 13 to 16), and bidirectional pins 2, 3, 39 to 44 of the GPIB controller 140 are connected to bidirectional pins 12 to 19 of the data bus driver.
[0039] As an exemplary embodiment, the GPIB control bus driver 130 is connected to the fifth bidirectional pin of the GPIB controller 140 through multiple fourth bidirectional pins, and is connected to the management signal interface line of the GPIB interface 110 through multiple fourth bidirectional pins to transmit management signals; the GPIB control bus driver 130 is connected to the handshake signal interface line of the GPIB interface 110 through multiple fifth bidirectional pins to transmit handshake signals.
[0040] In this embodiment, the GPIB control bus driver 130 may be an SN75161 eight-channel GPIB transceiver; schematically, Figure 4 FIG. 1 is a schematic circuit diagram of a GPIB control bus driver according to an embodiment of the present invention. Figure 4 As shown in FIG5 , the bidirectional pins 2, 3, 7, 8, and 9 of the SN75161 eight-channel GPIB transceiver are connected to the management signal interface line of the GPIB interface 110 , and the bidirectional pins 4, 5, and 6 of the SN75161 eight-channel GPIB transceiver are connected to the handshake signal interface line of the GPIB interface 110 .
[0041] In the several embodiments provided in this application, it should be understood that the disclosed client can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is merely a logical functional division. In actual implementation, there may be other division methods, such as combining or integrating multiple units or components into another system, or ignoring or not implementing some features. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interface, indirect coupling or communication connection of units or modules, and may be electrical or other forms.
[0042] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected based on actual needs to achieve the purpose of the solution provided in this embodiment.
[0043] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.
[0044] In the above embodiments of the present application, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments.
[0045] The above is only a preferred embodiment of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.
Claims
1. A data acquisition board based on GPIB interface, characterized in that: include: GPIB interface module and CPLD module; Described GPIB interface module comprises GPIB interface, GPIB data bus driver, GPIB control bus driver and GPIB controller; One end of the GPIB interface is communicatively connected to the target device, and the other end is communicatively connected to the GPIB controller via the GPIB data bus driver and the GPIB control bus driver, respectively, for exchanging GPIB communication data with the target device and the GPIB controller; The other end of the GPIB controller is communicatively connected to the CPLD module, and is used for exchanging GPIB instructions with the CPLD module; The CPLD module is used to send or receive the GPIB instructions through the GPIB interface module, and process the sent or received GPIB instructions to read, write, parse and convert the GPIB instructions.
2. The data acquisition board based on the GPIB interface as claimed in claim 1, wherein: The GPIB controller is communicatively connected with a plurality of second parallel data pins of the CPLD module via a plurality of first parallel data pins to exchange the GPIB instructions in parallel.
3. The data acquisition board based on the GPIB interface as claimed in claim 2, wherein: The data acquisition board also includes a level conversion module; One end of the level conversion module is connected to the first parallel data pin through a first bidirectional data pin, and the other end is connected to the second parallel data pin through a second bidirectional data pin, and is used to convert the first level at the first parallel data pin into the second level at the second parallel interface or convert the second level at the second parallel data pin into the first level at the first parallel interface.
4. The data acquisition board based on the GPIB interface as claimed in claim 3, wherein: The GPIB controller is communicatively connected to the multiple second control pins of the CPLD module via multiple first control pins.
5. The data acquisition board based on the GPIB interface as claimed in claim 3, characterized in that: The data acquisition board based on the GPIB interface also includes a voltage-stabilized power supply chip; The CPLD module is connected to the power supply pin of the level conversion module via a voltage-stabilized power supply chip, so as to supply power to the level conversion module via the voltage-stabilized power supply chip.
6. The data acquisition board based on the GPIB interface as claimed in claim 1, characterized in that: The GPIB data bus driver is connected to the data signal interface line of the GPIB interface through a plurality of first bidirectional pins, and is connected to the third bidirectional pin of the GPIB controller through a plurality of second bidirectional pins, for transmitting the GPIB communication data.
7. The data acquisition board based on the GPIB interface as claimed in claim 1, characterized in that: The GPIB control bus driver is connected to the fifth bidirectional pin of the GPIB controller via a plurality of fourth bidirectional pins, and Connecting to the management signal interface line of the GPIB interface through a plurality of fourth bidirectional pins to transmit management signals; The GPIB control bus driver is connected to the handshake signal interface line of the GPIB interface through a plurality of fifth bidirectional pins to transmit the handshake signal.