AFCI upgrade architecture

Abstract

The utility model discloses an AFCI upgrading architecture. The AFCI upgrading architecture comprises a master control DSP, an ARM and an AFCI controller, the ARM is in communication connection with the master control DSP and the AFCI controller, and the ARM is suitable for directly sending an upgrade program package to the AFCI controller when the AFCI controller is upgraded. The method has the beneficial effects that compared with a traditional mode, the communication complexity of the AFCI upgrading architecture can be reduced; the communication content is limited to the upgrading information, so that the complexity of communication between systems can be reduced, potential communication errors and conflicts are reduced, the stability and reliability of the whole system are improved, and upgrading management is facilitated.

Description

Technical Field

[0001] The present application relates to the field of inverter technology, and in particular to an AFCI upgrade architecture. Background Art

[0002] Among all types of safety incidents in photovoltaic power generation, electrical fires occur most frequently and cause the greatest losses. The DC voltage in a photovoltaic system is typically as high as 600-1000V. DC arcing can easily occur due to loose connectors on photovoltaic modules, poor contact, damp wiring, and insulation cracks. Numerous case studies have shown that electrical fires are primarily caused by DC arcing. AFCIs (arc fault interrupters) can immediately identify and interrupt an arc, ensuring the safety of distributed photovoltaic systems and preventing fires caused by high arc temperatures.

[0003] The existing inverter adds an AFCI controller on the basis of the main control DSP controlling and communicating with the LCD ARM, and communicates with the LCD ARM to realize the AFCI fault detection, display and software update functions.

[0004] Figure 1 The connection architecture between the main control DSP and LCD ARM of the existing inverter is added; on this basis, an AFCI controller is added to communicate with the LCD ARM to achieve the functions of AFCI fault detection, display and software update, which is an urgently needed technical means. However, the existing technology forwards the upgrade data packet through the intermediate control module, making the communication process complicated and inefficient. Utility Model Content

[0005] One of the objectives of the present application is to provide an AFCI upgrade architecture that can address at least one of the deficiencies in the above-mentioned background technology.

[0006] In order to achieve at least one of the above-mentioned purposes, the technical solution adopted in this application is: an AFCI upgrade architecture, including a main control DSP, an ARM and an AFCI controller; the ARM is communicatively connected with the main control DSP and the AFCI controller, and the ARM is suitable for sending the upgrade program package directly to the AFCI controller when the AFCI controller is upgraded.

[0007] Preferably, the main control DSP and the AFCI controller communicate with the ARM via a communication bus at the same time; and the ARM directly sends the upgrade program package to the AFCI controller via the communication bus.

[0008] Preferably, the master control DSP communicates with the ARM via a communication bus, and the AFCI controller communicates separately with the ARM via a communication branch line, so that the ARM sends the upgrade program package directly to the AFCI controller via the communication branch line.

[0009] Preferably, the main control DSP and the ARM are connected via a first communication bus, and the main control DSP and the AFCI are also connected via a second communication bus for transmitting AFCI fault detection information.

[0010] Preferably, the communication branch lines are isolated.

[0011] Preferably, a signal connection is established between the master DSP and the ARM, and a signal connection is also established between the master DSP and the AFCI controller; the master DSP is suitable for forwarding the upgrade signal sent by the ARM to the AFCI controller, so that the AFCI controller enters the upgrade mode; the AFCI controller receives the upgrade program package sent by the ARM after entering the upgrade mode.

[0012] Preferably, there are multiple master control DSPs, at least one of which is connected to the ARM through a first upgrade signal line to receive the upgrade signal sent by the ARM, and the remaining master control DSPs are connected to the master control DSP that receives the ARM upgrade signal through a second upgrade signal line, and the AFCI controller is connected to the master control DSP that receives the ARM upgrade signal through a third upgrade signal line.

[0013] Preferably, the first upgrade signal line is isolated.

[0014] Preferably, the AFCI controller and the ARM are directly connected via a third upgrade signal line, and the ARM is suitable for sending an upgrade signal to the AFCI controller via the third upgrade signal line, so that the AFCI controller enters an upgrade mode; and the AFCI controller receives the upgrade program package sent by the ARM after entering the upgrade mode.

[0015] Preferably, the third upgrade signal line is isolated.

[0016] Compared with the prior art, the present invention has the following advantages:

[0017] Compared with traditional methods, this application can reduce the communication complexity of the AFCI upgrade architecture; by limiting the communication content to upgrade information only, it can reduce the complexity of communication between systems, reduce potential communication errors and conflicts, improve the stability and reliability of the entire system, and facilitate upgrade management. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 Schematic diagram of the connection architecture between the master control DSP and ARM in the prior art.

[0019] Figure 2 This is a schematic diagram of the connection architecture of Example 1 in this application.

[0020] Figure 3 For this application Figure 2 Timing diagram for the shown example.

[0021] Figure 4 This is a schematic diagram of omitting the I2C bus between the master DSP#1 and the master DSP# in the first embodiment of the present application.

[0022] Figure 5 This is a schematic diagram of the connection architecture of one of the examples of Example 2 in this application.

[0023] Figure 6 For this application Figure 5 Timing diagram for the shown example.

[0024] Figure 7 This is a schematic diagram of the connection architecture of another example of Example 2 in this application.

[0025] Figure 8 For this application Figure 7 Timing diagram for the shown example. DETAILED DESCRIPTION

[0026] Below, the present application is further described in conjunction with specific implementation methods. It should be noted that, in the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" and the like are intended to mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms should not be understood as necessarily referring to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0027] In the description of this application, it should be noted that for directional words, such as the terms "center", "horizontal", "longitudinal", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and so on, the directions and positional relationships indicated are based on the directions or positional relationships shown in the accompanying drawings, which are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and cannot be understood as limiting the specific scope of protection of this application.

[0028] It should be noted that the terms "first", "second", etc. in the description and claims of this application are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0029] In this application, unless otherwise expressly specified or limited, terms such as "mounted," "connected," "connect," and "fixed" should be understood broadly. For example, they may refer to connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; and internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0030] In this application, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Moreover, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0031] The terms "comprises" and "having" and any variations thereof in the specification and claims of this application are intended to cover non-exclusive inclusions. For example, a process, method, system, product or apparatus that includes a series of steps or units is not necessarily limited to those steps or units expressly listed, but may include other steps or units not expressly listed or inherent to such process, method, product or apparatus.

[0032] One of the preferred embodiments of this application is as follows: Figure 2 、 Figure 5 as well as Figure 7As shown, an AFCI upgrade architecture includes a master DSP, an ARM, and an AFCI controller. The master DSP is used for internal system control, the ARM is used for information exchange within and outside the system, and the AFCI controller is used to detect arc fault conditions. The ARM communicates with the master DSP and the AFCI controller. When the AFCI controller needs to be upgraded, the ARM can send the upgrade package directly to the AFCI controller. Compared with the traditional method of sending the upgrade package to the master DSP first and then forwarding it to the AFCI controller, it can effectively reduce the resource usage of the master DSP and reduce the burden on the master DSP. It also reduces the communication complexity of the AFCI upgrade architecture; by limiting the communication content to upgrade information, it can reduce the complexity of inter-system communication, reduce potential communication errors and conflicts, improve the stability and reliability of the entire system, and facilitate upgrade management.

[0033] It is understandable that there are many specific implementations for the ARM to send the upgrade program package directly to the AFCI controller without passing through the main control DSP. For ease of understanding, two specific embodiments will be used for detailed description below.

[0034] Example 1:

[0035] like Figure 2 and Figure 4 As shown, the master DSP and the AFCI controller communicate with the ARM through the communication bus at the same time, so that the ARM sends the upgrade program package to the AFCI controller and the master DSP through the communication bus.

[0036] It can be understood that the connection mode between the master DSP and the AFCI controller and the communication bus can be regarded as parallel, so the ARM can send separate upgrade program packages to the master DSP and the AFCI controller respectively through the communication bus.

[0037] It should be noted that when upgrading an AFCI controller, the controller must first enter upgrade mode. In upgrade mode, the controller will no longer perform control operations, meaning it is in a low-level state to ensure a stable upgrade process. Therefore, the ARM must first send an upgrade signal to the controller before sending the upgrade package. After the controller enters upgrade mode, the ARM receives the upgrade package. There are various ways for the ARM to send the upgrade signal to the AFCI controller. For ease of understanding, the following will provide a detailed explanation using two specific examples.

[0038] Example 1: Figure 2 and Figure 4As shown, the master DSP and ARM are connected via a first upgrade signal line to receive the upgrade signal sent by the ARM; the AFCI controller and the master DSP are connected via a third upgrade signal line. Thus, when the master DSP is being upgraded, the ARM can send an upgrade signal to the master DSP via the first upgrade signal line; when the AFCI controller needs to be upgraded, the ARM can send the upgrade signal to the master DSP, which is then sent to the AFCI controller via the third upgrade signal line.

[0039] Example 2: For example Figure 7 As shown, the AFCI controller and ARM are directly connected via a third upgrade signal line; when the AFCI controller needs to be upgraded, the ARM can directly send an upgrade signal to the AFCI controller via the third upgrade signal line to enable the AFCI controller to enter an upgrade mode.

[0040] It should be noted that both of the above examples can meet the needs of this application. For the above example 1, it is necessary to occupy the interface of the main control DSP when upgrading the AFCI controller; for the above example 2, if the ARM does not have a reserved interface, it may be necessary to add a new interface to connect the third upgrade signal line. Therefore, when constructing the AFCI upgrade architecture, the method for sending the upgrade signal of the AFCI controller can be selected according to actual needs; in order to facilitate the description of subsequent content, the above example 1 is preferably used for sending the upgrade signal of the AFCI controller in this embodiment.

[0041] It's important to note that the ARM is an external chip, while the main control DSP and AFCI controller are both internal chips. Therefore, in Example 1, the information exchange between the ARM and the main control DSP requires electrical isolation, that is, the first upgrade signal line needs to be isolated. Similarly, in Example 2, the third upgrade signal line also needs to be isolated.

[0042] Specifically, such as Figure 2 and Figure 4As shown, there are multiple master control DSPs, at least one of which is connected to the ARM via a first upgrade signal line to receive the upgrade signal sent by the ARM, and the remaining master control DSPs are connected to the master control DSP that receives the ARM upgrade signal via a second upgrade signal line, and the AFCI controller is connected to the master control DSP that receives the ARM upgrade signal via a third upgrade signal line. When the master control DSP directly connected to the ARM needs to be upgraded, the ARM can send an upgrade signal to the master control DSP via the first upgrade signal line; when the remaining master control DSPs need to be upgraded, the ARM can send the upgrade signal to the master control DSP directly connected to it, and then send the upgrade signal to the master control DSP to be upgraded via the second upgrade signal line; when the AFCI controller needs to be upgraded, the ARM can send the upgrade signal to the master control DSP directly connected to it, and then send the upgrade signal to the AFCI controller to be upgraded via the third upgrade signal line.

[0043] In this embodiment, Figure 2 and Figure 4 As shown, there are two pairs of communication buses, namely the first communication bus and the second communication bus; the first communication bus is used for communication connection between the main control DSP and ARM, and the main control DSP and AFCI controller can be connected through the second communication bus for transmitting AFCI fault detection information.

[0044] For easier understanding, a specific architecture will be used for detailed explanation below.

[0045] like Figure 2 As shown, the master DSP includes master DSP#1 and master DSP#2; the first communication bus is labeled communication bus SCI#1, and the second communication bus is labeled communication bus SCI#2; the first upgrade signal line includes RESET1 and Boot1, the second upgrade signal line includes RESET2 and Boot2, and the third upgrade signal line includes RESET3 and Boot3. Master DSP#1, master DSP#2, AFCI controller, and ARM are all connected to communication bus SCI#1; at the same time, master DSP#1 and AFCI controller are also connected to communication bus SCI#2. It should be noted that ARM is an external chip and needs to be electrically isolated from internal chips, so the connection between ARM and communication bus SCI#1 needs to be isolated.

[0046] Information exchange between Master DSP#1 and Master DSP#2 utilizes the I2C bus. Information exchange between the AFCI controller and Master DSP#1 utilizes a separate communication bus, SCI#2. The ARM and Master DSP#1 are connected via signal lines RESET1 and Boot1. Similarly, these signal lines require electrical isolation. Master DSP#1 and Master DSP#2 are connected via signal lines RESET2 and Boot2, and Master DSP#1 and the AFCI controller are connected via signal lines RESET3 and Boot3.

[0047] When the architecture is operating normally, information flows between the ARM and master DSP#1, between master DSP#1 and master DSP#2, and between master DSP#1 and the AFCI controller. Information exchanges between the ARM and DSP#1 occur via signal bus SCI#1, between master DSP#1 and master DSP#2 via the I2C bus, and between master DSP#1 and the AFCI controller via communication bus SCI#2. If the ARM needs to exchange information with master DSP#2, it first passes the information to master DSP#1, and then master DSP#1 and master DSP#2 exchange information. Similarly, if the ARM needs to exchange information with the AFCI controller, it first passes the information to master DSP#1, and then master DSP#1 and the AFCI controller exchange information.

[0048] When the architecture needs to be upgraded, such as Figure 3 As shown, if ARM upgrades the master DSP#1, it first controls the signal lines Boot1 and RESET1 to send a low-level upgrade signal to the master DSP#1, so that the master DSP#1 enters the upgrade mode. Then the upgrade package is sent from ARM to the master DSP#1 via the communication bus SCI#1 to complete the upgrade. Figure 3 Middle a position.

[0049] If ARM upgrades the master DSP#2, ARM first sends the upgrade instruction of the master DSP#2 to the master DSP#1 through the communication bus SCI#1, corresponding to Figure 3 After the master DSP#2 receives the upgrade instruction, the master DSP#1 can reply the instruction to ARM via the communication bus SCI#. Figure 3 Then the master DSP#1 controls the signal lines Boot2 and RESET2 to send a low-level upgrade signal to the master DSP#2, so that the master DSP#2 enters the upgrade mode. Finally, the upgrade package is sent from ARM to the master DSP#2 via the communication bus SCI#1 to complete the upgrade. Figure 3 Middle c position.

[0050] If ARM upgrades the AFCI controller, ARM first sends the upgrade instruction of the AFCI controller to the main control DSP#1 through the communication bus SCI#1, corresponding to Figure 3 After the AFCI controller receives the upgrade command, the master DSP#1 can reply to the ARM through the communication bus SCI#, corresponding to Figure 3 Then the master DSP#1 controls the signal lines Boot3 and RESET3 to send a low-level upgrade signal to the AFCI controller, causing the AFCI controller to enter the upgrade mode. Finally, the upgrade program package is sent from the ARM to the AFCI controller via the communication bus SCI#1 to complete the upgrade. Figure 3 Middle e position.

[0051] It should be noted that the information exchange between the master DSP#1 and the master DSP#2 can also be completed completely through the communication bus SCI#1, that is, the master DSP#1 and the master DSP#2 can omit the I2C bus, and the specific architecture is as follows Figure 4 shown.

[0052] Example 2:

[0053] Compared with the first embodiment, the difference of this embodiment is that: Figure 5 and Figure 7 As shown, the main control DSP communicates with the ARM through a communication bus; the AFCI controller is connected to the ARM through an independent communication branch line, so that when the AFCI controller is upgraded, the ARM can send the upgrade program package communication branch line directly to the AFCI controller.

[0054] As you can understand, the AFCI controller and ARM are connected by adding a new independent serial port. When the AFCI controller needs to be upgraded, the ARM can send the upgrade package directly to the AFCI controller, avoiding resource constraints on the main control DSP and reducing the burden on the main control DSP. Compared with traditional methods, this can reduce the communication complexity of the AFCI upgrade architecture. By limiting communication content to upgrade information, the complexity of inter-system communication can be reduced, reducing potential communication errors and conflicts, improving the stability and reliability of the entire system, and facilitating upgrade management.

[0055] It should be noted that ARM is an external chip, while the AFCI controller is an internal chip. The two need to be electrically isolated when exchanging information, that is, the communication branch line needs to be isolated.

[0056] It should be known that there are two pairs of communication buses, namely the first communication bus and the second communication bus; the first communication bus is used for the communication connection between the main control DSP and the ARM, and the main control DSP and the AFCI controller can be connected through the second communication bus for transmitting AFCI fault detection information. When upgrading the AFCI controller, the AFCI controller needs to enter the upgrade mode first. In the upgrade mode, the AFCI controller will no longer perform control work, that is, the AFCI controller is in a low-level state at this time to ensure that the upgrade process can proceed stably. Therefore, ARM needs to send an upgrade signal to the AFCI controller before sending the upgrade program package to the AFCI controller, and then receive the upgrade program package sent by ARM after the AFCI controller enters the upgrade mode. There are many specific ways for ARM to send an upgrade signal to the AFCI controller. For the sake of ease of understanding, two specific examples will be used to explain in detail below.

[0057] Example 1: Figure 5 As shown, the master DSP and ARM are connected via a first upgrade signal line to receive the upgrade signal sent by the ARM; the AFCI controller and the master DSP are connected via a third upgrade signal line. Thus, when the master DSP is being upgraded, the ARM can send an upgrade signal to the master DSP via the first upgrade signal line; when the AFCI controller needs to be upgraded, the ARM can send the upgrade signal to the master DSP, which is then sent to the AFCI controller via the third upgrade signal line.

[0058] Generally speaking, there are multiple master DSPs, at least one of which is connected to the ARM via the first upgrade signal line to receive the upgrade signal sent by the ARM, the remaining master DSPs are connected to the master DSP that receives the ARM upgrade signal via the second upgrade signal line, and the AFCI controller is connected to the master DSP that receives the ARM upgrade signal via the third upgrade signal line. When the master DSP directly connected to the ARM needs to be upgraded, the ARM can send the upgrade signal to the master DSP via the first upgrade signal line; when the remaining master DSPs need to be upgraded, the ARM can send the upgrade signal to the master DSP directly connected to it, and then send the upgrade signal to the master DSP to be upgraded via the second upgrade signal line; when the AFCI controller needs to be upgraded, the ARM can send the upgrade signal to the master DSP directly connected to it, and then send the upgrade signal to the AFCI controller to be upgraded via the third upgrade signal line.

[0059] For easier understanding, a specific architecture will be used for detailed explanation below.

[0060] like Figure 5As shown, the master DSP includes master DSP#1 and master DSP#2; the first communication bus is labeled communication bus SCI#1, and the second communication bus is labeled communication bus SCI#2; the first upgrade signal line includes RESET1 and Boot1, the second upgrade signal line includes RESET2 and Boot2, and the third upgrade signal line includes RESET3 and Boot3; the communication branch line uses the UART communication protocol. Master DSP#1, master DSP#2, AFCI controller, and ARM are all connected to communication bus SCI#1; at the same time, master DSP#1 and AFCI controller are also connected to communication bus SCI#2. It should be noted that the ARM is an external chip and needs to be electrically isolated from the internal chips, so the connection between the ARM and communication bus SCI#1 needs to be isolated.

[0061] Information exchange between Master DSP#1 and Master DSP#2 utilizes the I2C bus. The ARM communicates with the AFCI controller using a new serial port, UART5. Conventional cables can be used between the AFCI controller and the ARM. Information exchange between the AFCI controller and Master DSP#1 utilizes a separate communication bus, SCI#2. The ARM and Master DSP#1 are connected via signal lines RESET1 and Boot1. Similarly, these signal lines require electrical isolation. Master DSP#1 and Master DSP#2 are connected via signal lines RESET2 and Boot2, and Master DSP#1 is connected to the AFCI controller via signal lines RESET3 and Boot3.

[0062] When the architecture is operating normally, information flows between the ARM and master DSP#1, between the ARM and the AFCI controller, between master DSP#1 and master DSP#2, and between master DSP#1 and the AFCI controller. Information exchanges between the ARM and DSP#1 occur via signal bus SCI#1, between master DSP#1 and master DSP#2 via the I2C bus, and between master DSP#1 and the AFCI controller via communication bus SCI#2. If the ARM needs to exchange information with master DSP#2, it first passes the information to master DSP#1, which then allows for interaction between master DSP#1 and master DSP#2.

[0063] When the architecture needs to be upgraded, such as Figure 6 As shown, if ARM upgrades the master DSP#1, it first controls the signal lines Boot1 and RESET1 to send a low-level upgrade signal to the master DSP#1, so that the master DSP#1 enters the upgrade mode. Then the upgrade package is sent from ARM to the master DSP#1 via the communication bus SCI#1 to complete the upgrade. Figure 6Middle a position.

[0064] If ARM upgrades the master DSP#2, ARM first sends the upgrade instruction of the master DSP#2 to the master DSP#1 through the communication bus SCI#1, corresponding to Figure 6 After the master DSP#2 receives the upgrade instruction, the master DSP#1 can reply the instruction to ARM via the communication bus SCI#. Figure 6 Then the master DSP#1 controls the signal lines Boot2 and RESET2 to send a low-level upgrade signal to the master DSP#2, so that the master DSP#2 enters the upgrade mode. Finally, the upgrade package is sent from ARM to the master DSP#2 via the communication bus SCI#1 to complete the upgrade. Figure 6 Middle c position.

[0065] If ARM upgrades the AFCI controller, ARM first sends the upgrade instruction of the AFCI controller to the main control DSP#1 through the communication bus SCI#1, corresponding to Figure 6 After the AFCI controller receives the upgrade command, the master DSP#1 can reply to the ARM through the communication bus SCI#, corresponding to Figure 6 Then the master DSP#1 controls the signal lines Boot3 and RESET3 to send a low-level upgrade signal to the AFCI controller, causing the AFCI controller to enter the upgrade mode. Finally, the upgrade package is sent from the new serial port UART5 of the ARM to the AFCI controller to complete the upgrade. Figure 6 Middle h position.

[0066] Example 2: For example Figure 7 As shown, the AFCI controller and ARM are directly connected via a third upgrade signal line. When the AFCI controller needs to be upgraded, the ARM can directly send an upgrade signal to the AFCI controller via the third upgrade signal line, causing the AFCI controller to enter upgrade mode. It should be noted that the ARM is an external chip, while the AFCI controller is an internal chip. The two need to be electrically isolated when exchanging information, that is, the third upgrade signal line needs to be isolated.

[0067] It is understandable that in this example, the upgrade signal and the upgrade package of the AFCI controller do not need to pass through the main control DSP, but communicate directly with the ARM. For ease of understanding, the following will be explained in detail through a specific architecture.

[0068] like Figure 7As shown, the master DSP includes master DSP#1 and master DSP#2; the first communication bus is labeled communication bus SCI#1, and the second communication bus is labeled communication bus SCI#2; the first upgrade signal line includes RESET1 and Boot1, the second upgrade signal line includes RESET2 and Boot2, and the third upgrade signal line includes RESET3 and Boot3; the communication branch line uses the UART communication protocol. Master DSP#1, master DSP#2, and ARM are connected to communication bus SCI#1; meanwhile, master DSP#1 and the AFCI controller are connected to communication bus SCI#2. It should be noted that the ARM is an external chip and needs to be electrically isolated from the internal chips, so the connection between the ARM and communication bus SCI#1 needs to be isolated.

[0069] Information exchange between Master DSP#1 and Master DSP#2 utilizes the I2C bus. The ARM communicates with the AFCI controller using a new serial port, UART5. Conventional cables can be used between the AFCI controller and the ARM. Information exchange between the AFCI controller and Master DSP#1 utilizes a separate communication bus, SCI#2. The ARM and Master DSP#1 are connected via signal lines RESET1 and Boot1. Similarly, these signal lines require electrical isolation. Master DSP#1 and Master DSP#2 are connected via signal lines RESET2 and Boot2, and Master DSP#1 is connected to the AFCI controller via signal lines RESET3 and Boot3.

[0070] When the architecture is operating normally, information flows between the ARM and master DSP#1, between the ARM and the AFCI controller, between master DSP#1 and master DSP#2, and between master DSP#1 and the AFCI controller. Information exchanges between the ARM and DSP#1 occur via signal bus SCI#1. The ARM communicates with the AFCI controller DSP using a separate serial port, UART5. Information exchanges between master DSP#1 and master DSP#2 occur via the I2C bus, and between master DSP#1 and the AFCI controller via communication bus SCI#2. If the ARM needs to exchange information with master DSP#2, it first passes the information to master DSP#1, which then allows the exchange between master DSP#1 and master DSP#2.

[0071] When the architecture needs to be upgraded, such as Figure 8As shown, if ARM upgrades the master DSP#1, it first controls the signal lines Boot1 and RESET1 to send a low-level upgrade signal to the master DSP#1, so that the master DSP#1 enters the upgrade mode. Then the upgrade package is sent from ARM to the master DSP#1 via the communication bus SCI#1 to complete the upgrade. Figure 8 Middle a position.

[0072] If ARM upgrades the master DSP#2, ARM first sends the upgrade instruction of the master DSP#2 to the master DSP#1 through the communication bus SCI#1, corresponding to Figure 8 After the master DSP#2 receives the upgrade instruction, the master DSP#1 can reply the instruction to ARM via the communication bus SCI#. Figure 8 Then the master DSP#1 controls the signal lines Boot2 and RESET2 to send a low-level upgrade signal to the master DSP#2, so that the master DSP#2 enters the upgrade mode. Finally, the upgrade package is sent from ARM to the master DSP#2 via the communication bus SCI#1 to complete the upgrade. Figure 8 Middle c position.

[0073] If ARM upgrades the AFCI controller, ARM directly sends a low-level upgrade signal to the AFCI controller through the new serial port UART5 and then controls the signal lines Boot3 and RESET3, so that the AFCI controller enters the upgrade mode. Then the upgrade package is sent from the new serial port UART5 of ARM to the AFCI controller to complete the upgrade, corresponding to Figure 8 Middle h position.

[0074] The above describes the basic principles, main features, and advantages of the present application. Those skilled in the art should understand that the present application is not limited to the above-described embodiments. The above-described embodiments and the specification merely illustrate the principles of the present application. Various changes and improvements may be made to the present application without departing from the spirit and scope of the present application. These changes and improvements fall within the scope of the present application for which protection is sought. The scope of protection claimed by the present application is defined by the appended claims and their equivalents.

Claims

1. An AFCI upgrade architecture, characterized in that: It includes a main control DSP, an ARM and an AFCI controller; the ARM is in communication connection with the main control DSP and the AFCI controller; the ARM is suitable for directly sending an upgrade program package to the AFCI controller when the AFCI controller is upgraded.

2. The AFCI upgrade architecture according to claim 1, wherein: The master control DSP and the AFCI controller communicate with the ARM via a communication bus at the same time; the ARM directly sends the upgrade program package to the AFCI controller via the communication bus.

3. The AFCI upgrade architecture according to claim 1, wherein: The main control DSP communicates with the ARM via a communication bus, and the AFCI controller communicates separately with the ARM via a communication branch line, so that the ARM directly sends the upgrade program package to the AFCI controller via the communication branch line.

4. The AFCI upgrade architecture according to claim 3, wherein: The communication branch lines are isolated.

5. The AFCI upgrade architecture according to claim 2 or 3, wherein: The main control DSP and the ARM are connected via a first communication bus, and the main control DSP and the AFCI are also connected via a second communication bus for transmitting AFCI fault detection information.

6. The AFCI upgrade architecture according to any one of claims 1 to 3, wherein: A signal connection is established between the master control DSP and the ARM, and a signal connection is also established between the master control DSP and the AFCI controller; the master control DSP is suitable for forwarding the upgrade signal sent by the ARM to the AFCI controller, so that the AFCI controller enters the upgrade mode; the AFCI controller receives the upgrade program package sent by the ARM after entering the upgrade mode.

7. The AFCI upgrade architecture according to claim 6, wherein: There are multiple master control DSPs, at least one of which is connected to the ARM via a first upgrade signal line to receive an upgrade signal sent by the ARM; The remaining master control DSPs are connected to the master control DSP that receives the ARM upgrade signal via a second upgrade signal line; the AFCI controller is connected to the master control DSP that receives the ARM upgrade signal via a third upgrade signal line.

8. The AFCI upgrade architecture according to claim 7, wherein: The first upgrade signal line is isolated.

9. The AFCI upgrade architecture according to any one of claims 1 to 3, wherein: The AFCI controller and the ARM are directly connected via a third upgrade signal line, and the ARM is suitable for sending an upgrade signal to the AFCI controller via the third upgrade signal line, so that the AFCI controller enters an upgrade mode; after entering the upgrade mode, the AFCI controller receives the upgrade program package sent by the ARM.

10. The AFCI upgrade architecture according to claim 9, wherein: The third upgrade signal line is isolated.

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