USB expansion circuit
Through USB3.0 expansion circuits, chip U1 and multiple USB communication units are used to expand the USB interface without taking up space, solving the problem of interface reduction caused by the thinning of electronic products, and improving space utilization and data transmission speed.
Patent Information
- Application Number
- CN202422199247.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-06
- Publication Date
- 2025-08-19
- Estimated Expiration
- 2034-09-06
AI Technical Summary
The thinning and thinning of electronic products leads to a decrease in USB interface types, limiting the application environment.
The USB3.0 expansion circuit is adopted, including input module, expansion module and reception module. The chip U1 and multiple USB communication units are used to achieve signal expansion through capacitors, resistors and crystal oscillators to ensure that space resources are not occupied.
Without taking up space, it is compatible with multiple USB2.0 and USB3.0 interfaces, improving space utilization and providing faster data transmission speed.
Smart Images
Figure CN223245099U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of USB, in particular to a USB expansion circuit. Background Art
[0002] At present, signal interfaces generally include USB interfaces and Type-C interfaces. These two interfaces have been widely used in major electronic products.
[0003] In related technologies, the trend toward lighter and thinner electronic products will eliminate interfaces that occupy larger areas, leading to a reduction in the types of USB interfaces and further limiting the application environment of electronic products. Utility Model Content
[0004] The purpose of the utility model is to overcome the deficiencies in the prior art and provide a USB expansion circuit that can expand the USB communication interface without occupying space resources, thereby improving space utilization.
[0005] The purpose of this utility model is achieved through the following technical solutions:
[0006] In a first aspect, the present application provides a USB expansion circuit, comprising: an input module; an expansion module, comprising a chip U1, a first USB communication unit, a second USB communication unit, and a third USB communication unit, wherein the chip U1 is electrically connected to the input module, and the first USB communication unit, the second USB communication unit, and the third USB communication unit are electrically connected to the chip U1, respectively; a receiving module, comprising a first interface, a second interface, and a third interface, wherein the first interface is electrically connected to the input module and the first USB communication unit, respectively, the second interface is electrically connected to the input module and the second USB communication unit, respectively, and the third interface is electrically connected to the input module and the third USB communication unit, respectively.
[0007] The first USB communication unit includes a first pin and a second pin, and the first pin and the second pin are respectively disposed on the chip U1.
[0008] The second USB communication unit includes a third pin and a fourth pin, and the third pin and the fourth pin are respectively disposed on the chip U1.
[0009] The third USB communication unit includes a fifth pin and a sixth pin, and the fifth pin and the sixth pin are respectively disposed on the chip U1.
[0010] The receiving module further includes a fourth interface, and the fourth interface is electrically connected to the chip U1.
[0011] The expansion module also includes capacitors C5, C6, C7 and C8. The first end of the capacitor C5 is electrically connected to the chip U1, and the second end of the capacitor C5 is grounded. The first end of the capacitor C6 is electrically connected to the chip U1, and the second end of the capacitor C6 is grounded. The first end of the capacitor C7 is electrically connected to the chip U1, and the second end of the capacitor C7 is grounded. The first end of the capacitor C8 is electrically connected to the chip U1, and the second end of the capacitor C8 is grounded.
[0012] The expansion module further includes a resistor R23 and a capacitor C20. The resistor R23 is electrically connected to the chip U1. A first end of the capacitor C20 is electrically connected to the resistor R23 and the chip U1 respectively. A second end of the capacitor C20 is grounded.
[0013] The expansion module further includes a crystal oscillator Y1 , which is electrically connected to the chip U1 .
[0014] The input module includes a fifth interface, a capacitor C9, a capacitor C10, a capacitor C11 and a capacitor C12. The fifth interface is electrically connected to the chip U1. The first end of the capacitor C9 is electrically connected to the fifth interface, and the second end of the capacitor C9 is grounded. The first end of the capacitor C10 is electrically connected to the fifth interface, and the second end of the capacitor C10 is grounded. The first end of the capacitor C11 is electrically connected to the fifth interface, and the second end of the capacitor C11 is grounded. The first end of the capacitor C12 is electrically connected to the fifth interface and the chip U1 respectively, and the second end of the capacitor C12 is grounded. The fifth interface is also electrically connected to the first interface, the second interface, the third interface and the fourth interface respectively.
[0015] The receiving module also includes capacitor C1, capacitor C2, capacitor C3 and capacitor C4, the first end of the capacitor C1 is electrically connected to the fifth interface, the second end of the capacitor C1 is electrically connected to the fourth interface, the first end of the capacitor C2 is electrically connected to the fifth interface, the second end of the capacitor C2 is electrically connected to the fourth interface, the first end of the capacitor C3 is electrically connected to the fifth interface, the second end of the capacitor C3 is electrically connected to the fourth interface, the first end of the capacitor C4 is electrically connected to the fifth interface, and the second end of the capacitor C4 is electrically connected to the fourth interface.
[0016] Compared with the prior art, the present invention has at least the following advantages:
[0017] This input module utilizes USB 3.0, making it compatible with most electronic products on the market without taking up space. It ensures full-duplex data communication between the interface circuit and the signal, providing faster data transfer speeds and backward compatibility with USB 2.0 devices. This allows a single input module to expand multiple USB 2.0 and USB 3.0 interfaces, improving space utilization. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the following briefly introduces the drawings required for use in the embodiments.
[0019] Figure 1 This is a functional module diagram of a USB expansion circuit in one embodiment of the present utility model;
[0020] Figure 2 This is a circuit diagram of an expansion module in one embodiment of the present utility model;
[0021] Figure 3 is a circuit diagram of an input module in one embodiment of the present utility model;
[0022] Figure 4 FIG. 1 is a circuit diagram of a receiving module in an embodiment of the present invention. DETAILED DESCRIPTION
[0023] The following describes embodiments of the present application in more detail with reference to the accompanying drawings. Although the accompanying drawings illustrate embodiments of the present application, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments described herein. Rather, these embodiments are provided to make the present application more thorough and complete, and to fully convey the scope of the present application to those skilled in the art.
[0024] It should be understood that although the terms "first", "second", "third", etc. may be used in this application to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.
[0025] Unless otherwise expressly specified or limited, the terms "mounted," "connected," "connect," "fixed," and the like should be interpreted broadly. For example, they may refer to fixed connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; and internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.
[0026] Currently, signal interfaces generally include USB and Type-C interfaces, both of which are already widely used in various electronic products. However, the trend towards thinner and lighter electronic products will eliminate interfaces that occupy larger areas, leading to a decrease in the number of USB interface types, which in turn further limits the application environments of electronic products.
[0027] In response to the above problems, an embodiment of the present application provides a USB expansion circuit that can expand the USB communication interface without occupying space resources, thereby improving space utilization.
[0028] The technical solutions of the embodiments of the present application are described in detail below with reference to the accompanying drawings.
[0029] See also Figure 1 A USB expansion circuit includes: an input module 100, an expansion module 200 and a receiving module 300. The expansion module 200 includes a chip U1, a first USB communication unit, a second USB communication unit and a third USB communication unit. The chip U1 is electrically connected to the input module 100, and the first USB communication unit, the second USB communication unit and the third USB communication unit are electrically connected to the chip U1 respectively; the receiving module 300 includes a first interface, a second interface and a third interface. The first interface is electrically connected to the input module 100 and the first USB communication unit respectively, the second interface is electrically connected to the input module 100 and the second USB communication unit respectively, and the third interface is electrically connected to the input module 100 and the third USB communication unit respectively.
[0030] It should be noted that the input module 100 is a USB3.0 interface for electronic products, and the chip U1 uses the model SL2.1S, which is a high-speed, low-power, high-performance USB2.0 hub master integrated chip. The first interface, the second interface, and the third interface are USB1, USB2, and USB3, respectively. The input module 100 of this application adopts USB3.0, and is compatible with most electronic products on the market without occupying space resources, ensuring full-duplex data communication between the interface circuit and the signal, providing faster data transmission speed, and is backward compatible with the use of USB2.0 devices. As a result, one input module 100 can expand multiple USB2.0 and USB3.0 interfaces, thereby improving space utilization.
[0031] See also Figure 3 Specifically, the first USB communication unit includes a first pin and a second pin, and the first pin and the second pin are respectively provided on the chip U1. Specifically, the second USB communication unit includes a third pin and a fourth pin, and the third pin and the fourth pin are respectively provided on the chip U1. The third USB communication unit includes a fifth pin and a sixth pin, and the fifth pin and the sixth pin are respectively provided on the chip U1.
[0032] It should be noted that the first pin is DP1, the second pin is DM1, the third pin is DP2, the fourth pin is DM2, the fifth pin is DP3, and the sixth pin is DM3.
[0033] See also Figure 3 In one embodiment, the receiving module 300 further includes a fourth interface, and the fourth interface is electrically connected to the chip U1.
[0034] It should be noted that the fourth interface is USB3.0 A2, and the fourth interface is used to electrically connect the signal of the input module 100. The direct signal connection does not occupy the interface of the electronic product, and plays the function of expanding the signal interface.
[0035] See also Figure 3 In one embodiment, the expansion module 200 further includes a capacitor C5, a capacitor C6, a capacitor C7, and a capacitor C8. The first end of the capacitor C5 is electrically connected to the chip U1, and the second end of the capacitor C5 is grounded. The first end of the capacitor C6 is electrically connected to the chip U1, and the second end of the capacitor C6 is grounded. The first end of the capacitor C7 is electrically connected to the chip U1, and the second end of the capacitor C7 is grounded. The first end of the capacitor C8 is electrically connected to the chip U1, and the second end of the capacitor C8 is grounded.
[0036] It should be noted that capacitor C5 , capacitor C6 , capacitor C7 and capacitor C8 are all filter capacitors.
[0037] See also Figure 3In one embodiment, the expansion module 200 further includes a resistor R23 and a capacitor C20, the resistor R23 is electrically connected to the chip U1, a first end of the capacitor C20 is electrically connected to the resistor R23 and the chip U1 respectively, and a second end of the capacitor C20 is grounded.
[0038] It should be noted that the resistor R23 and the capacitor C20 play the role of resistance-capacitance voltage reduction.
[0039] See also Figure 3 In one embodiment, the expansion module 200 further includes a crystal oscillator Y1 , which is electrically connected to the chip U1 .
[0040] It should be noted that the crystal oscillator Y1 is used to provide a crystal oscillation signal to the chip U1 so that the circuit can operate normally.
[0041] See also Figure 2 In one embodiment, the input module 100 includes a fifth interface, a capacitor C9, a capacitor C10, a capacitor C11 and a capacitor C12. The fifth interface is electrically connected to the chip U1, the first end of the capacitor C9 is electrically connected to the fifth interface, the second end of the capacitor C9 is grounded, the first end of the capacitor C10 is electrically connected to the fifth interface, the second end of the capacitor C10 is grounded, the first end of the capacitor C11 is electrically connected to the fifth interface, the second end of the capacitor C11 is grounded, the first end of the capacitor C12 is electrically connected to the fifth interface and the chip U1 respectively, the second end of the capacitor C12 is grounded, and the fifth interface is also electrically connected to the first interface, the second interface, the third interface and the fourth interface respectively.
[0042] It should be noted that capacitors C9, C10, C11, and C12 are all filter capacitors. The fifth interface is USB3.0_A1.
[0043] See also Figure 4 In one embodiment, the receiving module 300 further includes a capacitor C1, a capacitor C2, a capacitor C3, and a capacitor C4, the first end of the capacitor C1 is electrically connected to the fifth interface, the second end of the capacitor C1 is electrically connected to the fourth interface, the first end of the capacitor C2 is electrically connected to the fifth interface, the second end of the capacitor C2 is electrically connected to the fourth interface, the first end of the capacitor C3 is electrically connected to the fifth interface, the second end of the capacitor C3 is electrically connected to the fourth interface, the first end of the capacitor C4 is electrically connected to the fifth interface, and the second end of the capacitor C4 is electrically connected to the fourth interface.
[0044] It should be noted that the capacitors C1 , C2 , C3 and C4 are all coupling capacitors.
[0045] The circuit principle of this application is explained below:
[0046] The fifth interface, USB3.0_A1, connects to chip U1, the fourth interface, USB3.0_A2, the first interface, USB1, the second interface, USB2, and the third interface, USB3. Pin 1 of the fifth interface first inputs the VBUS voltage from the electronic product's USB port into the expansion circuit. This voltage is then filtered by capacitors C9, C10, C11, and C12 to produce a stable VDD5 voltage, which is then transmitted to expansion module 200. Pin 7 of chip U1 is connected to the VDD5 power supply, using resistor R23 and capacitor C20 to reduce the voltage, providing operating voltage for chip U1. This also provides operating voltage for external devices connected to the fourth interface, USB3.0_A2, the first interface, USB1, the second interface, USB2, and the third interface, USB3, of the receiving module 300. A capacitor is added to the power supply pin to filter the voltage to ground, enhancing interference resistance.
[0047] Furthermore, the fifth interface USB3.0_A1 is divided into two groups of signal protocols: 2Pin and 3Pin are for USB2.0 serial port communication, while 5Pin, 6Pin, 8Pin and 9Pin are for USB3.0 serial port communication. The 2Pin and 3Pin of the fifth interface are connected to the 5Pin and 6Pin of the chip U1 to form a communication line of the USB2.0 interface protocol; the 5Pin, 6Pin, 8Pin and 9Pin of the fifth interface are connected to the 5Pin, 6Pin, 8Pin and 9Pin of USB3.0_A2 through capacitors C1, C2, C3 and C4 coupling capacitors. The fourth interface USB3.0_A2 is electrically connected to the signal of the fifth interface. The direct signal connection method does not occupy the resource utilization space of the interface of the electronic product itself, and serves to expand the function of the signal interface.
[0048] Furthermore, after connecting Pins 5 and 6 of chip U1 to the fifth interface to read the signal, chip U1 will split the DM and DP signal sources into four sub-signals, which are then electrically connected to the first, second, and third interfaces. Pins 9 and 10 of chip U1 are connected to capacitors C5, C6, C7, and C8 to ground. Chip U1 has an internal reference voltage, allowing the circuit to expand the signal without a voltage. Pins 11 and 12 require an external 12MHz passive crystal oscillator to provide the crystal oscillation signal within chip U1, allowing the circuit to operate normally.
[0049] The scheme of the present application has been described in detail above with reference to the accompanying drawings. In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. Those skilled in the art should also be aware that the actions and modules involved in the description are not necessarily required for this application. In addition, it is understood that the steps in the method of the embodiment of the present application can be adjusted in sequence, merged and deleted according to actual needs, and the modules in the device of the embodiment of the present application can be merged, divided and deleted according to actual needs.
[0050] The embodiments of the present application have been described above. The above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or improvements to the technology in the market, or to enable other persons skilled in the art to understand the embodiments disclosed herein.
Claims
1. A USB expansion circuit, characterized in that: include: Input module; An expansion module includes a chip U1, a first USB communication unit, a second USB communication unit, and a third USB communication unit, wherein the chip U1 is electrically connected to the input module, and the first USB communication unit, the second USB communication unit, and the third USB communication unit are respectively disposed on the chip U1; The receiving module includes a first interface, a second interface and a third interface, wherein the first interface is electrically connected to the input module and the first USB communication unit respectively, the second interface is electrically connected to the input module and the second USB communication unit respectively, and the third interface is electrically connected to the input module and the third USB communication unit respectively.
2. The USB expansion circuit according to claim 1, wherein: The first USB communication unit includes a first pin and a second pin, and the first pin and the second pin are respectively disposed on the chip U1.
3. The USB expansion circuit according to claim 1, wherein: The second USB communication unit includes a third pin and a fourth pin, and the third pin and the fourth pin are respectively disposed on the chip U1.
4. The USB expansion circuit according to claim 1, wherein: The third USB communication unit includes a fifth pin and a sixth pin, and the fifth pin and the sixth pin are respectively disposed on the chip U1.
5. The USB expansion circuit according to claim 1, wherein: The receiving module further includes a fourth interface, and the fourth interface is electrically connected to the chip U1.
6. The USB expansion circuit according to claim 1, wherein: The expansion module also includes capacitors C5, C6, C7 and C8. The first end of the capacitor C5 is electrically connected to the chip U1, and the second end of the capacitor C5 is grounded. The first end of the capacitor C6 is electrically connected to the chip U1, and the second end of the capacitor C6 is grounded. The first end of the capacitor C7 is electrically connected to the chip U1, and the second end of the capacitor C7 is grounded. The first end of the capacitor C8 is electrically connected to the chip U1, and the second end of the capacitor C8 is grounded.
7. The USB expansion circuit according to claim 1, wherein: The expansion module further includes a resistor R23 and a capacitor C20. The resistor R23 is electrically connected to the chip U1. A first end of the capacitor C20 is electrically connected to the resistor R23 and the chip U1 respectively. A second end of the capacitor C20 is grounded.
8. The USB expansion circuit according to claim 1, wherein: The expansion module further includes a crystal oscillator Y1 , which is electrically connected to the chip U1 .
9. The USB expansion circuit according to claim 5, characterized in that: The input module includes a fifth interface, a capacitor C9, a capacitor C10, a capacitor C11 and a capacitor C12. The fifth interface is electrically connected to the chip U1. The first end of the capacitor C9 is electrically connected to the fifth interface, and the second end of the capacitor C9 is grounded. The first end of the capacitor C10 is electrically connected to the fifth interface, and the second end of the capacitor C10 is grounded. The first end of the capacitor C11 is electrically connected to the fifth interface, and the second end of the capacitor C11 is grounded. The first end of the capacitor C12 is electrically connected to the fifth interface and the chip U1 respectively, and the second end of the capacitor C12 is grounded. The fifth interface is also electrically connected to the first interface, the second interface, the third interface and the fourth interface respectively.
10. The USB expansion circuit according to claim 9, characterized in that: The receiving module also includes capacitor C1, capacitor C2, capacitor C3 and capacitor C4, the first end of the capacitor C1 is electrically connected to the fifth interface, the second end of the capacitor C1 is electrically connected to the fourth interface, the first end of the capacitor C2 is electrically connected to the fifth interface, the second end of the capacitor C2 is electrically connected to the fourth interface, the first end of the capacitor C3 is electrically connected to the fifth interface, the second end of the capacitor C3 is electrically connected to the fourth interface, the first end of the capacitor C4 is electrically connected to the fifth interface, and the second end of the capacitor C4 is electrically connected to the fourth interface.