Pixel circuit, flat panel display device and information processing device

Abstract

The utility model discloses a pixel circuit, which is used for forming a pixel unit with a light-emitting component and comprises a data driving unit, a first switch unit, a second switch unit, a capacitor and a third switch unit, and the data driving unit is coupled with the capacitor, the first switch unit and the second switch unit. According to the utility model, the third switch unit is coupled among the capacitor, the data driving unit and the first switch unit, so as to prevent the node voltage between the data driving unit and the capacitor from dropping when the first switch unit is turned off.

Description

Technical Field

[0001] The utility model belongs to the technical field of self-luminous flat panel display equipment, and in particular relates to a pixel circuit in which a self-luminous component constitutes a pixel unit. Background Art

[0002] As is known, flat panel displays include non-self-luminous flat panel displays and self-luminous flat panel displays. Liquid crystal displays are a type of non-self-luminous flat panel display that has been used for a long time, while organic light-emitting diode (OLED) displays and light-emitting diode (LED) displays are self-luminous flat panel displays that are currently in mainstream applications.

[0003] Figure 1 FIG. 1 is a block diagram of a known OLED display. Figure 1 As shown, the structure of the OLED display 1a mainly includes: an OLED display panel 11a and a display driver chip 12a, wherein the OLED display panel 11a includes M×N OLED pixel units, M and N are both positive integers, and each of the OLED pixel units is composed of a pixel circuit 111a and an OLED component 112a.

[0004] In recent years, Indium Gallium Zinc Oxide (IGZO) Thin Film Transistor (TFT) and Low Temperature Polysilicon (LTPS) Thin Film Transistor (TFT) have been widely used to form the pixel circuit 111a. In more detail, LTPS TFT components have high carrier mobility (~100cm 2 While this technology offers advantages such as high stability and low power consumption (Vs / Vs), it is limited to small and medium-sized OLED display panels 11a due to its high manufacturing costs. Currently, low power consumption is paramount for mobile electronic devices such as smartphones, smartwatches, and tablet computers. Conventional technology can effectively reduce the power consumption of OLED displays 1a by operating at low frame rates. However, LTPS TFT devices typically have a high cutoff current, limiting the frame rate of OLED displays 1a that include pixel circuits 111a using LTPS TFT devices.

[0005] On the other hand, IGZO TFT components have good uniformity and good mobility (10-50cm 2 / Vs), making it suitable for large-scale OLED display panels 11a. Although the stability and mobility of IGZO TFT components are not high enough, they still have unique component characteristics, namely, very low off-state current. Therefore, a new thin-film transistor that combines the advantages of LTPS TFT and IGZO TFT has been proposed and named Low Temperature Polycrystalline Oxide (LTPO) thin-film transistor.

[0006] Figure 2 Figure 1 is a topological diagram of a pixel circuit composed of LTPS TFT components and LTPO TFT components. Figure 2 As shown, the pixel circuit 111a includes a first TFT element T1a, a second TFT element T2a, a third TFT element T3a, a fourth TFT element T4a, a fifth TFT element T5a, a sixth TFT element T6a, a seventh TFT element T7a, and a capacitor Csa. The first TFT element T1a and the second TFT element T2a are both N-type LTPO thin-film transistors, while the third TFT element T3a, the fourth TFT element T4a, the fifth TFT element T5a, the sixth TFT element T6a, and the seventh TFT element T7a are P-type LTPS thin-film transistors. This pixel circuit 111a can operate normally in a low frequency range (1-30 Hz), significantly reducing the display refresh rate, thereby reducing the power consumption of the OLED display panel 11a.

[0007] Figure 3 for Figure 2 The working timing diagram of multiple control signals shown in FIG. Figure 2 and Figure 3 As shown, during the data writing phase, the first scan signal Scan-P (or gate control signal) is flipped from a high level to a low level, and the second scan signal Scan-N is flipped from a low level to a high level, so that the display data is written into the node N1. After the data writing phase ends, the first scan signal Scan-P is flipped from a low level to a high level, and the second scan signal Scan-N is flipped from a high level to a low level. At this time, Figure 2 As particularly indicated by the dotted box, due to the influence of the second TFT element T2a being turned off, the node voltage of N1 will be pulled down.

[0008] In order to compensate for the pull-down of the node voltage of N1, as shown in Figure 4As shown, the prior art solution adds a compensation voltage ΔV to the high-level voltage of the display data Data. Thus, at the end of the data writing phase, the voltage at node N1 increases from the uncompensated voltage V1 to V2, where V2 - V1 = ΔV. It is worth noting that while the prior art solution can compensate for the drop in node N1 voltage, adding a compensation voltage to the high-level voltage of the display data Data also increases power consumption.

[0009] From the above description, it can be seen that a new pixel circuit is urgently needed in the art. Utility Model Content

[0010] The primary objective of the present invention is to provide a pixel circuit for forming a pixel unit with a light-emitting component, comprising: a data driver unit, a first switch unit, a second switch unit, a capacitor, and a third switch unit, wherein the data driver unit is coupled to the capacitor, the first switch unit, and the second switch unit. Furthermore, the present invention couples the third switch unit between the capacitor, the data driver unit, and the first switch unit to prevent a voltage drop at the node between the data driver unit and the capacitor when the first switch unit is turned off.

[0011] According to a first aspect of the present invention, a pixel circuit is provided, characterized in that it includes a data driving unit having a first terminal, a first control terminal, a second control terminal, a second terminal, a third control terminal, a third terminal, a fourth control terminal, a fourth terminal, and a fifth control terminal, wherein the first terminal is coupled to a first driving voltage, the first control terminal and the third control terminal are both coupled to a light-emitting control signal, the second control terminal is coupled to a first scan signal, the second terminal DT2 is coupled to a display data signal, the fourth control terminal is coupled to a second scan signal, and the third terminal is coupled to a light-emitting component;

[0012] a first switch unit having a control terminal, a first terminal, and a second terminal, wherein the control terminal is coupled to the first scan signal, the first terminal is coupled to an initialization voltage, and the second terminal is coupled to the third terminal of the data driving unit;

[0013] a second switch unit having a control terminal, a first terminal, and a second terminal, wherein the control terminal is coupled to a reset signal, the first terminal is coupled to the initialization voltage, and the second terminal is coupled to the fourth terminal of the data driving unit;

[0014] a capacitor having a first terminal and a second terminal, wherein the first terminal is coupled to the first terminal of the data driving unit, and the second terminal is coupled to the fifth control terminal of the data driving unit; and

[0015] A third switch unit has a control end, a first end, and a second end, wherein the control end is coupled to the first scan signal, the first end is simultaneously coupled to the fifth control end of the data driving unit and the second end of the capacitor, and the second end is coupled to the fourth end of the data driving unit and the second end of the second switch unit.

[0016] In a possible implementation, the second switch unit includes a first TFT component having a gate terminal, a first electrical terminal, and a second electrical terminal serving as the control terminal, the first terminal, and the second terminal of the second switch unit, respectively.

[0017] In a possible implementation, the data driving unit includes:

[0018] a second TFT element having a gate terminal, a first electrical terminal, and a second electrical terminal, wherein the gate terminal and the first electrical terminal serve as a fourth control terminal and a fourth terminal of the data driving unit, respectively;

[0019] a third TFT element having a gate terminal, a first electrical terminal, and a second electrical terminal, wherein the gate terminal serves as the fifth control terminal of the data driving unit, and the first electrical terminal is coupled to the second electrical terminal of the second TFT element;

[0020] a fourth TFT element having a gate terminal, a first electrical terminal, and a second electrical terminal, wherein the gate terminal and the first electrical terminal serve as the second control terminal and the second terminal of the data driving unit, respectively, and the second electrical terminal is coupled to the second electrical terminal of the third TFT element;

[0021] a fifth TFT element having a gate terminal, a first electrical terminal, and a second electrical terminal, wherein the gate terminal and the first electrical terminal serve as the first control terminal and the first terminal of the data driving unit, respectively, and the second electrical terminal is coupled to the second electrical terminal of the third TFT element; and

[0022] A sixth TFT component has a gate terminal, a first electrical terminal and a second electrical terminal, wherein the gate terminal and the first electrical terminal serve as the third control terminal and the third terminal of the data driving unit respectively, and the second electrical terminal is coupled to the second electrical terminal of the second TFT component.

[0023] In one possible embodiment, the first switch unit includes a seventh TFT component whose gate terminal, a first electrical terminal and a second electrical terminal serve as the control terminal, the first terminal and the second terminal of the first switch unit respectively, and the third switch unit includes an eighth TFT component whose gate terminal, a first electrical terminal and a second electrical terminal serve as the control terminal, the first terminal and the second terminal of the third switch unit respectively.

[0024] According to another aspect of the present invention, a flat panel display device is provided, comprising a display driver circuit and a flat panel display panel, wherein the flat panel display panel comprises M×N pixel units, where M and N are both positive integers, and each pixel unit comprises a pixel circuit and a light-emitting component; wherein the pixel circuit comprises:

[0025] a data driving unit having a first terminal, a first control terminal, a second control terminal, a second terminal, a third control terminal, a third terminal, a fourth control terminal, a fourth terminal, and a fifth control terminal, wherein the first terminal is coupled to a first driving voltage, the first control terminal and the third control terminal are both coupled to a light-emitting control signal, the second control terminal is coupled to a first scan signal, the second terminal DT2 is coupled to a display data signal, the fourth control terminal is coupled to a second scan signal, and the third terminal is coupled to a light-emitting component;

[0026] a first switch unit having a control terminal, a first terminal, and a second terminal, wherein the control terminal is coupled to the first scan signal, the first terminal is coupled to an initialization voltage, and the second terminal is coupled to the third terminal of the data driving unit;

[0027] a second switch unit having a control terminal, a first terminal, and a second terminal, wherein the control terminal is coupled to a reset signal, the first terminal is coupled to the initialization voltage, and the second terminal is coupled to the fourth terminal of the data driving unit;

[0028] a capacitor having a first terminal and a second terminal, wherein the first terminal is coupled to the first terminal of the data driving unit, and the second terminal is coupled to the fifth control terminal of the data driving unit; and

[0029] A third switch unit has a control end, a first end, and a second end, wherein the control end is coupled to the first scan signal, the first end is simultaneously coupled to the fifth control end of the data driving unit and the second end of the capacitor, and the second end is coupled to the fourth end of the data driving unit and the second end of the second switch unit.

[0030] In a possible implementation, the flat display panel includes one of an organic light-emitting diode (OLED) display panel and a micro light-emitting diode (Mirco-LED) display panel.

[0031] In a possible implementation, the second switch unit includes a first TFT component having a gate terminal, a first electrical terminal, and a second electrical terminal serving as the control terminal, the first terminal, and the second terminal of the second switch unit, respectively.

[0032] In a possible implementation, the data driving unit includes:

[0033] a second TFT element having a gate terminal, a first electrical terminal, and a second electrical terminal, wherein the gate terminal and the first electrical terminal serve as a fourth control terminal and a fourth terminal of the data driving unit, respectively;

[0034] a third TFT element having a gate terminal, a first electrical terminal, and a second electrical terminal, wherein the gate terminal serves as the fifth control terminal of the data driving unit, and the first electrical terminal is coupled to the second electrical terminal of the second TFT element;

[0035] a fourth TFT element having a gate terminal, a first electrical terminal, and a second electrical terminal, wherein the gate terminal and the first electrical terminal serve as the second control terminal and the second terminal of the data driving unit, respectively, and the second electrical terminal is coupled to the second electrical terminal of the third TFT element;

[0036] a fifth TFT element having a gate terminal, a first electrical terminal, and a second electrical terminal, wherein the gate terminal and the first electrical terminal serve as the first control terminal and the first terminal of the data driving unit, respectively, and the second electrical terminal is coupled to the second electrical terminal of the third TFT element; and

[0037] A sixth TFT component has a gate terminal, a first electrical terminal and a second electrical terminal, wherein the gate terminal and the first electrical terminal serve as the third control terminal and the third terminal of the data driving unit respectively, and the second electrical terminal is coupled to the second electrical terminal of the second TFT component.

[0038] In one possible embodiment, the first switch unit includes a seventh TFT component whose gate terminal, a first electrical terminal and a second electrical terminal serve as the control terminal, the first terminal and the second terminal of the first switch unit respectively, and the third switch unit includes an eighth TFT component whose gate terminal, a first electrical terminal and a second electrical terminal serve as the control terminal, the first terminal and the second terminal of the third switch unit respectively.

[0039] According to another aspect of the present invention, an information processing device is provided, comprising the flat-panel display device of the present invention. In one possible embodiment, the information processing device is an electronic device selected from the group consisting of a smartphone, a smartwatch, a smart bracelet, a tablet computer, a laptop computer, an all-in-one computer, an access control device, and an electronic door lock. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 is a block diagram of a known OLED display;

[0041] Figure 2 The topology diagram of a pixel circuit composed of LTPS TFT components and LTPO TFT components;

[0042] Figure 3 for Figure 2 The working timing diagram of multiple control signals shown;

[0043] Figure 4 The working timing diagram showing data and node voltage of N1;

[0044] Figure 5 A block diagram of a flat panel display including a pixel circuit of the present invention;

[0045] Figure 6 A circuit topology diagram of a pixel circuit of the present invention; and

[0046] Figure 7 for Figure 6 The working timing diagram of multiple control signals is shown.

[0047] Figure symbols: 111: pixel circuit; 112: light-emitting component; I2: display driver chip; DD: data driver unit; DT1: first terminal; DT2: second terminal; DT3: third terminal; DT4: fourth terminal; DC1: first control terminal; DC2: second control terminal; DC3: third control terminal; DC4: fourth control terminal; DC5: fifth control terminal; S1: first switch unit; S1C: control terminal; S11: first terminal; S12: second terminal; S2: second switch unit; S2C: control terminal; S21: first terminal; S22: second terminal; S3: third switch unit; S3C: control terminal; S31: first terminal; S32: second terminal; T1: first T FT component; T2: second TFT component; T3: third TFT component; T4: fourth TFT component; T5: fifth TFT component; T6: sixth TFT component; T7: seventh TFT component; Cs: capacitor; 1a: OLED display; 11a: OLED display panel; 111a: pixel circuit; 112a: OLED element; 12a: display driver chip; T1a: first TFT element; T2a: second TFT element; T3a: third TFT element; T4a: fourth TFT element; T5a: fifth TFT element; T6a: sixth TFT element; T7a: seventh TFT element; Csa: capacitor; 1: flat panel display device. DETAILED DESCRIPTION

[0048] Figure 5 FIG. 1 is a block diagram of a flat panel display including a pixel circuit of the present invention. Figure 5As shown, the flat panel display 1 can be an OLED display or a Micro-LED display, and its structure mainly includes: a flat panel display panel 11 and a display driver chip 12, wherein the flat panel display panel 11 includes M×N pixel units, M and N are both positive integers, and each of the pixel units is composed of a light-emitting component 112 and a pixel circuit 111 disclosed in the present invention.

[0049] Figure 6 This is a circuit topology diagram of a pixel circuit of the present invention. Figure 6 As shown, the pixel circuit 111 of the present invention includes: a data driving unit DD, a first switch unit S1, a second switch unit S2, a capacitor Cs, and a third switch unit S3, wherein the data driving unit DD is coupled to the capacitor Cs, the first switch unit S1, and the second switch unit S2. In particular, the present invention couples the third switch unit S3 between the capacitor Cs, the data driving unit DD, and the first switch unit S1 to prevent the voltage of the node N1 between the data driving unit DD and the capacitor Cs from dropping when the first switch unit S1 is turned off.

[0050] like Figure 6 As shown, the data driving unit DD has a first terminal DT1, a first control terminal DC1, a second control terminal DC2, a second terminal DT2, a third control terminal DC3, a third terminal DT3, a fourth control terminal DC4, a fourth terminal DT4, and a fifth control terminal DC5, wherein the first terminal DT1 is coupled to a first driving voltage ELVDD, the first control terminal DC1 and the third control terminal DC3 are both coupled to a light-emitting control signal EM, the second control terminal DC2 is coupled to a first scan signal Scan-P, the second terminal DT2 is coupled to a display data signal Data, the fourth control terminal DC4 is coupled to a second scan signal Scan-N, and the third terminal DT3 is coupled to a light-emitting component 112 driven by a second driving voltage ELVSS.

[0051] On the other hand, the first switch unit S1 has a control terminal S1C, a first terminal S11, and a second terminal S12, wherein the control terminal S1C is coupled to the first scan signal Scan-P, the first terminal S11 is coupled to an initialization voltage Vint, and the second terminal S12 is coupled to the third terminal DT3 of the data driver unit DD. Furthermore, the second switch unit S2 has a control terminal S2C, a first terminal S21, and a second terminal S22, wherein the control terminal S2C is coupled to a reset signal Reset-N, the first terminal S21 is coupled to the initialization voltage Vint, and the second terminal S12 is coupled to the fourth terminal DT4 of the data driver unit DD. Figure 6As shown, the capacitor Cs has a first terminal and a second terminal, wherein the first terminal is coupled to the first terminal DT1 of the data driving unit DD, and the second terminal is coupled to the fifth control terminal DC5 of the data driving unit DD. Furthermore, the third switch unit S3 has a control terminal S3C, a first terminal S31, and a second terminal S32, wherein the control terminal S2C is coupled to the first scan signal Scan-P, the first terminal S21 is coupled to the fifth control terminal DC5 of the data driving unit DD and the second terminal of the capacitor Cs, and the second terminal S32 is coupled to the fourth terminal DT4 coupled to the data driving unit DD and the second terminal S22 of the second switch unit S2.

[0052] In one embodiment, the pixel circuit 111 of the present invention adopts an 8T1C architecture. Figure 6 As shown, the second switch unit S2 includes a first TFT element T1 having a gate terminal, a first electrical terminal, and a second electrical terminal, which respectively serve as the control terminal S2C, the first terminal S21, and the second terminal S22 of the second switch unit S2. More specifically, the data driver unit DD includes a second TFT element T2, a third TFT element T3, a fourth TFT element T4, a fifth TFT element T5, and a sixth TFT element T6. The second TFT element T2 has a gate terminal, a first electrical terminal, and a second electrical terminal, and the gate terminal and the first electrical terminal serve as the fourth control terminal DC4 and the fourth terminal DT4 of the data driver unit DD, respectively. The third TFT element T3 has a gate terminal, a first electrical terminal, and a second electrical terminal, and the gate terminal serves as the fifth control terminal DC4 of the data driver unit DD. The first electrical terminal is coupled to the second electrical terminal of the second TFT element T2.

[0053] Based on the above description, in the circuit topology of the data driver unit DD, the fourth TFT element T4 has a gate terminal, a first electrical terminal, and a second electrical terminal. The gate terminal and the first electrical terminal serve as the second control terminal DC2 and the second terminal DT2 of the data driver unit DD, respectively, and the second electrical terminal is coupled to the second electrical terminal of the third TFT element T3. Furthermore, the fifth TFT element T5 has a gate terminal, a first electrical terminal, and a second electrical terminal. The gate terminal and the first electrical terminal serve as the first control terminal DC1 and the first terminal DT1 of the data driver unit DD, respectively, and the second electrical terminal is coupled to the second electrical terminal of the third TFT element T3. Furthermore, the sixth TFT element T6 has a gate terminal, a first electrical terminal, and a second electrical terminal. The gate terminal and the first electrical terminal serve as the third control terminal DC2 and the third terminal DT3 of the data driver unit DD, respectively, and the second electrical terminal is also coupled to the second electrical terminal of the second TFT element T2.

[0054] like Figure 6 As shown, the first switch unit S1 includes a seventh TFT element T7, whose gate terminal, first electrical terminal, and second electrical terminal respectively serve as the control terminal S1C, first terminal S11, and second terminal S12 of the first switch unit S1. On the other hand, the third switch unit S3 includes an eighth TFT element T8, whose gate terminal, first electrical terminal, and second electrical terminal respectively serve as the control terminal S3C, first terminal S31, and second terminal S32 of the third switch unit S3.

[0055] It is worth noting that in Figure 6 In the circuit topology of the pixel circuit 111 of the present invention shown, the first TFT component T1 and the second TFT component T2 are both N-type LTPO thin-film transistors, while the third TFT component T3, the fourth TFT component T4, the fifth TFT component T5, the sixth TFT component T6, the seventh TFT component T7, and the eighth TFT component T8 are P-type LTPS thin-film transistors. This allows the pixel circuit 111 to operate normally in a low frequency range (1 to 30 Hz), greatly reducing the display refresh frequency, thereby reducing the power consumption of the flat display panel 11.

[0056] Figure 7 for Figure 6 The working timing diagram of multiple control signals shown in FIG. Figure 6 and Figure 7 As shown, the present invention couples the third switch unit S3 (i.e., the eighth TFT element T8) between the capacitor Cs, the third TFT element T3 and the second TFT element T2 of the data driving unit DD, and the first switch unit S1 (i.e., the first TFT element T1), to prevent the node voltage of the node N1 between the third TFT element T3 and the capacitor Cs from dropping when the second TFT element T2 is turned off. In other words, Figure 6 and Figure 7 As shown, during the data writing phase, the second scan signal Scan-N (or gate control signal) flips from a low level to a high level, and the first scan signal Scan-P flips from a high level to a low level, so that the display data is written to the node N1. After the data writing phase ends, the second scan signal Scan-N flips from a high level to a low level, and the first scan signal Scan-P flips from a low level to a high level. At this time, even if the second TFT element T2 is turned off by the second scan signal Scan-N, the node voltage at the node N1 between the third TFT element T3 and the capacitor Cs is not affected.

[0057] Thus, the above description has completely and clearly described a pixel circuit of the present invention. Furthermore, it can be seen from the above description that the present invention has the following advantages:

[0058] (1) The present invention discloses a pixel circuit, which is used to form a pixel unit with a light-emitting component, and includes: a data driving unit, a first switch unit, a second switch unit, a capacitor, and a third switch unit, wherein the data driving unit is coupled to the capacitor, the first switch unit, and the second switch unit. Furthermore, the present invention couples the third switch unit between the capacitor, the data driving unit, and the first switch unit, thereby preventing the voltage at the node between the data driving unit and the capacitor from dropping when the first switch unit is turned off.

[0059] (2) The present invention also provides a flat panel display device, which includes at least one display driving circuit and a flat panel display panel (such as an OLED panel or a Micro-LED panel), wherein the flat panel display panel includes M×N pixel units, M and N are both positive integers, and is characterized in that each of the pixel units is composed of a light-emitting component (such as an OLED component or a Micro-LED component) and a pixel circuit of the aforementioned present invention.

[0060] (3) The present invention also provides an information processing device having the flat-panel display device of the present invention as described above. Furthermore, the information processing device is an electronic device selected from the group consisting of a smart phone, a smart watch, a smart bracelet, a tablet computer, a laptop computer, an all-in-one computer, an access control device, and an electronic door lock.

[0061] While various embodiments of the present disclosure have been described above, the above descriptions are illustrative, non-exhaustive, and not intended to be limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or improvements to existing technologies, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A pixel circuit, characterized in that: include: a data driving unit having a first terminal, a first control terminal, a second control terminal, a second terminal, a third control terminal, a third terminal, a fourth control terminal, a fourth terminal, and a fifth control terminal, wherein the first terminal is coupled to a first driving voltage, the first control terminal and the third control terminal are both coupled to a light-emitting control signal, the second control terminal is coupled to a first scan signal, the second terminal is coupled to a display data signal, the fourth control terminal is coupled to a second scan signal, and the third terminal is coupled to a light-emitting component driven by a second driving voltage; a first switch unit having a control terminal, a first terminal, and a second terminal, wherein the control terminal is coupled to the first scan signal, the first terminal is coupled to an initialization voltage, and the second terminal is coupled to the third terminal of the data driving unit; a second switch unit having a control terminal, a first terminal, and a second terminal, wherein the control terminal is coupled to a reset signal, the first terminal is coupled to the initialization voltage, and the second terminal is coupled to the fourth terminal of the data driving unit; a capacitor having a first terminal and a second terminal, wherein the first terminal is coupled to the first terminal of the data driving unit, and the second terminal is coupled to the fifth control terminal of the data driving unit; as well as A third switch unit has a control end, a first end, and a second end, wherein the control end is coupled to the first scan signal, the first end is simultaneously coupled to the fifth control end of the data driving unit and the second end of the capacitor, and the second end is coupled to the fourth end of the data driving unit and the second end of the second switch unit.

2. The pixel circuit according to claim 1, wherein: The second switch unit includes a first TFT component having a gate terminal, a first electrical terminal and a second electrical terminal serving as a control terminal, a first terminal and a second terminal of the second switch unit respectively.

3. The pixel circuit according to claim 2, wherein: The data driving unit includes: a second TFT element having a gate terminal, a first electrical terminal, and a second electrical terminal, wherein the gate terminal and the first electrical terminal serve as a fourth control terminal and a fourth terminal of the data driving unit, respectively; a third TFT element having a gate terminal, a first electrical terminal, and a second electrical terminal, wherein the gate terminal serves as the fifth control terminal of the data driving unit, and the first electrical terminal is coupled to the second electrical terminal of the second TFT element; a fourth TFT element having a gate terminal, a first electrical terminal, and a second electrical terminal, wherein the gate terminal and the first electrical terminal serve as the second control terminal and the second terminal of the data driving unit, respectively, and the second electrical terminal is coupled to the second electrical terminal of the third TFT element; a fifth TFT element having a gate terminal, a first electrical terminal, and a second electrical terminal, wherein the gate terminal and the first electrical terminal serve as the first control terminal and the first terminal of the data driving unit, respectively, and the second electrical terminal is coupled to the second electrical terminal of the third TFT element; and A sixth TFT component has a gate terminal, a first electrical terminal and a second electrical terminal, wherein the gate terminal and the first electrical terminal serve as the third control terminal and the third terminal of the data driving unit respectively, and the second electrical terminal is coupled to the second electrical terminal of the second TFT component.

4. The pixel circuit according to claim 3, wherein: The first switch unit includes a seventh TFT component whose gate terminal, a first electrical terminal and a second electrical terminal serve as the control terminal, the first terminal and the second terminal of the first switch unit respectively, and the third switch unit includes an eighth TFT component whose gate terminal, a first electrical terminal and a second electrical terminal serve as the control terminal, the first terminal and the second terminal of the third switch unit respectively.

5. The pixel circuit according to claim 4, wherein: The first TFT component and the second TFT component are N-type LTPO thin film transistors, and the third TFT component, the fourth TFT component, the fifth TFT component, the sixth TFT component, the seventh TFT component, and the eighth TFT component are P-type LTPS thin film transistors.

6. A flat panel display device comprising a display driver circuit and a flat panel display panel, wherein the flat panel display panel comprises M×N pixel units, where M and N are both positive integers, and each pixel unit comprises a pixel circuit and a light-emitting element; characterized in that: The pixel circuit comprises: a data driving unit having a first terminal, a first control terminal, a second control terminal, a second terminal, a third control terminal, a third terminal, a fourth control terminal, a fourth terminal, and a fifth control terminal, wherein the first terminal is coupled to a first driving voltage, the first control terminal and the third control terminal are both coupled to a light-emitting control signal, the second control terminal is coupled to a first scan signal, the second terminal is coupled to a display data signal, the fourth control terminal is coupled to a second scan signal, and the third terminal is coupled to a light-emitting component driven by a second driving voltage; a first switch unit having a control terminal, a first terminal, and a second terminal, wherein the control terminal is coupled to the first scan signal, the first terminal is coupled to an initialization voltage, and the second terminal is coupled to the third terminal of the data driving unit; a second switch unit having a control terminal, a first terminal, and a second terminal, wherein the control terminal is coupled to a reset signal, the first terminal is coupled to the initialization voltage, and the second terminal is coupled to the fourth terminal of the data driving unit; a capacitor having a first terminal and a second terminal, wherein the first terminal is coupled to the first terminal of the data driving unit, and the second terminal is coupled to the fifth control terminal of the data driving unit; and A third switch unit has a control end, a first end, and a second end, wherein the control end is coupled to the first scan signal, the first end is simultaneously coupled to the fifth control end of the data driving unit and the second end of the capacitor, and the second end is coupled to the fourth end of the data driving unit and the second end of the second switch unit.

7. The flat panel display device according to claim 6, wherein: The second switch unit includes a first TFT component having a gate terminal, a first electrical terminal and a second electrical terminal serving as a control terminal, a first terminal and a second terminal of the second switch unit respectively.

8. The flat panel display device according to claim 7, wherein: The data driving unit includes: a second TFT element having a gate terminal, a first electrical terminal, and a second electrical terminal, wherein the gate terminal and the first electrical terminal serve as a fourth control terminal and a fourth terminal of the data driving unit, respectively; a third TFT element having a gate terminal, a first electrical terminal, and a second electrical terminal, wherein the gate terminal serves as the fifth control terminal of the data driving unit, and the first electrical terminal is coupled to the second electrical terminal of the second TFT element; a fourth TFT element having a gate terminal, a first electrical terminal, and a second electrical terminal, wherein the gate terminal and the first electrical terminal serve as the second control terminal and the second terminal of the data driving unit, respectively, and the second electrical terminal is coupled to the second electrical terminal of the third TFT element; a fifth TFT element having a gate terminal, a first electrical terminal, and a second electrical terminal, wherein the gate terminal and the first electrical terminal serve as the first control terminal and the first terminal of the data driving unit, respectively, and the second electrical terminal is coupled to the second electrical terminal of the third TFT element; and A sixth TFT component has a gate terminal, a first electrical terminal and a second electrical terminal, wherein the gate terminal and the first electrical terminal serve as the third control terminal and the third terminal of the data driving unit respectively, and the second electrical terminal is coupled to the second electrical terminal of the second TFT component.

9. The flat panel display device according to claim 8, wherein: The first switch unit includes a seventh TFT component whose gate terminal, a first electrical terminal and a second electrical terminal serve as the control terminal, the first terminal and the second terminal of the first switch unit respectively, and the third switch unit includes an eighth TFT component whose gate terminal, a first electrical terminal and a second electrical terminal serve as the control terminal, the first terminal and the second terminal of the third switch unit respectively.

10. The flat panel display device according to claim 9, wherein: The first TFT component and the second TFT component are N-type LTPO thin film transistors, while the third TFT component, the fourth TFT component, the fifth TFT component, the sixth TFT component, the seventh TFT component, and the eighth TFT component are P-type LTPS thin film transistors.

11. The flat panel display device according to claim 10, wherein: The flat display panel includes one of an organic light-emitting diode (OLED) display panel and a micro light-emitting diode (Mirco-LED) display panel.

12. An information processing device, characterized in that: The invention comprises the flat panel display device according to any one of claims 6 to 11.

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