Power supply box monitoring reset circuit for ink-jet printer

Abstract

The utility model discloses a power supply box monitoring reset circuit for an ink-jet printer, which comprises a power supply anode VDD42V, the input end of the power supply anode VDD42V is connected with the anode of a power supply box, and the output end of the power supply anode VDD42V is connected with a divider resistor R856 and a divider resistor R858 in series; the input end of the reset ICU92 is connected with the divider resistor R856 and the divider resistor R858; the output end of the reset ICU92 is connected with a buffer U93, and the output end of the power supply VCC3V3M is connected with a filter capacitor C467, a filter capacitor C468 and the buffer U93; by using the reset ICU92, repeated reset caused by unstable voltage of the power supply box can be prevented, and error reset caused by voltage fluctuation when the power supply box is started or powered off is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of digital inkjet printing equipment, in particular to a power box monitoring reset circuit for an inkjet printer. Background Art

[0002] Currently, most printer board designs have power boxes that directly power the board when they are started, and then the reset IC directly resets the main control. This design occasionally causes the board's system to be reset incorrectly. Furthermore, due to the uneven design quality of power boxes on the market, some power boxes will restart multiple times when they are started or powered off, causing the system to trigger resets multiple times. Summary of the Invention

[0003] In order to solve the above-mentioned technical problems, the utility model provides a power box monitoring reset circuit for an inkjet printer.

[0004] The technical solution of the present utility model is achieved as follows:

[0005] A power box monitoring reset circuit for an inkjet printer, comprising:

[0006] A positive power supply electrode VDD_42V, wherein the input end of the positive power supply electrode VDD_42V is connected to the positive electrode of the power supply box, and the output end of the positive power supply electrode VDD_42V is connected in series with a voltage dividing resistor R856 and a voltage dividing resistor R858;

[0007] It also includes a reset IC_U92, the input end of which is connected to the voltage-dividing resistor R856 and the voltage-dividing resistor R858; the output end of the reset IC_U92 is connected to the buffer U93, and also includes a power supply VCC_3V3M, the output end of the power supply VCC_3V3M is connected to the filter capacitor C467, the filter capacitor C468 and the buffer U93.

[0008] The output end of the buffer U93 is connected to the signal FPGA_GSRN, ie, the reset signal input end of the main control IC.

[0009] The output ends of the voltage-dividing resistors R856 and R858 are both connected to a voltage-stabilizing diode D306 , the output end of the voltage-stabilizing diode D306 is connected to a filter capacitor C469 , and the output end of the filter capacitor C469 is grounded.

[0010] The output end of the reset IC_U92 is further connected to a voltage divider resistor R857, and the output end of the voltage divider resistor R857 is connected to the input end of the buffer U93.

[0011] The output ends of the filter capacitor C467 and the filter capacitor C468 are both grounded.

[0012] The signal FPGA_GSRN input end is further connected to a voltage divider resistor R860, and the input end of the voltage divider resistor R860 is connected to the buffer U93.

[0013] Compared with the prior art, the present invention has the following beneficial effects:

[0014] 1. This utility model uses reset IC_U92 to ensure that the reset signal is not generated immediately when the power box is started. This can avoid false resets caused by voltage fluctuations at the moment the power box is started. Through the voltage divider resistors (R856 and R858) and the voltage regulator diode (D306), this design monitors the power supply voltage (VDD_42V) of the power box, ensuring that the reset IC only starts working when the voltage reaches a certain threshold. This can prevent multiple resets caused by unstable power box voltage.

[0015] 2. After detecting a stable power supply voltage, reset IC_U92 will delay for a period of time before generating a reset signal. This period of time is called reset time. This ensures that the power box has enough time to stabilize after power-on, thereby reducing the possibility of false reset.

[0016] 3. Buffer U93 performs secondary buffering and delay on the reset signal to ensure that the reset signal is transmitted to the main control IC only after it is stable, reducing false resets caused by voltage fluctuations when the power box is started or powered off; through filtering capacitors (C469, C467, C468) and voltage regulator diode (D306), the voltage provided by the power box is ensured to be stable, reducing voltage fluctuations and false resets caused by uneven design quality of the power box. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 The utility model is a circuit diagram of a power box monitoring reset circuit for an inkjet printer. DETAILED DESCRIPTION

[0018] In order to make the purposes, features, and advantages of the present invention more obvious and easy to understand, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described below are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0019] like Figure 1 As shown, a power box monitoring reset circuit for an inkjet printer includes:

[0020] A positive power supply electrode VDD_42V, wherein the input end of the positive power supply electrode VDD_42V is connected to the positive electrode of the power supply box, and the output end of the positive power supply electrode VDD_42V is connected in series with a voltage dividing resistor R856 and a voltage dividing resistor R858;

[0021] It also includes a reset IC_U92, the input end of which is connected to the voltage-dividing resistor R856 and the voltage-dividing resistor R858; the output end of the reset IC_U92 is connected to the buffer U93, and also includes a power supply VCC_3V3M, the output end of the power supply VCC_3V3M is connected to the filter capacitor C467, the filter capacitor C468 and the buffer U93.

[0022] The output end of the buffer U93 is connected to the signal FPGA_GSRN, ie, the reset signal input end of the main control IC.

[0023] The output ends of the voltage-dividing resistors R856 and R858 are both connected to a voltage-stabilizing diode D306 , the output end of the voltage-stabilizing diode D306 is connected to a filter capacitor C469 , and the output end of the filter capacitor C469 is grounded.

[0024] The output end of the reset IC_U92 is further connected to a voltage divider resistor R857, and the output end of the voltage divider resistor R857 is connected to the input end of the buffer U93.

[0025] The output ends of the filter capacitor C467 and the filter capacitor C468 are both grounded.

[0026] The signal FPGA_GSRN input end is further connected to a voltage divider resistor R860, and the input end of the voltage divider resistor R860 is connected to the buffer U93.

[0027] In this utility model:

[0028] The positive power supply VDD_42V is connected to the positive power supply of the power box, which provides the power supply voltage for the entire circuit;

[0029] Filter capacitor C469 is a filter capacitor connected to the positive power supply VDD_42V, which is used to smooth the voltage fluctuations on the power line and provide a more stable power supply;

[0030] The voltage divider resistors R856 and R858 are voltage divider resistors, which are connected in series with the positive power supply VDD_42V to reduce the voltage of the positive power supply VDD_42V to a level suitable for the operating voltage of the reset IC_U92;

[0031] The voltage regulator D306 is a 3.3V voltage regulator. It is connected in parallel to the power supply pin VIN of the reset IC_U92 to ensure that the power supply voltage of the reset IC_U92 does not exceed 3.3V, protecting the IC from damage due to excessive voltage.

[0032] Reset IC_U92 resets ICMAX809S. Its 3rd pin VIN receives the voltage divided by the voltage divider resistors R856 and R858. When the voltage of the positive power supply VDD_42V reaches 17.58V, reset IC_U92 starts working and generates a reset signal.

[0033] Filter capacitors C467 and C468 are filter capacitors connected to the power supply VCC_3V3M of reset IC_U92 to provide a stable power supply for reset IC_U92.

[0034] Buffer U93 receives the reset signal from reset IC_U92 and performs secondary buffering and delay to ensure that the reset signal is stable before being passed to the main control IC;

[0035] The input signal FPGA_GSRN is the reset signal input terminal of the main control IC, which receives the stable reset signal from the buffer U93;

[0036] VCC_3V3M provides power for U93.

[0037] The working principle of this utility model is as follows:

[0038] When the power box is turned on, the positive power supply VDD_42V will supply power to the board. At this time, the power supply voltage VIN of the reset IC_U92 will not be immediately available. The working voltage of VIN is about 2.98V, so according to the voltage divider resistor, VIN=voltage divider resistor R858 / (voltage divider resistor R856+voltage divider resistor R858)*positive power supply VDD_42V. If VIN=2.98V, then the positive power supply VDD_42V=17.58V can be calculated. Therefore, after the power box is turned on, the reset IC_U92 will officially enter the working state when the positive power supply VDD_42V rises to 17.58V. If the voltage value is lower than this, the system will not work.

[0039] The voltage regulator D306 is a 3.3V voltage regulator. When the divided VIN value is higher than 3.3V, the voltage regulator can ensure that the voltage of VIN does not exceed 3.3V, which can protect the reset IC_U92 from burning out due to excessive voltage.

[0040] When the positive power supply VDD_42V=17.58V, reset IC_U92 will delay the RESET signal to a low level for a period of time. This period of time is called reset time, and then the level will be pulled high again.

[0041] The function of the U93 buffer is to buffer and delay the reset signal. In this case, the reset signal FPGA_GSRN is given to the main control IC only after it stabilizes, avoiding false reset state.

[0042] This design can also ensure that the power box will not enter the reset state immediately after powering on, thus ensuring the stability of the reset signal.

Claims

1. A power box monitoring reset circuit for an inkjet printer, characterized in that: include: A positive power supply electrode VDD_42V, wherein the input end of the positive power supply electrode VDD_42V is connected to the positive electrode of the power supply box, and the output end of the positive power supply electrode VDD_42V is connected in series with a voltage dividing resistor R856 and a voltage dividing resistor R858; It also includes a reset IC_U92, the input end of which is connected to the voltage-dividing resistor R856 and the voltage-dividing resistor R858; the output end of the reset IC_U92 is connected to the buffer U93, and also includes a power supply VCC_3V3M, the output end of the power supply VCC_3V3M is connected to the filter capacitor C467, the filter capacitor C468 and the buffer U93.

2. A power supply box monitoring reset circuit for an inkjet printer according to claim 1, characterized in that: The output end of the buffer U93 is connected to the signal FPGA_GSRN, ie, the reset signal input end of the main control IC.

3. The power supply box monitoring reset circuit for an inkjet printer according to claim 1, characterized in that: The output ends of the voltage-dividing resistors R856 and R858 are both connected to a voltage-stabilizing diode D306 , the output end of the voltage-stabilizing diode D306 is connected to a filter capacitor C469 , and the output end of the filter capacitor C469 is grounded.

4. The power supply box monitoring reset circuit for an inkjet printer according to claim 1, characterized in that: The output end of the reset IC_U92 is further connected to a voltage divider resistor R857, and the output end of the voltage divider resistor R857 is connected to the input end of the buffer U93.

5. The power box monitoring reset circuit for an inkjet printer according to claim 1, characterized in that: The output ends of the filter capacitor C467 and the filter capacitor C468 are both grounded.

6. The power supply box monitoring reset circuit for an inkjet printer according to claim 2, characterized in that: The signal FPGA_GSRN input end is further connected to a voltage divider resistor R860, and the input end of the voltage divider resistor R860 is connected to the buffer U93.

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