Core board based on MT8395 processor

Abstract

The utility model belongs to the field of Internet of Things, and relates to a core board based on an MT8395 processor, which comprises the MT8395 processor, a golden finger electrically connected with the MT8395 processor, an encryption circuit, an RTC clock circuit, an eMMC memory and a PHY chip, the MT8395 processor is directly connected with the golden finger through a PCIE bus, the MT8395 processor is used for data processing of the core board, and the golden finger and the MT8395 processor work cooperatively; the encryption circuit is used for providing an encryption function for the core board, the RTC clock circuit is used for providing a time reference for the core board, the eMMC memory is used for storing an operating system, an application program and a data file, and the PHY chip is used for converting a digital signal into an analog signal or converting the analog signal into the digital signal so as to realize data transmission. The hardware design of the core board is simplified, the cost is reduced, the power consumption is reduced, and the safety and reliability are enhanced.

Description

Technical Field

[0001] The utility model relates to the technical field of Internet of Things, and more specifically, to a core board based on an MT8395 processor. Background Art

[0002] SMARC (Smart Mobility Architecture) is a standard for computer-on-modules (COMs) for embedded systems, designed to enhance computing power and flexibility, particularly in industrial automation, medical equipment, transportation, and the Internet of Things. SMARC modules typically include core components such as a processor, memory, storage, and communication interfaces. They are compact, low-power, and high-performance, making them easy to deploy and use in a variety of environments.

[0003] The origins of SMARC can be traced back to the evolving demands for embedded systems, particularly for applications requiring high computing power and flexibility. The introduction of this standard offers the advantages of modular design, making it easier for device manufacturers to develop and deploy complex embedded systems.

[0004] The LEC-MKT-I1200 SMARC computer module uses the MediaTek Genio1200 processing chip and is designed for edge AI IoT processing needs and 4K graphics display applications. It can realize terminal AI devices and simultaneously support multiple 4K-quality displays and camera inputs.

[0005] The core board of LEC-MKT-I1200 lacks functional optimization in terms of power consumption, cost, performance, hardware design simplification and security encryption. Utility Model Content

[0006] In view of the above-mentioned defects of the prior art, the present invention provides a core board based on the MT8395 processor, comprising:

[0007] An MT8395 processor, a gold finger, an encryption circuit, an RTC clock circuit, an eMMC memory, and a PHY chip electrically connected to the MT8395 processor, the MT8395 and the gold finger being directly connected via a PCIE bus, the MT8395 processor being used for data processing of the core board, and the gold finger working in conjunction with the MT8395 processor; the encryption circuit being used to provide an encryption function for the core board, the RTC clock circuit being used to provide an accurate time reference for the core board, the eMMC memory being used to store an operating system, applications, and data files, and the PHY chip being used to convert digital signals into analog signals or convert analog signals into digital signals to achieve data transmission.

[0008] Preferably, the encryption circuit includes: pin 1 of the programmable mixed signal matrix chip U110 is connected to one end of the capacitor C1100, pin 2 of the programmable mixed signal matrix chip U110 is respectively connected to one end of the resistor R1205 and one end of the resistor R1200, pin 3 of the programmable mixed signal matrix chip U110 is connected to pin 7 of the bidirectional level conversion chip U115, pin 4 of the programmable mixed signal matrix chip U110 is connected to pin 6 of the bidirectional level conversion chip U115, pin 8 of the bidirectional level conversion chip U115 is connected to one end of the capacitor C873, the other end of the capacitor C873 is grounded, pin 5 of the bidirectional level conversion chip U115 is respectively connected to one end of the resistor R896 and one end of the resistor R895, pin 1 of the bidirectional level conversion chip U115 is connected to one end of the capacitor C872, and the other end of the capacitor C872 is grounded.

[0009] Preferably, the RTC clock circuit includes: pin L13 of the power management chip U2H is respectively connected to one end of capacitor C214 and one end of resistor R58, the other end of capacitor C214 is grounded, the other end of resistor R58 is connected to one end of capacitor C215, and the other end of capacitor C215 is grounded.

[0010] Preferably, the core board further includes a power conversion circuit, which includes: pin 20 of the buck converter chip U111 is respectively connected to pin 21 of the buck converter chip U111, one end of capacitor C824, one end of capacitor C818, one end of capacitor C817, one end of capacitor C816, one end of capacitor C815, one end of capacitor C829, and one end of resistor R1196; the other end of capacitor C824 is respectively connected to the other end of capacitor C818, the other end of capacitor C817, the other end of capacitor C816, the other end of capacitor C815, and the other end of capacitor C829 and is grounded; pin 19 of the buck converter chip U111 is connected to one end of capacitor C1098 and one end of resistor R1194; capacitor C816 is respectively connected to the other end of capacitor C818, the other end of capacitor C817, the other end of capacitor C816, the other end of capacitor C815, and the other end of capacitor C829; The other end of 98 is grounded, the other end of resistor R1194 is connected to pin 9 of the buck converter chip U111, pin 8 of the buck converter chip U111 is respectively connected to one end of capacitor C1099, the other end of resistor R1196, and one end of resistor R1239, pin 4 of the buck converter chip U111 is respectively connected to one end of resistor R1198 and one end of resistor R1197, the other end of resistor R1198 is grounded, pin 1 of the buck converter chip U111 is connected to one end of capacitor C844, the other end of capacitor C844 is respectively connected to one end of inductor L73 and pin 20 of the buck converter chip U111, and pin 7 of the buck converter chip U111 is respectively connected to one end of resistor R874 and one end of resistor R875.

[0011] Preferably, the core board also includes: an HDMI circuit, wherein the HDMI circuit includes: pin 1 of the MOSFET chip Q28 is connected to one end of the resistor R645, pin 2 of the MOSFET chip Q28 is connected to the other end of the resistor R645, pin 3 of the MOSFET chip Q28 is respectively connected to one end of the resistor R648, one end of the resistor R649, and the negative electrode of the diode D17, the positive electrode of the diode D17 is connected to one end of the resistor R643, the other end of the resistor R649 is connected to pin 2 of the protection chip ESD57, and pin 1 of the protection chip ESD57 is grounded.

[0012] Preferably, the core board further includes: a power management circuit, wherein the power management circuit includes: pin J9 of the power management chip U5C is respectively connected to pin K9 of the power management chip U5C and one end of the capacitor C250; the other end of the capacitor C250 is respectively connected to pin J11 of the power management chip U5C and pin K11 of the power management chip U5C; pin J8 of the power management chip U5C is respectively connected to pin K8 of the power management chip U5C and one end of the capacitor C259; the other end of the capacitor C259 is respectively connected to the power management chip U5C; 5C is connected to pin J6 of the power management chip U5C and pin K6 of the power management chip U5C, pin J10 of the power management chip U5C is respectively connected to pin K10 of the power management chip U5C and one end of the inductor PL16, the other end of the inductor PL16 is respectively connected to one end of capacitor C253 and one end of capacitor C254, pin J7 of the power management chip U5C is respectively connected to pin K7 of the power management chip U5C and one end of the inductor PL17, the other end of the inductor PL17 is connected to one end of capacitor C260, and the other end of capacitor C260 is grounded.

[0013] Preferably, the core board also includes: an LP4X DRAM I / O interface voltage 0.75V circuit, and the LP4X DRAM I / O interface voltage 0.75V circuit includes, pin A1 of the wireless communication chip U6 is respectively connected to pin B1 of the wireless communication chip U6, pin C1 of the wireless communication chip U6, one end of capacitor C826, and one end of capacitor C825, pin E2 of the wireless communication chip U6 is respectively connected to one end of resistor R237 and one end of resistor R239, pin D3 of the wireless communication chip U6 is respectively connected to one end of resistor R243 and one end of resistor R241, pin D2 of the wireless communication chip U6 is connected to one end of resistor R245, pin A2 of the wireless communication chip U6 is respectively connected to pin B2 of the wireless communication chip U6 and one end of inductor L18, and the other end of inductor L18 is connected to one end of capacitor C823.

[0014] Preferably, the core board also includes: a DRAM power supply voltage 1.8V circuit, the DRAM power supply voltage 1.8V circuit includes, pin C2 of the voltage regulating chip U7 is respectively connected to one end of the resistor R251 and one end of the capacitor C811, pin B2 of the voltage regulating chip U7 is connected to one end of the resistor R254, pin A2 of the voltage regulating chip U7 is respectively connected to one end of the resistor R255 and one end of the capacitor C813, the other end of the capacitor C813 is grounded, pin B1 of the voltage regulating chip U7 is respectively connected to one end of the resistor R253, one end of the capacitor C426, and one end of the resistor R252, pin A1 of the voltage regulating chip U7 is respectively connected to the other end of the capacitor C426, the other end of the resistor R252, and one end of the capacitor C812, and the other end of the capacitor C812 is grounded.

[0015] Preferably, the core board also includes: a UART circuit, wherein the UART circuit includes: pin 1 of the logic level converter chip U87 is respectively connected to one end of the resistor R760 and one end of the capacitor C357, the other end of the capacitor C357 is grounded, the other end of the resistor R760 is connected to pin 12 of the logic level converter chip U87, pin 11 of the logic level converter chip U87 is respectively connected to one end of the resistor R761, one end of the resistor R762, and one end of the capacitor C358, pin 10 of the logic level converter chip U87 is connected to the other end of the resistor R761, pin 9 of the logic level converter chip U87 is connected to the other end of the resistor R762, and the other end of the capacitor C358 is connected to pin 6 of the logic level converter chip U87 and grounded.

[0016] Preferably, the core board further includes: an eDP and DSI0 two-in-one circuit, and the eDP and DSI0 two-in-one circuit includes a bidirectional passive switch chip U99.

[0017] The core board based on the MT8395 processor of the present invention has the following beneficial effects:

[0018] First, the connection between the SOC (MT8395) and the MXM3 (SMARC2.1 standard) gold finger on the PCIE bus adopts a direct connection, without the need for a clock management chip and PCIE multiplexing switch (which is used in ADLINK's core board). This not only simplifies the core board hardware design and reduces costs, but also reduces the power consumption of the core board.

[0019] Secondly, the MT8395 core board has added a secure encryption chip design, which enhances the security and reliability of the core board;

[0020] Third, the RTC clock of the MT8395 core board uses the MT6365 (PMIC) with its own output (ADLINK also adds a dedicated RTC clock chip 8563), which reduces costs and simplifies hardware design.

[0021] Fourth, the MT8395 core board uses eMMC for storage (ADLINK uses UFS). eMMC is the mainstream storage solution for embedded systems. It has mature technology, is relatively cheaper than UFS, is easy to purchase, and is the best choice for later mass production of products.

[0022] Fifth, the PHY chip of the MT8395 core board GBE0 uses Realtek's RTL8211 FI-CG (ADLINK uses DP83867). This PHY chip is widely recognized in the market, with a small package size, relatively simple design and low price. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative work. The following will further illustrate the present invention in conjunction with the drawings and embodiments. In the drawings:

[0024] Figure 1 This is a schematic diagram of the core board of the utility model based on the MT8395 processor;

[0025] Figure 2 This is the circuit diagram of the encryption circuit in the core board based on the MT8395 processor of the utility model;

[0026] Figure 3 This is a circuit diagram of the RTC clock circuit in the core board based on the MT8395 processor of the utility model;

[0027] Figure 4 This is a circuit diagram of the power conversion circuit in the core board based on the MT8395 processor of the utility model;

[0028] Figure 5 This is the circuit diagram of the HDM I circuit in the core board based on the MT8395 processor of the utility model;

[0029] Figure 6 This is the circuit diagram of the power management circuit in the core board based on the MT8395 processor of the utility model;

[0030] Figure 7This is the circuit diagram of the LP4X DRAM I / O interface voltage 0.75V circuit in the core board based on the MT8395 processor of the utility model;

[0031] Figure 8 This is a circuit diagram of a DRAM power supply voltage 1.8V circuit in a core board based on the MT8395 processor of the utility model;

[0032] Figure 9 This is a circuit diagram of the UART circuit in the core board based on the MT8395 processor of the utility model;

[0033] Figure 10 This is a circuit diagram of the eDP and DS 1 0 two-in-one circuit in the core board based on the MT8395 processor of the utility model. DETAILED DESCRIPTION

[0034] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0035] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indications will also change accordingly.

[0036] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features specified as "first" or "second" may explicitly or implicitly include at least one of such features. In addition, the technical solutions between the various embodiments can be combined with each other, but this must be based on the fact that ordinary technicians in this field can implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0037] See also Figure 1 , is a schematic diagram of the core board of the utility model based on the MT8395 processor. Figure 1As shown, the core board based on the MT8395 processor provided in the first embodiment of the present invention includes at least an MT8395 processor, a gold finger electrically connected to the MT8395 processor (refer to the SMARC standard definition), an encryption circuit, an RTC clock circuit, an eMMC memory, and a PHY chip. The MT8395 is directly connected to the gold finger through the PCIE bus. The MT8395 processor is used for data processing of the core board, and the gold finger works with the MT8395 processor; the encryption circuit is used to provide encryption function for the core board, the RTC clock circuit is used to provide an accurate time reference for the core board, the eMMC memory is used to store operating systems, applications and data files, and the PHY chip is used to convert digital signals into analog signals or convert analog signals into digital signals to realize data transmission.

[0038] Gold fingers refer to board edge connectors or edge gold-plated connectors. They are primarily used to achieve stable connections and efficient signal transmission between circuit boards. Gold fingers are in the form of narrow, gold-plated contacts, characterized by strong conductivity, corrosion resistance, and wear resistance, ensuring high performance and long life of the circuit system. In this embodiment, the gold fingers use 314 pins. Since the 314-pin gold fingers refer to the SMARC 2.1 standard, the core board of this utility model is also a module that implements the SMARC interface.

[0039] The MT8395 (Genio 1200) is a general-purpose system-on-chip (SoC) designed for high-performance Internet of Things (AI-oT) and artificial intelligence (AI) applications. The MT8395 (Genio 1200) is the core component of the core board, integrating an octa-core CPU (including four Cortex-A78 high-performance cores and four Cortex-A55 high-performance cores), a five-core Mal i-G57 graphics processor (GPU), and an independent dual-core AI processor unit (APU). These features enable it to handle high-performance computing and complex graphics rendering tasks.

[0040] In specific implementation, the PHY chip can adopt Realtek's RTL8211 FI-CG.

[0041] Figure 2 This is the encryption circuit diagram of the core board based on the MT8395 processor of the utility model. Figure 2As shown, the encryption circuit includes: Pin 1 of the programmable mixed signal matrix chip U110 is connected to one end of the capacitor C1100, Pin 2 of the programmable mixed signal matrix chip U110 is connected to one end of the resistor R1205 and one end of the resistor R1200, Pin 3 of the programmable mixed signal matrix chip U110 is connected to Pin 7 of the bidirectional level conversion chip U115, Pin 4 of the programmable mixed signal matrix chip U110 is connected to Pin 6 of the bidirectional level conversion chip U115, Pin 8 of the bidirectional level conversion chip U115 is connected to one end of the capacitor C873, the other end of the capacitor C873 is grounded, Pin 5 of the bidirectional level conversion chip U115 is connected to one end of the resistor R896 and one end of the resistor R895, Pin 1 of the bidirectional level conversion chip U115 is connected to one end of the capacitor C872, the other end of the capacitor C872 is grounded. In a specific implementation, the programmable mixed signal matrix chip U110 can be, but is not limited to, SLG46811, etc.

[0042] As a key member of the GreenPAK family, the SLG46811 integrates an analog temperature sensor, readback protection, an I2C communication interface, and advanced encryption technology, enabling the design of a variety of mixed-signal functions within a very small, low-power single integrated circuit. The chip is programmed via one-time programmable (OTP) non-volatile memory (NVM), enabling configuration of interconnect logic, I / O pins, and macrocells to meet diverse circuit design requirements. It supports an operating voltage range of 2.3V to 5.5V and a temperature range of -40°C to 85°C. It is housed in a 12-pin STQFN package, is RoHS-compliant, halogen-free, and environmentally friendly.

[0043] In the Internet of Things (IoT), the SLG46811 seamlessly connects to various sensors and actuators via the I2C communication interface, enabling data collection, processing, and transmission, thereby building efficient and reliable IoT systems. In embedded system design, the SLG46811, with its flexible configuration capabilities and low power consumption, can significantly reduce the number of external circuit components, lower system complexity, and improve overall performance. Furthermore, the chip supports bidirectional I2C-to-SPI conversion, providing a convenient solution for communication between different protocols and further expanding its application in various digital projects.

[0044] The encryption circuit encrypts input data using a built-in encryption algorithm (such as AES or RSA) to generate ciphertext. It also provides key management functions, including key generation, storage, distribution, and updates, to ensure key security and reliability. When data decryption is required, the encryption circuit uses the corresponding key and algorithm to decrypt the data and restore the original data. Encryption circuits typically use physical isolation to protect the encryption algorithm and key to prevent external attacks and cracking.

[0045] Figure 3 This is the RTC clock circuit circuit diagram in the core board based on the MT8395 processor of the utility model. Figure 3 As shown, the RTC clock circuit includes: Pin L13 of the power management chip U2H is connected to one end of a capacitor C214 and one end of a resistor R58, respectively. The other end of capacitor C214 is grounded. The other end of resistor R58 is connected to one end of a capacitor C215, and the other end of capacitor C215 is grounded. The power management chip U2H can be, but is not limited to, an MT6365.

[0046] The MT6365 uses a 203-pin WFBGA package and supports a wide input voltage range of 2.6V to 5V, enabling it to operate stably in a variety of power supply environments. The chip has nine built-in buck converters and 33 low-dropout linear regulators (LDOs) to meet the precise power supply requirements of different subsystems.

[0047] Figure 4 This is the power conversion circuit diagram of the core board based on the MT8395 processor of the utility model. Figure 4As shown, in a specific implementation, the core board may further include a power conversion circuit, which includes: pin 20 of the buck converter chip U111 is respectively connected to pin 21 of the buck converter chip U111, one end of capacitor C824, one end of capacitor C818, one end of capacitor C817, one end of capacitor C816, one end of capacitor C815, one end of capacitor C829, and one end of resistor R1196; the other end of capacitor C824 is respectively connected to the other end of capacitor C818, the other end of capacitor C817, the other end of capacitor C816, the other end of capacitor C815, and the other end of capacitor C829 and is grounded; pin 19 of the buck converter chip U111 is connected to one end of capacitor C1098 and one end of resistor R1194; capacitor C The other end of resistor R1098 is connected to ground. The other end of resistor R1194 is connected to pin 9 of buck converter chip U111. Pin 8 of buck converter chip U111 is connected to one end of capacitor C1099, the other end of resistor R1196, and one end of resistor R1239. Pin 4 of buck converter chip U111 is connected to one end of resistor R1198 and one end of resistor R1197. The other end of resistor R1198 is grounded. Pin 1 of buck converter chip U111 is connected to one end of capacitor C844. The other end of capacitor C844 is connected to one end of inductor L73 and pin 20 of buck converter chip U111. Pin 7 of buck converter chip U111 is connected to one end of resistor R874 and one end of resistor R875. Buck converter chip U111 may be, but is not limited to, MPQ8633AGLE, etc.

[0048] The MPQ8633AGLE chip provides efficient and stable voltage conversion, suitable for a variety of applications requiring a wide input voltage range and high output current. Key features include high-efficiency voltage conversion, programmability, protection mechanisms, and a compact design.

[0049] Figure 5 This is the circuit diagram of the HDM I circuit in the core board based on the MT8395 processor of the utility model. Figure 5 As shown, during specific implementation, the core board may further include: an HDM I circuit, which includes: pin 1 of the MOSFET chip Q28 connected to one end of the resistor R645, pin 2 of the MOSFET chip Q28 connected to the other end of the resistor R645, pin 3 of the MOSFET chip Q28 connected to one end of the resistor R648, one end of the resistor R649, and the cathode of the diode D17, respectively; the anode of the diode D17 connected to one end of the resistor R643, the other end of the resistor R649 connected to pin 2 of the protection chip ESD57, and pin 1 of the protection chip ESD57 connected to ground. The provision of the HDM I circuit expands the scope of use of this core board.

[0050] Figure 6 This is the power management circuit diagram of the core board based on the MT8395 processor of the utility model. Figure 6 As shown, in a specific implementation, the core board may further include: a power management circuit, the power management circuit includes: pin J9 of the power management chip U5C is connected to pin K9 of the power management chip U5C and one end of the capacitor C250, the other end of the capacitor C250 is connected to pin J11 of the power management chip U5C and pin K11 of the power management chip U5C, the pin J8 of the power management chip U5C is connected to pin K8 of the power management chip U5C and one end of the capacitor C259, the other end of the capacitor C259 is connected to the power management chip Pin J6 of chip U5C is connected to pin K6 of power management chip U5C. Pin J10 of power management chip U5C is connected to pin K10 of power management chip U5C and one end of inductor PL16 respectively. The other end of inductor PL16 is connected to one end of capacitor C253 and one end of capacitor C254 respectively. Pin J7 of power management chip U5C is connected to pin K7 of power management chip U5C and one end of inductor PL17 respectively. The other end of inductor PL17 is connected to one end of capacitor C260. The other end of capacitor C260 is grounded. Power management chip U5C may be, but is not limited to, MT6365 or the like.

[0051] The main functions of MT6365 are:

[0052] The MT6365 uses its internal buck converter and LDO to provide stable and efficient power to various components of the phone (such as the processor, display, camera, sensors, etc.). This refined power management helps extend battery life and improve overall device performance.

[0053] System control supports controlling the switching states of the buck converter, LDO, and various drivers through the SPI interface and two SRCLKEN control pins, achieving fine control of system power consumption. In addition, it can also precisely control power-on and RTC (real-time clock) alarms to ensure stable system operation.

[0054] Enhanced security: The MT6365 provides enhanced security controls and protocols for handshake communication with the baseband processor, ensuring the security and stability of the power management system.

[0055] Figure 7 This is the circuit diagram of the LP4X DRAM I / O interface voltage 0.75V circuit in the core board based on the MT8395 processor of this utility model. Figure 7As shown, the core board may also include: an LP4X DRAM I / O interface voltage 0.75V circuit, and the LP4X DRAM I / O interface voltage 0.75V circuit includes, pin A1 of the wireless communication chip U6 is respectively connected to pin B1 of the wireless communication chip U6, pin C1 of the wireless communication chip U6, one end of capacitor C826, and one end of capacitor C825, pin E2 of the wireless communication chip U6 is respectively connected to one end of resistor R237 and one end of resistor R239, pin D3 of the wireless communication chip U6 is respectively connected to one end of resistor R243 and one end of resistor R241, pin D2 of the wireless communication chip U6 is connected to one end of resistor R245, pin A2 of the wireless communication chip U6 is respectively connected to pin B2 of the wireless communication chip U6 and one end of inductor L18, and the other end of inductor L18 is connected to one end of capacitor C823.

[0056] LP4X DRAM: VMDDR (0.75V) primarily serves as a cache device on the core board, temporarily storing file data during operation. This low-voltage interface not only reduces energy consumption but also improves data transmission efficiency, enabling faster processing speeds and longer battery life.

[0057] Figure 8 This is a circuit diagram of a 1.8V DRAM power supply voltage circuit in a core board based on the MT8395 processor of the utility model. Figure 8 As shown, during specific implementation, the core board may further include: a DRAM power supply voltage 1.8V circuit, which includes: pin C2 of the voltage regulating chip U7 connected to one end of the resistor R251 and one end of the capacitor C811, pin B2 of the voltage regulating chip U7 connected to one end of the resistor R254, pin A2 of the voltage regulating chip U7 connected to one end of the resistor R255 and one end of the capacitor C813, and the other end of the capacitor C813 is grounded, pin B1 of the voltage regulating chip U7 connected to one end of the resistor R253, one end of the capacitor C426, and one end of the resistor R252, pin A1 of the voltage regulating chip U7 connected to the other end of the capacitor C426, the other end of the resistor R252, and one end of the capacitor C812, and the other end of the capacitor C812 is grounded. The voltage regulating chip U7 may be, but is not limited to, MT6680P / A, etc.

[0058] The MT6680P / A's primary function is to stabilize and regulate circuit voltages, ensuring stable operation even in complex operating environments. Its ultra-low leakage voltage makes it particularly suitable for applications where the output voltage is close to the input voltage, such as smart home devices.

[0059] In terms of operating principle, the MT6680P / A converts and regulates the input voltage and uses an external resistor divider to set and adjust the desired output voltage. This design not only improves the accuracy of voltage conversion but also effectively controls the output current, thereby ensuring efficient and stable operation of the system.

[0060] Figure 9 This is the UART circuit diagram in the core board of the utility model based on the MT8395 processor. Figure 9 As shown, the core board may further include: a UART circuit, wherein the UART circuit includes: pin 1 of the logic level converter chip U87 is respectively connected to one end of the resistor R760 and one end of the capacitor C357, the other end of the capacitor C357 is grounded, the other end of the resistor R760 is connected to pin 12 of the logic level converter chip U87, pin 11 of the logic level converter chip U87 is respectively connected to one end of the resistor R761, one end of the resistor R762, and one end of the capacitor C358, pin 10 of the logic level converter chip U87 is connected to the other end of the resistor R761, pin 9 of the logic level converter chip U87 is connected to the other end of the resistor R762, and the other end of the capacitor C358 is connected to pin 6 of the logic level converter chip U87 and grounded. The logic level converter chip U87 may be, but is not limited to, TXB0104RUTR, etc.

[0061] The TXB0104RUTR has a four-channel non-inverting function that can support level translation between two power rails with different voltage ranges (A port: 1.2V to 3.6V; B port: 1.65V to 5.5V), and requires that VCCB (B port voltage) is always higher than VCCA (A port voltage).

[0062] The TXB0104RUTR's primary function is to resolve interface issues between systems with different logic levels, enabling seamless connection and communication. During data transmission and signal processing, the chip automatically completes level conversion, eliminating the need for an additional conversion enable control interface and simplifying circuit design.

[0063] Figure 10 This is the circuit diagram of the eDP and DSI0 two-in-one circuit in the core board based on the MT8395 processor of this utility model. Figure 10 As shown, the core board may further include: an eDP and DSI 0 two-in-one circuit, wherein the eDP and DSI 0 two-in-one circuit includes a bidirectional passive switch chip U99. The bidirectional passive switch chip U99 may be, but is not limited to, TMUXHS4212 I RKSR, etc.

[0064] The TMUXHS4212 I RKSR is a 2-channel, 16Gbps differential multiplexer / demultiplexer. It supports a variety of high-speed interface standards, including but not limited to USB 3.2 (up to 10Gbps), PCI Express (up to 16Gbps, Gen 4.0), SATA, SAS, MIPI DSI / CSI, FPD-Link III, and LVDS. Its differential signal processing capabilities ensure signal integrity and stability at high data rates.

[0065] The TMUXHS4212 I RKSR operates by implementing bidirectional signal transmission through multiplexing and demultiplexing mechanisms. In multiplexing mode, it combines two input signals into a single output; in demultiplexing mode, it decomposes a single input signal into two output signals. The chip supports adaptive common-mode voltage tracking, ensuring stable signal transmission within the common-mode voltage range of 0V to 1.8V. Its excellent dynamic characteristics minimize signal eye diagram attenuation during high-speed switching, while also reducing jitter to ensure signal quality.

[0066] The utility model has the following beneficial effects through the design of the above embodiments:

[0067] First, the connection between the SOC (MT8395) and the MXM3 (SMARC2.1 standard) gold finger on the PCIE bus adopts a direct connection, without the need for a clock management chip and PCIE multiplexing switch (which is used in ADLINK's core board). This not only simplifies the core board hardware design and reduces costs, but also reduces the power consumption of the core board.

[0068] Secondly, the MT8395 core board has added a secure encryption chip design, which enhances the security and reliability of the core board;

[0069] Third, the RTC clock of the MT8395 core board uses the MT6365 (PMIC) with its own output (ADLINK also adds a dedicated RTC clock chip 8563), which reduces costs and simplifies hardware design.

[0070] Fourth, the MT8395 core board uses eMMC for storage (ADLINK uses UFS). eMMC is the mainstream storage solution for embedded systems. It has mature technology, is relatively cheaper than UFS, is easy to purchase, and is the best choice for later mass production of products.

[0071] Fifth, the PHY chip of the MT8395 core board GBE0 uses Realtek's RTL8211 FI-CG (ADLINK uses DP83867). This PHY chip is widely recognized in the market, with a small package size, relatively simple design and low price.

[0072] While the present invention has been described with reference to specific embodiments, those skilled in the art will appreciate that various modifications and equivalents may be made without departing from the scope of the present invention. Furthermore, numerous modifications may be made to adapt the present invention to specific applications without departing from its scope. Therefore, the present invention is not limited to the specific embodiments disclosed herein but encompasses all embodiments falling within the scope of the claims.

Claims

1. A core board based on MT8395 processor, characterized in that, include: MT8395 processor, a gold finger, an encryption circuit, an RTC clock circuit, an eMMC memory, and a PHY chip electrically connected to the MT8395 processor, the MT8395 and the gold finger are directly connected via a PCIE bus, the MT8395 processor is used for data processing of the core board, and the gold finger works in conjunction with the MT8395 processor; The encryption circuit is used to provide encryption function for the core board, the RTC clock circuit is used to provide an accurate time reference for the core board, the eMMC memory is used to store operating systems, applications and data files, and the PHY chip is used to convert digital signals into analog signals or convert analog signals into digital signals to achieve data transmission.

2. The core board based on the MT8395 processor according to claim 1, characterized in that, The encryption circuit includes: pin 1 of the programmable mixed signal matrix chip U110 is connected to one end of the capacitor C1100, pin 2 of the programmable mixed signal matrix chip U110 is respectively connected to one end of the resistor R1205 and one end of the resistor R1200, pin 3 of the programmable mixed signal matrix chip U110 is connected to pin 7 of the bidirectional level conversion chip U115, pin 4 of the programmable mixed signal matrix chip U110 is connected to pin 6 of the bidirectional level conversion chip U115, pin 8 of the bidirectional level conversion chip U115 is connected to one end of the capacitor C873, the other end of the capacitor C873 is grounded, pin 5 of the bidirectional level conversion chip U115 is respectively connected to one end of the resistor R896 and one end of the resistor R895, pin 1 of the bidirectional level conversion chip U115 is connected to one end of the capacitor C872, and the other end of the capacitor C872 is grounded.

3. The core board based on the MT8395 processor according to claim 1, characterized in that, The RTC clock circuit includes: pin L13 of the power management chip U2H is respectively connected to one end of the capacitor C214 and one end of the resistor R58, the other end of the capacitor C214 is grounded, the other end of the resistor R58 is connected to one end of the capacitor C215, and the other end of the capacitor C215 is grounded.

4. The core board based on the MT8395 processor according to claim 1, characterized in that, The core board also includes a power conversion circuit, which includes: pin 20 of the buck converter chip U111 is respectively connected to pin 21 of the buck converter chip U111, one end of capacitor C824, one end of capacitor C818, one end of capacitor C817, one end of capacitor C816, one end of capacitor C815, one end of capacitor C829, and one end of resistor R1196; the other end of capacitor C824 is respectively connected to the other end of capacitor C818, the other end of capacitor C817, the other end of capacitor C816, the other end of capacitor C815, and the other end of capacitor C829 and grounded; pin 19 of the buck converter chip U111 is connected to one end of capacitor C1098 and one end of resistor R1194; capacitor C1098 is respectively connected to one end of capacitor C818, the other end of capacitor C817, the other end of capacitor C816, the other end of capacitor C815, and the other end of capacitor C829 and grounded; pin 19 of the buck converter chip U111 is connected to one end of capacitor C1098 and one end of resistor R1194; capacitor C1098 is respectively connected to one end of capacitor C818, the other end of capacitor C817, the other end of capacitor C816, the other end of capacitor C815, and the other end of capacitor C829; The other end of the resistor R1194 is connected to pin 9 of the buck converter chip U111, and pin 8 of the buck converter chip U111 is respectively connected to one end of the capacitor C1099, the other end of the resistor R1196, and one end of the resistor R1239. Pin 4 of the buck converter chip U111 is respectively connected to one end of the resistor R1198 and one end of the resistor R1197. The other end of the resistor R1198 is grounded, and pin 1 of the buck converter chip U111 is connected to one end of the capacitor C844. The other end of the capacitor C844 is respectively connected to one end of the inductor L73 and pin 20 of the buck converter chip U111. Pin 7 of the buck converter chip U111 is respectively connected to one end of the resistor R874 and one end of the resistor R875.

5. The core board based on the MT8395 processor according to claim 1, characterized in that, The core board also includes: an HDMI circuit, which includes: pin 1 of the MOSFET chip Q28 is connected to one end of the resistor R645, pin 2 of the MOSFET chip Q28 is connected to the other end of the resistor R645, pin 3 of the MOSFET chip Q28 is respectively connected to one end of the resistor R648, one end of the resistor R649, and the negative electrode of the diode D17, the positive electrode of the diode D17 is connected to one end of the resistor R643, the other end of the resistor R649 is connected to pin 2 of the protection chip ESD57, and pin 1 of the protection chip ESD57 is grounded.

6. The core board based on the MT8395 processor according to claim 1, characterized in that, The core board also includes: a power management circuit, wherein the power management circuit includes: pin J9 of the power management chip U5C is connected to pin K9 of the power management chip U5C and one end of the capacitor C250, and the other end of the capacitor C250 is connected to pin J11 of the power management chip U5C and pin K11 of the power management chip U5C, and pin J8 of the power management chip U5C is connected to pin K8 of the power management chip U5C and one end of the capacitor C259, and the other end of the capacitor C259 is connected to the power management chip U5C. Pin J6 of the power management chip U5C and pin K6 of the power management chip U5C are connected. Pin J10 of the power management chip U5C is respectively connected to pin K10 of the power management chip U5C and one end of the inductor PL16. The other end of the inductor PL16 is respectively connected to one end of capacitor C253 and one end of capacitor C254. Pin J7 of the power management chip U5C is respectively connected to pin K7 of the power management chip U5C and one end of the inductor PL17. The other end of the inductor PL17 is connected to one end of capacitor C260. The other end of capacitor C260 is grounded.

7. The core board based on the MT8395 processor according to claim 1, characterized in that, The core board also includes: an LP4X DRAM I / O interface voltage 0.75V circuit, and the LP4X DRAM I / O interface voltage 0.75V circuit includes: pin A1 of the wireless communication chip U6 is respectively connected to pin B1 of the wireless communication chip U6, pin C1 of the wireless communication chip U6, one end of capacitor C826, and one end of capacitor C825, pin E2 of the wireless communication chip U6 is respectively connected to one end of resistor R237 and one end of resistor R239, pin D3 of the wireless communication chip U6 is respectively connected to one end of resistor R243 and one end of resistor R241, pin D2 of the wireless communication chip U6 is connected to one end of resistor R245, pin A2 of the wireless communication chip U6 is respectively connected to pin B2 of the wireless communication chip U6 and one end of inductor L18, and the other end of inductor L18 is connected to one end of capacitor C823.

8. The core board based on the MT8395 processor according to claim 1, characterized in that: The core board also includes: a DRAM power supply voltage 1.8V circuit, which includes: pin C2 of the voltage regulating chip U7 is respectively connected to one end of the resistor R251 and one end of the capacitor C811, pin B2 of the voltage regulating chip U7 is connected to one end of the resistor R254, pin A2 of the voltage regulating chip U7 is respectively connected to one end of the resistor R255 and one end of the capacitor C813, and the other end of the capacitor C813 is grounded, pin B1 of the voltage regulating chip U7 is respectively connected to one end of the resistor R253, one end of the capacitor C426, and one end of the resistor R252, pin A1 of the voltage regulating chip U7 is respectively connected to the other end of the capacitor C426, the other end of the resistor R252, and one end of the capacitor C812, and the other end of the capacitor C812 is grounded.

9. The core board based on the MT8395 processor according to claim 1, characterized in that: The core board also includes: a UART circuit, wherein the UART circuit includes: pin 1 of the logic level converter chip U87 is respectively connected to one end of the resistor R760 and one end of the capacitor C357, the other end of the capacitor C357 is grounded, the other end of the resistor R760 is connected to pin 12 of the logic level converter chip U87, pin 11 of the logic level converter chip U87 is respectively connected to one end of the resistor R761, one end of the resistor R762, and one end of the capacitor C358, pin 10 of the logic level converter chip U87 is connected to the other end of the resistor R761, pin 9 of the logic level converter chip U87 is connected to the other end of the resistor R762, and the other end of the capacitor C358 is connected to pin 6 of the logic level converter chip U87 and grounded.

10. The core board based on the MT8395 processor according to any one of claims 1 to 9, characterized in that: The core board also includes: an eDP and DSI 0 two-in-one circuit, and the eDP and DSI 0 two-in-one circuit includes a bidirectional passive switch chip U99.

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