Image sensor supporting multiple resolutions

Abstract

The utility model provides an image sensor supporting multiple resolutions, and the image sensor comprises a plurality of pixel units which are arranged in an array, and each pixel unit at least comprises a first pixel part, a second pixel part, and a resolution regulation and control part. The first pixel part is connected with the second pixel part through the resolution regulation and control part, the first pixel part and the second pixel part are subjected to pixel merging through the resolution regulation and control part, and resolution regulation and control are achieved. According to the utility model, the problem that the expected noise performance cannot be achieved when the pixels with different resolutions are merged in the signal processing stage in the prior art is solved.

Description

Technical Field

[0001] The utility model relates to the technical field of image sensors, in particular to an image sensor supporting multiple resolutions. Background Art

[0002] As image sensor pixel sizes shrink, current image sensors can support a variety of pixel density outputs. For example, an image sensor with a maximum density of 200MP can now support 50MP / 12.5MP image outputs. By varying pixel density, a single sensor can support different lenses. To meet these requirements, image sensors are expected to exhibit consistent noise performance at all resolutions. However, existing techniques for merging pixels at different resolutions during signal processing fail to achieve these expectations. Therefore, reducing correlated noise is a pressing technical challenge for those skilled in the art.

[0003] It should be noted that the above technical background is merely for the purpose of providing a clear and complete description of the technical solutions of the present invention and to facilitate understanding by those skilled in the art. It should not be assumed that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present invention. Utility Model Content

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide an image sensor supporting multiple resolutions, so as to solve the problem that the expected noise performance cannot be achieved when pixels at different resolutions are combined in the existing signal processing stage.

[0005] To achieve the above-mentioned and other related objectives, the present invention provides an image sensor supporting multiple resolutions, comprising:

[0006] A plurality of pixel units arranged in an array, each pixel unit comprising at least a first pixel portion, a second pixel portion, and a resolution control portion, wherein:

[0007] The first pixel portion is connected to the second pixel portion via the resolution control portion, and the first pixel portion and the second pixel portion are pixel-merged by the resolution control portion to achieve resolution control.

[0008] Optionally, the first pixel portion includes a first photosensitive module, a first reset module, a first readout module, a first capacitance adjustment module and a first floating diffusion node, and the second pixel portion includes a second photosensitive module, a second reset module, a second readout module, a second capacitance adjustment module and a second floating diffusion node, the corresponding photosensitive module is connected to the corresponding floating diffusion node for converting the light signal into a corresponding charge signal, the corresponding reset module is connected to the corresponding floating diffusion node for at least resetting the corresponding floating diffusion node, the corresponding readout module is connected to the corresponding floating diffusion node for at least reading out the corresponding charge signal, and the corresponding capacitance adjustment module is coupled to the corresponding floating diffusion node for adjusting the storage capacity of the corresponding pixel portion; wherein the resolution control portion is connected between the first capacitance adjustment module and the second capacitance adjustment module.

[0009] Optionally, the first capacitance adjustment module and the second capacitance adjustment module are gain conversion modules, which are connected between the corresponding reset module and the corresponding floating diffusion node or connected to the corresponding floating diffusion node, and adjust the storage capacity of the corresponding pixel part by switching different conversion gains; or, the first capacitance adjustment module and the second capacitance adjustment module are charge overflow modules, which are connected between the corresponding reset module and the corresponding floating diffusion node or connected to the corresponding floating diffusion node, and adjust the storage capacity of the corresponding pixel part by receiving the charge signal overflowed from the corresponding photosensitive module.

[0010] Optionally, when the first capacitance adjustment module and the second capacitance adjustment module are gain conversion modules: the resolution control unit includes at least one first switching tube, the control end of the first switching tube receives a first control signal, the first end of the first switching tube is connected to the connection node between the first capacitance adjustment module and the first reset module or is connected to the end of the first capacitance adjustment module away from the first floating diffusion node, and the second end of the first switching tube is connected to the connection node between the second capacitance adjustment module and the second reset module or is connected to the end of the second capacitance adjustment module away from the second floating diffusion node; and / or, at least one reset module in each pixel unit connected to the same resolution control unit is retained, and the others are omitted.

[0011] Optionally, when the number of the first switching tubes is greater than one, the first switching tubes are connected in series.

[0012] Optionally, when the first capacitance adjustment module and the second capacitance adjustment module are gain conversion modules: the first pixel portion also includes a first charge overflow module, and the second pixel portion also includes a second charge overflow module, wherein the corresponding charge overflow module is connected to the corresponding floating diffusion node for receiving the corresponding charge signal overflowed from the corresponding photosensitive module.

[0013] Optionally, when the first capacitance adjustment module and the second capacitance adjustment module are charge overflow modules:

[0014] The resolution control unit includes a shared overflow capacitor, a first end of the shared overflow capacitor is connected to a connection node between the first capacitance adjustment module and the first reset module and a connection node between the second capacitance adjustment module and the second reset module, or is connected to an end of the first capacitance adjustment module away from the first floating diffusion node and an end of the second capacitance adjustment module away from the second floating diffusion node, and a second end of the shared overflow capacitor is connected to a first potential; or the resolution control unit includes a first overflow capacitor, a second overflow capacitor, and at least one second switch transistor, a first end of the first overflow capacitor is connected to a connection node between the first capacitance adjustment module and the first reset module or to an end of the first capacitance adjustment module away from the first floating diffusion node, a second end of the first overflow capacitor is connected to a second potential, a first end of the second overflow capacitor is connected to a connection node between the second capacitance adjustment module and the second reset module or to an end of the second capacitance adjustment module away from the second floating diffusion node, a second end of the second overflow capacitor is connected to a third potential, a control end of the second switch transistor receives a second control signal, a first end of the second switch transistor is connected to a first end of the first overflow capacitor, and a second end of the second switch transistor is connected to a first end of the second overflow capacitor;

[0015] And / or, at least one reset module in each pixel unit connected to the same resolution control unit is retained, and the others are omitted.

[0016] Optionally, the resolution control unit further includes a fast reset tube, the control end of the fast reset tube receives a fast reset control signal, the first end of the fast reset tube is connected to the power supply potential, and the second end of the fast reset tube is connected to the second end of the corresponding overflow capacitor.

[0017] Optionally, the first pixel portion further includes a first gain conversion module, and the second pixel portion further includes a second gain conversion module, wherein, when the first capacitance adjustment module and the second capacitance adjustment module are connected between the corresponding reset module and the corresponding floating diffusion node, the corresponding gain conversion module is connected to the corresponding floating diffusion node; when the first capacitance adjustment module and the second capacitance adjustment module are connected to the corresponding floating diffusion node, the corresponding gain conversion module is connected between the corresponding reset module and the corresponding floating diffusion node or to the corresponding floating diffusion node, for switching different conversion gains.

[0018] Optionally, when the corresponding gain conversion module is connected to the corresponding floating diffusion node, the first gain conversion module and the second gain conversion module each include a gain transistor and a gain capacitor, a control terminal of the gain transistor receives a gain control signal, a first terminal of the gain transistor is connected to the corresponding floating diffusion node, and a second terminal of the gain transistor is connected to a fourth potential via the gain capacitor; wherein, in at least two pixel units in the same column, the second terminals of the gain transistors in the first pixel portions are connected to each other, and the second terminals of the gain transistors in the second pixel portions are connected to each other;

[0019] When the corresponding gain conversion module is connected between the corresponding reset module and the corresponding floating diffusion node, the first gain conversion module and the second gain conversion module each include a gain transistor, a control end of the gain transistor receives a gain control signal, a first end of the gain transistor is connected to the corresponding reset module, and a second end of the gain transistor is connected to the corresponding floating diffusion node; wherein, in at least two pixel units in the same column, the first ends of the gain transistors in the first pixel portions are connected to each other, and the first ends of the gain transistors in the second pixel portions are connected to each other.

[0020] As described above, the image sensor supporting multiple resolutions of the present invention can reduce signal-correlated noise through signal merging operations in the charge domain within the pixel, so that the image sensor has approximately the same noise performance at each resolution, which is beneficial to improving image quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 Shown is a structural schematic diagram of a pixel unit in the first embodiment of the present invention.

[0022] Figure 2 Shown is another structural schematic diagram of the pixel unit in the first embodiment of the present invention.

[0023] Figure 3 Shown is another structural schematic diagram of the pixel unit in the first embodiment of the present utility model.

[0024] Figure 4 Shown is another structural schematic diagram of the pixel unit in the first embodiment of the present invention.

[0025] Figure 5 Shown is a structural schematic diagram of a pixel unit in the second embodiment of the present utility model.

[0026] Figure 6 Shown is another structural schematic diagram of the pixel unit in the second embodiment of the present utility model.

[0027] Figure 7Shown is another structural schematic diagram of the pixel unit in the second embodiment of the present utility model.

[0028] Figure 8 Shown is another structural schematic diagram of the pixel unit in the second embodiment of the present utility model.

[0029] Figure 9 It shows a schematic structural diagram of node sharing among multiple pixel units in the same column in the second embodiment of the present invention.

[0030] Figure 10 Shown is a structural schematic diagram of a pixel unit in the third embodiment of the present utility model.

[0031] Figure 11 Shown is another structural schematic diagram of the pixel unit in the third embodiment of the present invention.

[0032] Figure 12 Shown is another structural schematic diagram of the pixel unit in the third embodiment of the present utility model.

[0033] Figure 13 Shown is another structural schematic diagram of the pixel unit in the third embodiment of the present utility model.

[0034] Figure 14 Shown is a schematic structural diagram of node sharing among multiple pixel units in the same column in the third embodiment of the present invention.

[0035] Component number description

[0036] 100-pixel unit

[0037] 110 first pixel portion

[0038] 111 First photosensitive module

[0039] 112 First reset module

[0040] 113 First readout module

[0041] 114 First Capacity Adjustment Module

[0042] 115 First Charge Overflow Module

[0043] 116 First gain conversion module

[0044] 120 second pixel portion

[0045] 121 Second photosensitive module

[0046] 122 Second reset module

[0047] 123 Second readout module

[0048] 124 Second capacity adjustment module

[0049] 125 Second charge overflow module

[0050] 126 Second gain conversion module

[0051] 130 Resolution Control Unit DETAILED DESCRIPTION

[0052] The following describes the implementation of the present invention through specific examples. Those skilled in the art can easily understand the other advantages and functions of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments. The details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. The "coupling" mentioned in this application can be a direct connection or a connection through other transistors. It can be understood according to the specific solution, which is known to those skilled in the art.

[0053] See also Figures 1 to 14 It should be noted that the illustrations provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the form, quantity, and proportion of each component may be arbitrarily changed, and the component layout may also be more complex.

[0054] Example 1

[0055] like Figures 1-4 As shown, this embodiment provides an image sensor supporting multiple resolutions, including a plurality of pixel units 100 arranged in an array; wherein the pixel unit 100 at least includes a first pixel portion 110 , a second pixel portion 120 and a resolution control portion 130 .

[0056] The first pixel portion 110 is connected to the second pixel portion 120 via the resolution control portion 130. The first pixel portion 110 and the second pixel portion 120 are combined by the resolution control portion 130 to achieve resolution control. This embodiment facilitates reducing noise performance at each resolution and improving image quality at each resolution by combining pixels in the charge domain. It should be noted that the pixel unit 100 may also include multiple pixel portions, such as a third pixel portion, a fourth pixel portion, etc., the number of which is set as required. When there are multiple pixel portions, the pixel portions are connected to each other through the resolution control portion 130 for signal merging.

[0057] As an example, the first pixel portion 110 includes a first photosensitive module 111, a first reset module 112, a first readout module 113, a first capacitance adjustment module 114 and a first floating diffusion node FD1. Figure 1 As shown, the first photosensitive module 111 is connected to the first floating diffusion node FD1 and is configured to convert a light signal into a first charge signal. The first reset module 112 is connected to the first floating diffusion node FD1 and is configured to at least reset the first floating diffusion node FD1. The first readout module 113 is connected to the first floating diffusion node FD1 and is configured to at least read out the first charge signal. The first capacitance adjustment module 114 is coupled to the first floating diffusion node FD1. For example, the first capacitance adjustment module 114 is connected between the first reset module 112 and the first floating diffusion node FD1. Alternatively, the first capacitance adjustment module 114 is connected to the first floating diffusion node FD1. In this case, the first capacitance adjustment module 114 and the first reset module 112 are each connected to the first floating diffusion node FD1. The first capacitance adjustment module 114 is configured to adjust the storage capacity of the first pixel portion 110. In a specific example, the first capacitance adjustment module 114 is a gain conversion module that adjusts the storage capacity of the first pixel portion 110 by switching between different conversion gains (e.g., a low conversion gain and a high conversion gain). Furthermore, the first pixel portion 110 further includes a first charge overflow module 115 connected to the first floating diffusion node FD1 for receiving a first charge signal (ie, a first overflow charge signal) overflowed from the first photosensitive module 111. Figure 2-Figure 4 As shown; at this time, the first charge signal includes a first potential well charge signal and a first overflow charge signal, wherein the first potential well charge signal is stored in the first photosensitive module 111, and the first overflow charge signal is stored in the first charge overflow module 115.

[0058] The second pixel portion 120 includes a second photosensitive module 121, a second reset module 122, a second readout module 123, a second capacitance adjustment module 124 and a second floating diffusion node FD2. Figure 1As shown, the second photosensitive module 121 is connected to the second floating diffusion node FD2 for converting the light signal into a second charge signal; the second reset module 122 is connected to the second floating diffusion node FD2 for at least resetting the second floating diffusion node FD2; the second readout module 123 is connected to the second floating diffusion node FD2 for at least reading out the second charge signal; and the second capacitance adjustment module 124 is coupled to the second floating diffusion node FD2. For example, the second capacitance adjustment module 124 is connected between the second reset module 122 and the second floating diffusion node FD2, or the second capacitance adjustment module 124 is connected to the second floating diffusion node FD2. In this case, the second capacitance adjustment module 124 and the reset module 122 are each connected to the second floating diffusion node FD2. The second capacitance adjustment module 124 is used to adjust the storage capacity of the second pixel portion 120. In a specific example, the second capacitance adjustment module 124 is a gain conversion module that adjusts the storage capacity of the second pixel portion 120 by switching between different conversion gains (for example, a low conversion gain and a high conversion gain). Furthermore, the second pixel portion 120 further includes a second charge overflow module 125 connected to the second floating diffusion node FD2 for receiving a second charge signal (ie, a second overflow charge signal) overflowed from the second photosensitive module 121. Figure 2-Figure 4 As shown; at this time, the second charge signal includes a second potential well charge signal and a second overflow charge signal, wherein the second potential well charge signal is stored in the second photosensitive module 121, and the second overflow charge signal is stored in the second charge overflow module 125.

[0059] Specifically, the first photosensitive module 111 and the second photosensitive module 121 have the same circuit structure, including at least one transfer transistor and at least one photosensitive element. In an optional solution, eight transfer transistors M11 to M18 and eight photosensitive elements PD1 to PD8 are included. Of course, other numbers of transfer transistors and photosensitive elements are also feasible. The transfer transistors correspond to the photosensitive elements one by one, and the control end of the transfer transistor receives a corresponding transfer control signal. The first end of the transfer transistor is connected to the corresponding floating diffusion node, and the second end of the transfer transistor is connected to a reference potential (for example, a reference ground) via the photosensitive element. Figures 1-4 In practical applications, the resolution of the image sensor is adjusted by adjusting the number of photosensitive elements involved in the calculation.

[0060] The first reset module 112 and the second reset module 122 have the same circuit structure, including a reset transistor M2; wherein the control terminal of the reset transistor M2 receives the reset control signal RST, the first terminal of the reset transistor M2 is connected to the power supply potential, and the second terminal of the reset transistor M2 is connected to the corresponding floating diffusion node, such as Figures 1-4 shown.

[0061] The first readout module 113 and the second readout module 123 have the same circuit structure, including a source follower transistor M3 and a selection transistor M4; wherein the control end of the source follower transistor M3 is connected to the corresponding floating diffusion node, the first end of the source follower transistor M3 is connected to the power supply potential, the second end of the source follower transistor M3 is connected to the first end of the selection transistor M4, the control end of the selection transistor M4 receives the selection control signal SEL, and the second end of the selection transistor M4 is connected to the column line, such as Figures 1-4 shown.

[0062] The first capacitance adjustment module 114 and the second capacitance adjustment module 124 have the same circuit structure, including a gain transistor M5. When the corresponding capacitance adjustment module is connected between the corresponding reset module and the corresponding floating diffusion node, the control terminal of the gain transistor M5 receives the gain control signal DCG, the first terminal of the gain transistor M5 is connected to the corresponding reset module, and the second terminal of the gain transistor M5 is connected to the corresponding floating diffusion node. Figure 1-Figure 3 When the corresponding capacitance adjustment module is connected to the corresponding floating diffusion node, the control terminal of the gain transistor M5 receives the gain control signal DCG, the first terminal of the gain transistor M5 is connected to the resolution control unit 130, and the second terminal of the gain transistor M5 is connected to the corresponding floating diffusion node, as shown. Figure 4 shown.

[0063] The first charge overflow module 115 and the second charge overflow module 125 have the same circuit structure, including an overflow transistor M6 and an overflow capacitor Cof; wherein the control terminal of the overflow transistor M6 receives the overflow control signal OF, the first terminal of the overflow transistor M6 is connected to the corresponding floating diffusion node, and the second terminal of the overflow transistor M6 is connected to a fifth potential (e.g., a variable potential) via the overflow capacitor Cof. Figure 2-Figure 4 As shown, of course, in other implementations, the first charge overflow module 115 and the second charge overflow module 125 may not exist, such as Figure 1 shown.

[0064] In the above example, each pixel portion connected to the same resolution control portion 130 includes its own reset module. For example, the first pixel portion 110 includes a first reset module 112, and the second pixel portion 120 includes a second reset module 122. In actual applications, each pixel portion connected to the same resolution control portion 130 may not include its own reset module, as long as there is at least one reset module. In this case, among the pixel portions connected to the same resolution control portion 130, at least one reset module is retained, and the other reset modules are omitted. For example, the reset module of any one of the first pixel portion 110 and the second pixel portion 120 is retained, and the reset module of the other is omitted.

[0065] The resolution control unit 130 is connected between the first capacitance adjustment module 114 and the second capacitance adjustment module 124, for example, between the connection node between the first capacitance adjustment module 114 and the first reset module 112 and the connection node between the second capacitance adjustment module 124 and the second reset module 122, or between an end of the first capacitance adjustment module 114 away from the first floating diffusion point FD1 and an end of the second capacitance adjustment module 124 away from the second floating diffusion point FD2. Specifically, the resolution control unit 130 includes at least one first switch transistor M7. In one embodiment, the control end of the first switch transistor M7 receives the first control signal CTL1, the first end of the first switch transistor M7 is connected to the connection node between the first capacitance adjustment module 114 and the first reset module 112, and the second end of the first switch transistor M7 is connected to the connection node between the second capacitance adjustment module 124 and the second reset module 122. Figure 1-Figure 3 As shown; in another embodiment, the control end of the first switch tube M7 receives the first control signal CTL1, the first end of the first switch tube M7 is connected to the end of the first capacitance adjustment module 114 away from the first floating diffusion node FD1, and the second end of the first switch tube M7 is connected to the end of the second capacitance adjustment module 124 away from the second floating diffusion node FD2, as shown Figure 4 In this embodiment, when the gain transistor M5 is turned on, by controlling the first switch M7 to be turned on, the first pixel portion 110 and the second pixel portion 120 can be pixel-merged. That is, the first pixel portion 110 and the second pixel portion 120 are pixel-merged in a manner of sharing an LCG (low conversion gain) node through the resolution control portion 130. Of course, by controlling the first switch M7 to be turned off, the first pixel portion 110 and the second pixel portion 120 can also operate independently.

[0066] In practical applications, when the number of the first switch tubes M7 is greater than one, the first switch tubes M7 are connected in series, such as Figure 3 As shown; at this time, the first control signal CTL1 received by the control end of each first switch tube M7 is usually partially the same and partially different. In this way, when the first pixel portion 110 and the second pixel portion 120 operate independently, by controlling the on / off status of each first switch tube M7, the storage capacity of the first pixel portion 110 and the second pixel portion 120 can be adjusted when the gain transistor M5 is turned on, thereby obtaining more conversion gain.

[0067] It should be noted that, for the pixel unit 100 of this embodiment, in one implementation, each transistor is an NMOS tube, in which case the control end is the gate end, the first end is the drain end, the second end is the source end, and the photosensitive element is a photodiode; of course, in other implementations, it is also feasible for each transistor to be a PMOS tube, and it is also feasible for the photosensitive element to be a grating or a photoconductor.

[0068] In addition, the image sensor of this embodiment includes, in addition to the circuit structure described above, an optical structure, wherein the optical structure is located on the upper surface or the lower surface of the circuit structure; in a specific example, the optical structure includes a plurality of color filter units, each color filter unit corresponding one-to-one to each pixel unit 100, by allowing visible light of a specific color to pass through, for example, allowing red light, filtered light or blue light to pass through, so as to form a Bayer color array.

[0069] Accordingly, this embodiment also provides an operating method for an image sensor supporting multiple resolutions, which includes at least a pixel merging mode and further includes a pixel independent mode; wherein the image sensor is implemented using the structure described above.

[0070] In pixel binning mode, the resolution control unit 130 performs pixel binning on the first pixel unit 110 and the second pixel unit 120. At this time, the first switch M7 in the resolution control unit 130 is turned on, allowing the first pixel unit 110 and the second pixel unit 120 to work together to obtain pixel signals. The pixel binning mode includes a reset phase, an exposure phase, and a quantization readout phase. This mode includes at least one step of performing pixel binning and readout on the first pixel unit 110 and the second pixel unit 120 by the resolution control unit 130 to obtain image information in the binning mode. Of course, it is understood that this mode operation may also include a process of separately reading the signals from the first pixel unit 110 and the second pixel unit 120.

[0071] During the reset stage, the first photosensitive module 111, the first floating diffusion node FD1 and the first capacitance adjustment module 114 are reset through the first reset module 112, and the second photosensitive module 121, the second floating diffusion node FD2 and the second capacitance adjustment module 124 are reset through the second reset module 122; further, the first charge overflow module 115 is reset through the first reset module 112, and the second charge overflow module 125 is reset through the second reset module 122.

[0072] For example, the transmission transistors in the first photosensitive module 111 and the second photosensitive module 121, the gain transistor M5 in the first capacitance adjustment module 114 and the second capacitance adjustment module 124, and the overflow transistor M6 in the first charge overflow module 115 and the second charge overflow module 125 are controlled to be turned on, and the reset transistor M2 in the first reset module 112 and the second reset module 122 is controlled to be turned on, so as to clear the charge of the first photosensitive module 111, the first floating diffusion node FD1, the first capacitance adjustment module 114, the first charge overflow module 115, the second photosensitive module 121, the second floating diffusion node FD2, the second capacitance adjustment module 124 and the second charge overflow module 125; then, the transmission transistors in the first photosensitive module 111 and the second photosensitive module 121, the gain transistor M5 in the first capacitance adjustment module 114 and the second capacitance adjustment module 124, and the reset transistor M2 in the first reset module 112 and the second reset module 122 are controlled to be turned off.

[0073] During the exposure stage, the first potential well charge signal is stored by the first photosensitive module 111, and the second potential well charge signal is stored by the second photosensitive module 121; further, the first overflow charge signal is stored by the first charge overflow module 115, and the second overflow charge signal is stored by the second charge overflow module 125.

[0074] For example, when the amount of charge sensed by the first photosensitive module 111 has not reached the overflow state, the first charge signal only includes the first potential well charge signal, and the first overflow charge signal is zero. At this time, the first potential well charge signal is stored in the first photosensitive module 111, and no first overflow charge signal is stored in the first charge overflow module 115; when the amount of charge sensed by the first photosensitive module 111 reaches the overflow state, the first charge signal includes the first potential well charge signal and the first overflow charge signal. At this time, the first potential well charge signal is stored in the first photosensitive module 111, and the first overflow charge signal is stored in the first charge overflow module 115; thereafter, the overflow transistor M6 in the first charge overflow module 115 is controlled to be turned off. Similarly, when the charge amount sensed by the second photosensitive module 121 has not reached an overflow state, the second charge signal includes only the second potential well charge signal, and the second overflow charge signal is zero. In this case, the second potential well charge signal is stored in the second photosensitive module 121, and no second overflow charge signal is stored in the second charge overflow module 125. When the charge amount sensed by the second photosensitive module 121 reaches an overflow state, the second charge signal includes the second potential well charge signal and the second overflow charge signal. In this case, the second potential well charge signal is stored in the second photosensitive module 121, and the second overflow charge signal is stored in the second charge overflow module 125. Thereafter, the overflow transistor M6 in the second charge overflow module 125 is controlled to be turned off. It should be noted that at the end of the reset phase, the overflow transistor M6 in the first charge overflow module 115 and the second charge overflow module 125 is not turned off to facilitate charge overflow during the exposure phase.

[0075] The quantization readout stage includes quantization readout of pixel signals under low conversion gain, quantization readout of pixel signals under high conversion gain, and further, quantization readout of pixel signals under charge overflow.

[0076] Among them, under low conversion gain, the first pixel portion 110 and the second pixel portion 120 are pixel-merged through the resolution control portion 130, and the first potential well charge signal and the second potential well charge signal are merged and then correlated double sampling is performed; it should be noted that the low gain in this application refers to the low gain corresponding to the larger capacitance relative to the floating diffusion node, and the specific low gain value can be determined based on actual operation; under high conversion gain, the first potential well charge signal and the second potential well charge signal are respectively correlated double sampled; under charge overflow, the first pixel portion 110 and the second pixel portion 120 are pixel-merged through the resolution control portion 130, and the first overflow charge signal and the second overflow charge signal are merged and then correlated double sampling is performed in a non-true sense, or the first overflow charge signal and the second overflow charge signal are respectively correlated double sampled in a non-true sense; wherein, in the case of charge overflow, the use of merged readout or independent readout can be achieved through the control of the resolution control portion.

[0077] Here is a specific operation method:

[0078] The gain transistor M5 in the first capacitance adjustment module 114 and the second capacitance adjustment module 124 is controlled to be turned on. Since the first switch tube M7 in the resolution control unit 130 is in the on state, the first pixel unit 110 and the second pixel unit 120 enter a low conversion gain and achieve pixel merging. Then, the selection transistor M4 in the first readout module 113 or the second readout module 123 is controlled to be turned on and then turned off. The first potential well reset signal and the second potential well reset signal are combined under the low conversion gain and then quantized and read out.

[0079] Afterwards, the gain transistors M5 in the first capacitance adjustment module 114 and the second capacitance adjustment module 124 are controlled to be turned off, so that the first pixel portion 110 and the second pixel portion 120 enter a high conversion gain and pixel merging is temporarily cut off. The selection transistors M4 in the first readout module 113 and the second readout module 123 are controlled to be turned on, and the first potential well reset signal and the second potential well reset signal are respectively quantized and read out at a high conversion gain. Then, the transmission transistors in the first photosensitive module 111 and the second photosensitive module 121 are controlled to be turned on and then turned off, and the first potential well charge signal and the second potential well charge signal are respectively quantized and read out at a high conversion gain through the first readout module 113 and the second readout module 123, thereby achieving correlated double sampling of the first potential well charge signal and the second potential well charge signal at a high conversion gain. After completion, the selection transistors M4 in the first readout module 113 and the second readout module 123 are controlled to be turned off.

[0080] Afterwards, the gain transistor M5 in the first capacitance adjustment module 114 and the second capacitance adjustment module 124 is controlled to be turned on again, so that the first pixel portion 110 and the second pixel portion 120 enter a low conversion gain and pixel merging is re-implemented. Then, the transmission transistors in the first photosensitive module 111 and the second photosensitive module 121 are controlled to be turned on and then turned off, and the selection transistor M4 in the first readout module 113 or the second readout module 123 is controlled to be turned on. The first potential well charge signal and the second potential well charge signal are merged at a low conversion gain and then quantized and read out, thereby realizing correlated double sampling after the first potential well charge signal and the second potential well charge signal are merged at a low conversion gain.

[0081] Finally, the overflow transistor M6 in the first charge overflow module 115 and the second charge overflow module 125 is controlled to be turned on, and each transmission transistor in the first photosensitive module 111 and the second photosensitive module 121 is controlled to be turned on and then turned off, and the first overflow charge signal and the second overflow charge signal are merged and quantized and read out through the first readout module 113 or the second readout module 123; then the reset transistor M2 in the first reset module 112 and the second reset module 122 is controlled to be turned on and then turned off, the first charge overflow module 115 and the second charge overflow module 125 are reset, and the first overflow reset signal and the second overflow reset signal are merged and quantized and read out through the first readout module 113 or the second readout module 123, thereby realizing non-true correlated double sampling after the first overflow charge signal and the second overflow charge signal are merged under charge overflow.

[0082] It should be noted that in the pixel merging mode, the first switch tube M7 in the resolution control unit 130 is always in the on state. Of course, it is also feasible that the first switch tube M7 is in the off state during the reset stage and the exposure stage and is only in the on state during the quantization readout stage. In addition, the selection transistor M4 in the first readout module 113 and the second readout module 123 can also be controlled differently, as long as the relevant signals are read out normally.

[0083] In pixel-independent mode, the resolution control unit 130 disconnects the first pixel unit 110 and the second pixel unit 120. At this point, the first switch M7 in the resolution control unit 130 is turned off, allowing the first pixel unit 110 and the second pixel unit 120 to function independently to acquire pixel signals. The pixel-independent mode includes a reset phase, an exposure phase, and a quantized readout phase. In this mode, at least one first switch M7 is turned off to enable signal readout between pixel units, obtaining high-resolution pixel information. Of course, if there are multiple first switches M7, the gain of the corresponding pixel units can be adjusted by using the other non-disabled first switches M7, which can facilitate gain optimization.

[0084] Specifically, the quantization readout stage includes quantization readout of pixel signals at low conversion gain and high conversion gain, and further includes quantization readout of pixel signals under charge overflow. Under low conversion gain, correlated double sampling is performed on the first potential well charge signal and the second potential well charge signal; under high conversion gain, correlated double sampling is performed on the first potential well charge signal and the second potential well charge signal; and under charge overflow, non-true correlated double sampling is performed on the first overflow charge signal and the second overflow charge signal.

[0085] It should be noted that when the first pixel portion 110 and the second pixel portion 120 operate independently, the control of the two is the same; and in the pixel independent mode, the on-off control of each transistor in the first pixel portion 110 and the second pixel portion 120 at each stage is roughly the same as the on-off control of each transistor in the first pixel portion 110 and the second pixel portion 120 at each stage in the pixel merging mode, which will not be repeated here.

[0086] Example 2

[0087] like Figures 5 to 8 As shown, this embodiment provides an image sensor supporting multiple resolutions, which differs from the first embodiment in that the first capacitance adjustment module 114 in the first pixel portion 110 and the second capacitance adjustment module 124 in the second pixel portion 120 are changed from gain conversion modules to charge overflow modules, the first pixel portion 110 further includes a first gain conversion module 116, and the second pixel portion 120 further includes a second gain conversion module 126, and the circuit structure of the resolution control portion 130 is different.

[0088] The first pixel portion 110 includes a first photosensitive module 111, a first reset module 112, a first readout module 113, a first capacitance adjustment module 114, and a first floating diffusion node FD1. The first capacitance adjustment module 114 is a charge overflow module connected between the first reset module 112 and the first floating diffusion node FD1. It adjusts the storage capacity of the first pixel portion 110 by receiving a first charge signal overflowing from the first photosensitive module 111. In this case, the first charge signal includes a first potential well charge signal and a first overflow charge signal. The first potential well charge signal is stored in the first photosensitive module 111, and the first overflow charge signal is stored in the first capacitance adjustment module 114. Furthermore, the first pixel portion 110 also includes a first gain conversion module 116 connected to the first floating diffusion node FD1 for switching between different conversion gains (e.g., low conversion gain and high conversion gain).

[0089] The second pixel portion 120 includes a second photosensitive module 121, a second reset module 122, a second readout module 123, a second capacitance adjustment module 124, and a second floating diffusion node FD2. The second capacitance adjustment module 124 is a charge overflow module connected between the second reset module 122 and the second floating diffusion node FD2. It adjusts the storage capacity of the second pixel portion 120 by receiving a second charge signal overflowing from the second photosensitive module 121. In this case, the second charge signal includes a second potential well charge signal and a second overflow charge signal. The second potential well charge signal is stored in the second photosensitive module 121, and the second overflow charge signal is stored in the second capacitance adjustment module 124. Furthermore, the second pixel portion 120 also includes a second gain conversion module 126 connected to the second floating diffusion node FD2 for switching between different conversion gains (e.g., low conversion gain and high conversion gain).

[0090] Specifically, the first capacitance adjustment module 114 and the second capacitance adjustment module 124 have the same circuit structure, including an overflow transistor M6; wherein the control end of the overflow transistor M6 receives the overflow control signal OF, the first end of the overflow transistor M6 is connected to the corresponding reset module, and the second end of the overflow transistor M6 is connected to the corresponding floating diffusion node.

[0091] The first gain conversion module 116 and the second gain conversion module 126 have the same circuit structure, including a gain transistor M5 and a gain capacitor Cdcg; wherein the control terminal of the gain transistor M5 receives the gain control signal DCG, the first terminal of the gain transistor M5 is connected to the corresponding floating diffusion node, and the second terminal of the gain transistor M5 is connected to a fourth potential V4 (e.g., a variable potential) via the gain capacitor Cdcg.

[0092] In addition, the first photosensitive module 111, the first reset module 112 and the first readout module 113 in the first pixel unit 110 and the second photosensitive module 121, the second reset module 122 and the second readout module 123 in the second pixel unit 120 are the same as those in the first embodiment and will not be repeated here.

[0093] In the above example, each pixel portion connected to the same resolution control portion 130 includes its own reset module. For example, the first pixel portion 110 includes a first reset module 112, and the second pixel portion 120 includes a second reset module 122. In actual applications, each pixel portion connected to the same resolution control portion 130 may not include its own reset module, as long as there is at least one reset module. In this case, among the pixel portions connected to the same resolution control portion 130, at least one reset module is retained, and the other reset modules are omitted. For example, the reset module of any one of the first pixel portion 110 and the second pixel portion 120 is retained, and the reset module of the other is omitted.

[0094] The resolution control unit 130 is connected between the first capacitance adjustment module 114 and the second capacitance adjustment module 124 and has the following different circuit structures.

[0095] In one embodiment, Figure 5As shown, the resolution control unit 130 includes a shared overflow capacitor Cof; wherein a first end of the shared overflow capacitor Cof is connected to a connection node between the first capacitance adjustment module 114 and the first reset module 112 and to a connection node between the second capacitance adjustment module 124 and the second reset module 122, and a second end of the shared overflow capacitor Cof is connected to a first potential V1 (e.g., a variable potential). In this embodiment, when the overflow transistor M6 is turned on, pixel merging of the first pixel unit 110 and the second pixel unit 120 can be achieved based on the shared overflow capacitor Cof. That is, the first pixel unit 110 and the second pixel unit 120 are pixel-merged by sharing a single overflow capacitor node through the resolution control unit 130.

[0096] In another embodiment, Figure 6 As shown, the resolution control unit 130 includes a first overflow capacitor Cof1, a second overflow capacitor Cof2 and at least one second switch tube M8; wherein, the first end of the first overflow capacitor Cof1 is connected to the connection node between the first capacitance adjustment module 114 and the first reset module 112, the second end of the first overflow capacitor Cof1 is connected to the second potential V2 (for example, a variable potential), the first end of the second overflow capacitor Cof2 is connected to the connection node between the second capacitance adjustment module 124 and the second reset module 122, the second end of the second overflow capacitor Cof2 is connected to the third potential V3 (for example, a variable potential), the control end of the second switch tube M8 receives the second control signal CTL2, the first end of the second switch tube M8 is connected to the first end of the first overflow capacitor Cof1, and the second end of the second switch tube M8 is connected to the first end of the second overflow capacitor Cof2. In this embodiment, when the overflow transistor M6 is turned on, the first pixel portion 110 and the second pixel portion 120 can be pixel-merged by controlling the second switch tube M8 to be turned on. Of course, by controlling the second switch tube M8 to be turned off, the first pixel portion 110 and the second pixel portion 120 can also operate independently. Through the design of the second switch tube M8, the first pixel portion 110 and the second pixel portion 120 can be configured with different overflow capacitors.

[0097] In practical applications, the number of the second switch tubes M8 can be one or more than one; when the number of the second switch tubes M8 is more than one, the second switch tubes M8 are connected in series. Figure 2 In the embodiment of the present invention, the first switch tube M7 is connected in a manner as shown in FIG. 1 ; at this time, the second control signal CTL2 received by the control terminal of each second switch tube M8 is usually partially the same and partially different. In this way, when the first pixel portion 110 and the second pixel portion 120 operate independently, by controlling the on / off status of each second switch tube M8, the storage capacity of the first pixel portion 110 and the second pixel portion 120 can be adjusted when the overflow transistor M6 is turned on, thereby obtaining more conversion gain.

[0098] Further, such as Figure 7 As shown, the resolution control unit 130 also includes a fast reset transistor M9; wherein, when the resolution control unit 130 includes a shared overflow capacitor Cof, the control end of the fast reset transistor M9 receives a fast reset control signal OF_RST, the first end of the fast reset transistor M9 is connected to the power supply potential VDD, and the second end of the fast reset transistor M9 is connected to the second end of the shared overflow capacitor Cof. In this case, the second end of the shared overflow capacitor Cof is no longer connected to the first potential V1; when the resolution control unit 130 includes a first overflow capacitor Cof1, a second overflow capacitor Cof2, and at least one second switch transistor M8, the control end of the fast reset transistor M9 receives a fast reset control signal OF_RST, the first end of the fast reset transistor M9 is connected to the power supply potential VDD, and the second end of the fast reset transistor M9 is connected to the second end of the first overflow capacitor Cof1 and the second end of the second overflow capacitor Cof2. In this case, the second end of the first overflow capacitor Cof1 is no longer connected to the second potential V2, and the second end of the second overflow capacitor Cof2 is no longer connected to the third potential V3. Due to the design of the fast reset transistor M9, when resetting the corresponding overflow capacitor, a fast reset can be achieved by controlling the fast reset transistor M9 to turn on. In addition, when the fast reset transistor M9 is present, the first reset module 112 or the second reset module 122 can be omitted. Figure 8 As shown in FIG, the second reset module 122 is omitted.

[0099] Alternatively, as Figure 9 As shown, for the image sensor of this embodiment, in at least two pixel units 100 in the same column, the second ends of the gain transistors M5 in the first pixel portions 110 are connected to each other, and the second ends of the gain transistors M5 in the second pixel portions 120 are connected to each other. In this way, the pixel units 100 can share gain capacitance. For example, the low-gain ends of two pixel portions in adjacent rows are shared, and the gain node of the required row can be borrowed during readout.

[0100] Accordingly, this embodiment also provides an operating method for an image sensor supporting multiple resolutions, which includes at least a pixel merging mode; wherein, if the image sensor adopts Figure 5 、 Figure 7 or Figure 8 The structure shown in the figure, the operation method only includes the pixel merging mode; if the image sensor adopts Figure 6 As shown in the structure, the operation method may include not only the pixel merging mode but also the pixel independent mode.

[0101] Regarding the pixel merging mode: the first pixel unit 110 and the second pixel unit 120 are pixel-merged by the resolution control unit 130, so that the first pixel unit 110 and the second pixel unit 120 work together to obtain pixel signals; wherein, the pixel merging mode includes a reset stage, an exposure stage and a quantization readout stage. In this mode, at least one step of performing pixel merging and reading out the first pixel unit 110 and the second pixel unit 120 by the resolution control unit 130 is included to obtain image information in the merging mode. Of course, it is understandable that the operation process of this mode can also include a process of separately reading out the signals in the first pixel unit 110 and the second pixel unit 120. It should be noted that the reset stage and exposure stage of the pixel merging mode of this embodiment are respectively the same as the reset stage and exposure stage of the pixel merging mode in Example 1, and will not be repeated here. Only the quantization readout stage will be explained.

[0102] The quantization readout stage includes quantization readout of pixel signals at low conversion gain, quantization readout of pixel signals at high conversion gain, and quantization readout of pixel signals under charge overflow. Under low conversion gain, correlated double sampling is performed on the first and second potential well charge signals, respectively; under high conversion gain, correlated double sampling is performed on the first and second potential well charge signals, respectively; under charge overflow, pixel merging is performed on the first and second pixel portions via the resolution control unit, and non-true correlated double sampling is performed after merging the first and second overflow charge signals.

[0103] For example, the gain transistors M5 in the first gain conversion module 116 and the second gain conversion module 126 are controlled to be turned on, so that the first pixel portion 110 and the second pixel portion 120 enter a low conversion gain state, and then the selection transistors M4 in the first readout module 113 and the second readout module 123 are controlled to be turned on, so that the first potential well reset signal and the second potential well reset signal are respectively quantized and read out at the low conversion gain state.

[0104] Afterwards, the gain transistors M5 in the first gain conversion module 116 and the second gain conversion module 126 are controlled to be turned off, so that the first pixel portion 110 and the second pixel portion 120 enter a high conversion gain, and the first potential well reset signal and the second potential well reset signal are respectively quantized and read out at the high conversion gain through the first readout module 113 and the second readout module 123; then, the transmission transistors in the first photosensitive module 111 and the second photosensitive module 121 are controlled to be turned on and then turned off, and the first potential well charge signal and the second potential well charge signal are respectively quantized and read out at the high conversion gain through the first readout module 113 and the second readout module 123, thereby achieving correlated double sampling of the first potential well charge signal and the second potential well charge signal at the high conversion gain;

[0105] Afterwards, the gain transistor M5 in the first gain conversion module 116 and the second gain conversion module 126 is controlled to be turned on again, so that the first pixel portion 110 and the second pixel portion 120 enter a low conversion gain state, and the transmission transistors in the first photosensitive module 111 and the second photosensitive module 121 are controlled to be turned on and then turned off, so that the first potential well charge signal and the second potential well charge signal are respectively quantized and read out through the first readout module 113 and the second readout module 123 at a low conversion gain, thereby achieving correlated double sampling of the first potential well charge signal and the second potential well charge signal at a low conversion gain. After completion, the selection transistor M4 in the first readout module 113 and the second readout module 123 is controlled to be turned off.

[0106] Finally, the overflow transistor M6 in the first capacitance adjustment module 114 and the second capacitance adjustment module 124 is controlled to be turned on, so that the first pixel portion 110 and the second pixel portion 120 are pixel-merged. Then, the transmission transistors in the first photosensitive module 111 and the second photosensitive module 121 are controlled to be turned on and then turned off, and the selection transistor M4 in the first readout module 113 or the second readout module 123 is controlled to be turned on, and the first overflow charge signal and the second overflow charge signal are merged and quantized and read out. Then, the reset transistor M2 in the first reset module 112 and the second reset module 122 is controlled to be turned on and then turned off, so as to reset the first capacitance adjustment module 114 and the second capacitance adjustment module 124. The first overflow reset signal and the second overflow reset signal are merged and quantized and read out through the first readout module 113 or the second readout module 123, thereby realizing non-true correlated double sampling after the first overflow charge signal and the second overflow charge signal are merged under charge overflow.

[0107] It should be noted that in pixel merging mode, Figure 5 、 Figure 7 or Figure 8 As shown in the structure, as long as the overflow transistor M6 is turned on, Figure 6 In the structure shown, the second switch tube M8 is required to be in the on state at all times. Of course, it is also feasible that the second switch tube M8 is in the off state during the reset stage and the exposure stage and is only in the on state during the quantization readout stage. In addition, the selection transistors M4 in the first readout module 113 and the second readout module 123 can also be controlled differently, as long as the relevant signals are read out normally.

[0108] In pixel-independent mode, the resolution control unit 130 disconnects the first pixel unit 110 and the second pixel unit 120. At this point, the second switch M8 in the resolution control unit 130 is turned off, allowing the first pixel unit 110 and the second pixel unit 120 to function independently to acquire pixel signals. Pixel-independent mode includes a reset phase, an exposure phase, and a quantized readout phase. In this mode, at least one second switch M8 is turned off to enable signal readout between pixel units, obtaining high-resolution pixel information. Of course, if multiple second switches M8 are present, the gain of the corresponding pixel units can be adjusted using the remaining non-disabled second switches M8, facilitating gain optimization.

[0109] Specifically, the quantization readout stage includes quantization readout of pixel signals under low conversion gain, quantization readout of pixel signals under high conversion gain, and quantization readout of pixel signals under charge overflow. Under low conversion gain, correlated double sampling is performed on the first potential well charge signal and the second potential well charge signal; under high conversion gain, correlated double sampling is performed on the first potential well charge signal and the second potential well charge signal; and under charge overflow, non-true correlated double sampling is performed on the first overflow charge signal and the second overflow charge signal.

[0110] It should be noted that when the first pixel portion 110 and the second pixel portion 120 operate independently, the control of the two is the same; and in the pixel independent mode, the on-off control of each transistor in the first pixel portion 110 and the second pixel portion 120 at each stage is roughly the same as the on-off control of each transistor in the first pixel portion 110 and the second pixel portion 120 at each stage in the pixel merging mode, which will not be repeated here.

[0111] Example 3

[0112] like Figures 10 to 13 As shown, this embodiment provides an image sensor supporting multiple resolutions, which differs from the first embodiment in that the first capacitance adjustment module 114 in the first pixel portion 110 and the second capacitance adjustment module 124 in the second pixel portion 120 are changed from gain conversion modules to charge overflow modules, the first pixel portion 110 further includes a first gain conversion module 116, and the second pixel portion 120 further includes a second gain conversion module 126, and the circuit structure of the resolution control portion 130 is different.

[0113] The first pixel portion 110 includes a first photosensitive module 111, a first reset module 112, a first readout module 113, a first capacitance adjustment module 114, and a first floating diffusion node FD1. The first capacitance adjustment module 114 is a charge overflow module connected to the first floating diffusion node FD1. It adjusts the storage capacity of the first pixel portion 110 by receiving a first charge signal overflowing from the first photosensitive module 111. In this case, the first charge signal includes a first potential well charge signal and a first overflow charge signal. The first potential well charge signal is stored in the first photosensitive module 111, and the first overflow charge signal is stored in the first capacitance adjustment module 114. Furthermore, the first pixel portion 110 also includes a first gain conversion module 116, connected between the first reset module 112 and the first floating diffusion node FD1, or connected to the first floating diffusion node FD1, for switching between different conversion gains (e.g., low conversion gain and high conversion gain).

[0114] The second pixel portion 120 includes a second photosensitive module 121, a second reset module 122, a second readout module 123, a second capacitance adjustment module 124, and a second floating diffusion node FD2. The second capacitance adjustment module 124 is a charge overflow module connected to the second floating diffusion node FD2. It adjusts the storage capacity of the second pixel portion 120 by receiving a second charge signal overflowing from the second photosensitive module 121. In this case, the second charge signal includes a second potential well charge signal and a second overflow charge signal. The second potential well charge signal is stored in the second photosensitive module 121, and the second overflow charge signal is stored in the second capacitance adjustment module 124. Furthermore, the second pixel portion 120 also includes a second gain conversion module 126 connected between the second reset module 122 and the second floating diffusion node FD2, or connected to the second floating diffusion node FD2, for switching between different conversion gains (e.g., low conversion gain and high conversion gain).

[0115] Specifically, the first capacitance adjustment module 114 and the second capacitance adjustment module 124 have the same circuit structure, including an overflow transistor M6; wherein the control terminal of the overflow transistor M6 receives the overflow control signal OF, the first terminal of the overflow transistor M6 is connected to the corresponding floating diffusion node, and the second terminal of the overflow transistor M6 is connected to the resolution control unit 130, as shown in FIG. Figure 10-13 shown.

[0116] The first gain conversion module 116 and the second gain conversion module 126 have the same circuit structure; when the corresponding gain conversion module is connected between the corresponding reset module and the corresponding floating diffusion node, it includes a gain transistor M5, the control end of the gain transistor M5 receives the gain control signal DCG, the first end of the gain transistor M5 is connected to the corresponding reset module, and the second end of the gain transistor M5 is connected to the corresponding floating diffusion node, such as Figure 10-12As shown; when the corresponding gain conversion module is connected to the corresponding floating diffusion node, it includes a gain transistor M5 and a gain capacitor Cdcg, the control end of the gain transistor M5 receives the gain control signal, the first end of the gain transistor M5 is connected to the corresponding floating diffusion node, and the second end of the gain transistor M5 is connected to the fourth potential via the gain capacitor Cdcg, as shown Figure 13 shown.

[0117] In addition, the first photosensitive module 111, the first reset module 112 and the first readout module 113 in the first pixel unit 110 and the second photosensitive module 121, the second reset module 122 and the second readout module 123 in the second pixel unit 120 are the same as those in the first embodiment and will not be repeated here.

[0118] In the above example, each pixel portion connected to the same resolution control portion 130 includes its own reset module. For example, the first pixel portion 110 includes a first reset module 112, and the second pixel portion 120 includes a second reset module 122. In actual applications, each pixel portion connected to the same resolution control portion 130 may not include its own reset module, as long as there is at least one reset module. In this case, among the pixel portions connected to the same resolution control portion 130, at least one reset module is retained, and the other reset modules are omitted. For example, the reset module of any one of the first pixel portion 110 and the second pixel portion 120 is retained, and the reset module of the other is omitted.

[0119] The resolution control unit 130 is connected between the first capacitance adjustment module 114 and the second capacitance adjustment module 124 and has the following different circuit structures.

[0120] In one embodiment, Figure 10 As shown, the resolution control unit 130 includes a shared overflow capacitor Cof; wherein a first end of the shared overflow capacitor Cof is connected to an end of the first capacitance adjustment module 114 away from the first floating diffusion node FD1, and is connected to an end of the second capacitance adjustment module 124 away from the second floating diffusion node FD2, and a second end of the shared overflow capacitor Cof is connected to a first potential V1 (e.g., a variable potential). In this embodiment, when the overflow transistor M6 is turned on, the shared overflow capacitor Cof can be used to achieve pixel merging of the first pixel portion 110 and the second pixel portion 120. That is, the first pixel portion 110 and the second pixel portion 120 are pixel-merged by sharing a single overflow capacitor node through the resolution control unit 130.

[0121] In another embodiment, Figure 11As shown, the resolution control unit 130 includes a first overflow capacitor Cof1, a second overflow capacitor Cof2 and at least one second switch tube M8; wherein, the first end of the first overflow capacitor Cof1 is connected to the end of the first capacitance adjustment module 114 away from the first floating diffusion node FD1, the second end of the first overflow capacitor Cof1 is connected to the second potential V2 (for example, a variable potential), the first end of the second overflow capacitor Cof2 is connected to the end of the second capacitance adjustment module 124 away from the second floating diffusion node FD2, the second end of the second overflow capacitor Cof2 is connected to the third potential V3 (for example, a variable potential), the control end of the second switch tube M8 receives the second control signal CTL2, the first end of the second switch tube M8 is connected to the first end of the first overflow capacitor Cof1, and the second end of the second switch tube M8 is connected to the first end of the second overflow capacitor Cof2. In this embodiment, when the overflow transistor M6 is turned on, the first pixel portion 110 and the second pixel portion 120 can be pixel-merged by controlling the second switch tube M8 to be turned on. Of course, by controlling the second switch tube M8 to be turned off, the first pixel portion 110 and the second pixel portion 120 can also operate independently. Through the design of the second switch tube M8, the first pixel portion 110 and the second pixel portion 120 can be configured with different overflow capacitors.

[0122] In practical applications, the number of the second switch tubes M8 can be one or more than one; when the number of the second switch tubes M8 is more than one, the second switch tubes M8 are connected in series. Figure 2 In the embodiment of the present invention, the first switch tube M7 is connected in a manner as shown in FIG. 1 ; at this time, the second control signal CTL2 received by the control terminal of each second switch tube M8 is usually partially the same and partially different. In this way, when the first pixel portion 110 and the second pixel portion 120 operate independently, by controlling the on / off status of each second switch tube M8, the storage capacity of the first pixel portion 110 and the second pixel portion 120 can be adjusted when the overflow transistor M6 is turned on, thereby obtaining more conversion gain.

[0123] Further, such as Figure 12As shown, the resolution control unit 130 also includes a fast reset transistor M9; wherein, when the resolution control unit 130 includes a shared overflow capacitor Cof, the control end of the fast reset transistor M9 receives a fast reset control signal OF_RST, the first end of the fast reset transistor M9 is connected to the power supply potential VDD, and the second end of the fast reset transistor M9 is connected to the second end of the shared overflow capacitor Cof. In this case, the second end of the shared overflow capacitor Cof is no longer connected to the first potential V1; when the resolution control unit 130 includes a first overflow capacitor Cof1, a second overflow capacitor Cof2, and at least one second switch transistor M8, the control end of the fast reset transistor M9 receives a fast reset control signal OF_RST, the first end of the fast reset transistor M9 is connected to the power supply potential VDD, and the second end of the fast reset transistor M9 is connected to the second end of the first overflow capacitor Cof1 and the second end of the second overflow capacitor Cof2. In this case, the second end of the first overflow capacitor Cof1 is no longer connected to the second potential V2, and the second end of the second overflow capacitor Cof2 is no longer connected to the third potential V3. Due to the design of the fast reset transistor M9, when resetting the corresponding overflow capacitor, a fast reset can be achieved by controlling the fast reset transistor M9 to turn on. In addition, when the fast reset transistor M9 is present, the first reset module 112 or the second reset module 122 may be omitted.

[0124] Optionally, for the image sensor of this embodiment: when the corresponding gain conversion module is connected between the corresponding reset module and the corresponding floating diffusion node, in at least two pixel units 100 in the same column, the first ends of the gain transistors M5 in the first pixel portions 110 are connected to each other, and the first ends of the gain transistors M5 in the second pixel portions 120 are connected to each other. In this way, the pixel units 100 can share gain capacitance, as shown in FIG. Figure 14 When the corresponding gain conversion modules are connected to the corresponding floating diffusion nodes, in at least two pixel units 100 in the same column, the second ends of the gain transistors M5 in the first pixel portions 110 are connected to each other, and the second ends of the gain transistors M5 in the second pixel portions 120 are connected to each other. In this way, the pixel units 100 can share gain capacitance.

[0125] Accordingly, this embodiment also provides an operating method for an image sensor supporting multiple resolutions, which includes at least a pixel merging mode; wherein, if the image sensor adopts Figure 10 、 Figure 12 or Figure 13 The structure shown in the figure, the operation method only includes the pixel merging mode; if the image sensor adopts Figure 11 The structure shown in FIG2 shows a pixel-binning mode. The operation method includes not only the pixel-binning mode but also the pixel-independent mode. It should be noted that the pixel-binning mode and the pixel-independent mode of this embodiment are the same as those of the second embodiment and will not be described in detail here.

[0126] It should be noted that the pixel merging mode and pixel independent mode provided by the present invention can be selected according to actual needs. For example, considering factors such as resolution requirements, different operating modes can include different information under the merged signal and the independent signal. The actual readout data is not opposite in different modes. In actual applications, the corresponding signals can be read out according to the circuit structure as needed. When the signals need to be read out in both the merged and independent modes, the reset stage and the exposure stage can be shared, and different modes are only read out in the readout stage. A single frame can obtain image information at different resolutions. The design based on the present invention can achieve readout of different resolutions, reduce noise and noise differences at different resolutions, and improve the quality of the final image obtained.

[0127] In summary, the present invention, a multi-resolution image sensor, through signal merging within the pixel's charge domain, can reduce signal-correlated noise, ensuring that the image sensor exhibits approximately the same noise performance at each resolution, thereby improving image quality. Therefore, the present invention effectively overcomes the shortcomings of existing technologies and possesses high industrial value.

[0128] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed in the present invention are intended to be covered by the claims of the present invention.

Claims

1. An image sensor supporting multiple resolutions, characterized in that: include: A plurality of pixel units arranged in an array, each pixel unit comprising at least a first pixel portion, a second pixel portion, and a resolution control portion, wherein: The first pixel portion is connected to the second pixel portion via the resolution control portion, and the first pixel portion and the second pixel portion are pixel-merged by the resolution control portion to achieve resolution control.

2. The image sensor supporting multiple resolutions according to claim 1, wherein: The first pixel portion includes a first photosensitive module, a first reset module, a first readout module, a first capacitance adjustment module and a first floating diffusion node; the second pixel portion includes a second photosensitive module, a second reset module, a second readout module, a second capacitance adjustment module and a second floating diffusion node; the corresponding photosensitive module is connected to the corresponding floating diffusion node for converting the light signal into a corresponding charge signal; the corresponding reset module is connected to the corresponding floating diffusion node for at least resetting the corresponding floating diffusion node; the corresponding readout module is connected to the corresponding floating diffusion node for at least reading out the corresponding charge signal; the corresponding capacitance adjustment module is coupled to the corresponding floating diffusion node for adjusting the storage capacity of the corresponding pixel portion; wherein the resolution control portion is connected between the first capacitance adjustment module and the second capacitance adjustment module.

3. The image sensor supporting multiple resolutions according to claim 2, wherein: The first capacitance adjustment module and the second capacitance adjustment module are gain conversion modules, which are connected between the corresponding reset module and the corresponding floating diffusion node or connected to the corresponding floating diffusion node, and adjust the storage capacity of the corresponding pixel part by switching different conversion gains; or, the first capacitance adjustment module and the second capacitance adjustment module are charge overflow modules, which are connected between the corresponding reset module and the corresponding floating diffusion node or connected to the corresponding floating diffusion node, and adjust the storage capacity of the corresponding pixel part by receiving the charge signal overflowed from the corresponding photosensitive module.

4. The image sensor supporting multiple resolutions according to claim 3, wherein: When the first capacitance adjustment module and the second capacitance adjustment module are gain conversion modules: the resolution control unit includes at least one first switching tube, the control end of the first switching tube receives a first control signal, the first end of the first switching tube is connected to the connection node between the first capacitance adjustment module and the first reset module or is connected to an end of the first capacitance adjustment module away from the first floating diffusion node, and the second end of the first switching tube is connected to the connection node between the second capacitance adjustment module and the second reset module or is connected to an end of the second capacitance adjustment module away from the second floating diffusion node; and / or, at least one reset module in each pixel unit connected to the same resolution control unit is retained, and the others are omitted.

5. The image sensor supporting multiple resolutions according to claim 4, wherein: When the number of the first switching tubes is greater than one, the first switching tubes are connected in series.

6. The image sensor supporting multiple resolutions according to claim 3, wherein: When the first capacitance adjustment module and the second capacitance adjustment module are gain conversion modules: the first pixel portion also includes a first charge overflow module, and the second pixel portion also includes a second charge overflow module, wherein the corresponding charge overflow module is connected to the corresponding floating diffusion node for receiving the corresponding charge signal overflowed from the corresponding photosensitive module.

7. The image sensor supporting multiple resolutions according to claim 3, wherein: When the first capacitance adjustment module and the second capacitance adjustment module are charge overflow modules: The resolution control unit includes a shared overflow capacitor, a first end of the shared overflow capacitor is connected to a connection node between the first capacitance adjustment module and the first reset module and a connection node between the second capacitance adjustment module and the second reset module, or is connected to an end of the first capacitance adjustment module away from the first floating diffusion node and an end of the second capacitance adjustment module away from the second floating diffusion node, and a second end of the shared overflow capacitor is connected to a first potential; or the resolution control unit includes a first overflow capacitor, a second overflow capacitor, and at least one second switch transistor, a first end of the first overflow capacitor is connected to a connection node between the first capacitance adjustment module and the first reset module or to an end of the first capacitance adjustment module away from the first floating diffusion node, a second end of the first overflow capacitor is connected to a second potential, a first end of the second overflow capacitor is connected to a connection node between the second capacitance adjustment module and the second reset module or to an end of the second capacitance adjustment module away from the second floating diffusion node, a second end of the second overflow capacitor is connected to a third potential, a control end of the second switch transistor receives a second control signal, a first end of the second switch transistor is connected to a first end of the first overflow capacitor, and a second end of the second switch transistor is connected to a first end of the second overflow capacitor; And / or, at least one reset module in each pixel unit connected to the same resolution control unit is retained, and the others are omitted.

8. The image sensor supporting multiple resolutions according to claim 7, wherein: The resolution control unit also includes a fast reset tube, a control end of the fast reset tube receives a fast reset control signal, a first end of the fast reset tube is connected to a power supply potential, and a second end of the fast reset tube is connected to the second end of a corresponding overflow capacitor.

9. The image sensor supporting multiple resolutions according to claim 7, wherein: The first pixel portion further includes a first gain conversion module, and the second pixel portion further includes a second gain conversion module, wherein when the first capacitance adjustment module and the second capacitance adjustment module are connected between the corresponding reset module and the corresponding floating diffusion node, the corresponding gain conversion module is connected to the corresponding floating diffusion node; when the first capacitance adjustment module and the second capacitance adjustment module are connected to the corresponding floating diffusion node, the corresponding gain conversion module is connected between the corresponding reset module and the corresponding floating diffusion node or to the corresponding floating diffusion node, for switching different conversion gains.

10. The image sensor supporting multiple resolutions according to claim 9, wherein: When the corresponding gain conversion module is connected to the corresponding floating diffusion node, the first gain conversion module and the second gain conversion module each include a gain transistor and a gain capacitor, a control terminal of the gain transistor receives a gain control signal, a first terminal of the gain transistor is connected to the corresponding floating diffusion node, and a second terminal of the gain transistor is connected to a fourth potential via the gain capacitor; wherein, in at least two pixel units in the same column, the second terminals of the gain transistors in the first pixel portions are connected to each other, and the second terminals of the gain transistors in the second pixel portions are connected to each other; When the corresponding gain conversion module is connected between the corresponding reset module and the corresponding floating diffusion node, the first gain conversion module and the second gain conversion module each include a gain transistor, a control end of the gain transistor receives a gain control signal, a first end of the gain transistor is connected to the corresponding reset module, and a second end of the gain transistor is connected to the corresponding floating diffusion node; wherein, in at least two pixel units in the same column, the first ends of the gain transistors in the first pixel portions are connected to each other, and the first ends of the gain transistors in the second pixel portions are connected to each other.

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