Semiconductor device and clock control circuit

Abstract

A semiconductor device and a clock control circuit, the semiconductor device including an on-chip clock controller configured to provide a clock output signal, configured to receive a mode signal and a speed enable signal, and configured to generate a first fast clock enable signal and a first slow clock enable signal. The on-chip clock controller is configured to overwrite the first fast clock enable signal based on the mode signal and the speed enable signal to provide a fast clock in the clock output signals, the overwrite circuit is configured to overwrite the first slow clock enable signal based on the mode signal and the speed enable signal to provide a slow clock in the clock output signal.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device having an on-chip clock controller. Background Art

[0002] Generally, testing a large-scale semiconductor device involves at least one scan phase for loading a test pattern into the device, at least one capture phase for exercising the device, and at least one scan phase for transferring results out of the device. During the scan phase, which transfers the test pattern into the device, the test pattern is loaded at a slower clock rate to initialize the device to a known state. During the capture phase, multiple clock pulses are supplied at a higher clock rate to operate the device, also known as at-speed testing. During the scan phase, which transfers results out of the device, the results are transferred out at the slower clock rate. Utility Model Content

[0003] A semiconductor device includes an on-chip clock controller configured to provide a clock output signal and configured to receive a mode signal and a speed enable signal. The on-chip clock controller is also configured to generate a first fast clock enable signal and a first slow clock enable signal, wherein the on-chip clock controller is configured to overwrite the first fast clock enable signal based on the mode signal and the speed enable signal to provide a fast clock in the clock output signal, and is configured to overwrite the first slow clock enable signal based on the mode signal and the speed enable signal to provide a slow clock in the clock output signal.

[0004] In some embodiments, the on-chip clock controller includes a first clock circuit and a second clock circuit, the first clock circuit being configured to provide a second fast clock enable signal based on the mode signal, the speed enable signal, and the first fast clock enable signal, and being configured to provide a second slow clock enable signal based on the mode signal, the speed enable signal, and the first slow clock enable signal, while the second clock circuit receives the second fast clock enable signal and the second slow clock enable signal and provides the clock output signal.

[0005] In some embodiments, the on-chip clock controller further comprises:

[0006] a first clock circuit, comprising:

[0007] a first AND gate having a first non-inverting input terminal and a second non-inverting input terminal, wherein the first non-inverting input terminal receives the mode signal, and the second non-inverting input terminal receives the speed enable signal;

[0008] a second AND gate having a third non-inverting input terminal and an inverting input terminal, wherein the third non-inverting input terminal receives the mode signal, and the inverting input terminal receives the speed enable signal;

[0009] a first OR gate, configured to receive a first AND gate output signal and the first fast clock enable signal, and provide a second fast clock enable signal; and

[0010] a second OR gate for receiving a second AND gate output signal and the first slow clock enable signal and providing a second slow clock enable signal; and

[0011] a second clock circuit, comprising:

[0012] a third AND gate for receiving the second fast clock enable signal and a fast clock signal and providing a gated fast clock signal;

[0013] a fourth AND gate, configured to receive the second slow clock enable signal and a slow clock signal, and provide a gated slow clock signal; and

[0014] a third OR gate for receiving the gated fast clock signal and the gated slow clock signal and providing the clock output signal;

[0015] The first AND gate provides the first AND gate output signal, the second AND gate provides the second AND gate output signal, and the second clock circuit receives the second fast clock enable signal, the second slow clock enable signal, the fast clock signal, and the slow clock signal, and provides the clock output signal.

[0016] In some embodiments, when the mode signal is at a high level and the speed enable signal is at a high level, the on-chip clock controller controls the clock output signal to oscillate at a fast clock speed.

[0017] In some embodiments, when the mode signal is at a high level and the speed enable signal is at a low level, the on-chip clock controller controls the clock output signal to oscillate at a slow clock speed.

[0018] In some embodiments, the on-chip clock controller uses the first fast clock enable signal at a high level to control the clock output signal to oscillate at a fast clock speed, and uses the first slow clock enable signal at a high level to control the clock output signal to oscillate at a slow clock speed.

[0019] A clock control circuit includes a first AND gate having a first non-inverting input terminal and a second non-inverting input terminal, the first non-inverting input terminal being configured to receive a mode signal, and the second non-inverting input terminal being configured to receive a speed enable signal; the clock control circuit further includes a second AND gate having a third non-inverting input terminal and an inverting input terminal, the third non-inverting input terminal being configured to receive the mode signal, and the inverting input terminal being configured to receive the speed enable signal; the clock control circuit further includes a first OR gate being configured to receive a first fast clock enable signal and a first AND gate output signal from the first AND gate, and being configured to output a second fast clock enable signal; the clock control circuit further includes a second OR gate being configured to receive a first slow clock enable signal and a second AND gate output signal from the second AND gate, and being configured to output a second slow clock enable signal.

[0020] In some embodiments, the clock control circuit further includes a third AND gate configured to receive the second fast clock enable signal and a fast clock signal, and configured to output a gated fast clock signal.

[0021] In some embodiments, the clock control circuit further includes a fourth AND gate configured to receive the second slow clock enable signal and a slow clock signal, and configured to provide a gated slow clock signal.

[0022] In some embodiments, the clock control circuit further includes a third OR gate configured to receive the gated fast clock signal and the gated slow clock signal, and configured to output a clock output signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The following detailed description and accompanying drawings provide a complete disclosure. It should be noted that, in accordance with common industry practice, the illustrations are not necessarily drawn to scale. Indeed, the dimensions of elements may be arbitrarily enlarged or reduced for clarity. Furthermore, the accompanying drawings are provided as examples of embodiments of the present disclosure and are not intended to be limiting.

[0024] Figure 1 A schematic diagram conceptually illustrating a semiconductor device including an on-chip clock controller (OCC) according to some embodiments is shown.

[0025] Figure 2A To conceptually describe some embodiments Figure 1 Schematic diagram of an example of a semiconductor device, the semiconductor device includes a first clock circuit in the OCC.

[0026] Figure 2B To conceptually describe some embodiments Figure 1 An example of a semiconductor device in the embodiment of the present invention includes the first clock circuit and a second clock circuit in the OCC.

[0027] Figure 3 FIG. 1 is a diagram conceptually illustrating a waveform used to test the semiconductor device and provided by the clock output signal OUT of the OCC according to some embodiments.

[0028] Figure 4 FIG. 1 is a diagram conceptually illustrating another waveform used for testing the semiconductor device and provided by the clock output signal OUT of the OCC according to some embodiments.

[0029] Figure 5 A diagram conceptually illustrating a waveform including a plurality of fast clock pulses in a second shift-in phase, wherein the second shift-in phase is between a first capture phase and a second capture phase, according to some embodiments.

[0030] Figure 6 FIG. 1 is a diagram conceptually illustrating a method for acquiring power profile information of a semiconductor device according to some embodiments.

[0031] Figure 7 is a graph conceptually illustrating maximum power pattern switching rate versus number of cycles or pulses according to some embodiments.

[0032] Figure 8 FIG. 5 is a graph conceptually illustrating a chain (0 / 1) pattern switching rate versus the number of cycles or pulses according to some embodiments.

[0033] Figure 9 FIG. 1 is a graph conceptually illustrating a maximum power pattern switching rate and a zero (0 / 1) pattern switching rate versus the number of cycles or pulses according to some embodiments.

[0034] Figure 10 is a block diagram conceptually illustrating an example of a computer system configured to provide the semiconductor devices and methods of the present disclosure according to some embodiments.

[0035] Figure 11is a block diagram of a semiconductor device production system and a related semiconductor device production process according to some embodiments.

[0036] The description of the accompanying drawings is as follows:

[0037] 20: Semiconductor devices

[0038] 22: OCC

[0039] OUT: clock output signal

[0040] 24: SOC

[0041] 26: Block Circuit

[0042] 28: First clock circuit

[0043] 30: Second clock circuit

[0044] 32: First AND gate

[0045] 34: Second AND gate

[0046] 36: First OR gate

[0047] 38: Second OR gate

[0048] 40: The third AND gate

[0049] 42: Fourth AND gate

[0050] 44: Third OR gate

[0051] 46: Trigger

[0052] 50, 60, 80: Waveform

[0053] 52: Move-in phase

[0054] 54: Extraction Phase

[0055] 56, 74, 90: Removal phase

[0056] 62, 82: First migration phase

[0057] 64, 84: First extraction stage

[0058] 66, 86: Second migration phase

[0059] 68, 88: Second extraction stage

[0060] 70: Third migration phase

[0061] 72: The third extraction stage

[0062] 100, 102, 104, 106, 108, 110, 112, 114: Operation

[0063] 122, 152, 172: x-axis

[0064] 124, 154, 174: y-axis

[0065] 126, 128, 132, 134, 136, 138, 156, 158, 160, 176, 178: Switching rate 130: Functional limitation

[0066] 200: Computer Systems

[0067] 202: Processor

[0068] 204: Computer-readable storage media

[0069] 206: Instructions

[0070] 208: Production Tools

[0071] 210: Bus

[0072] 212: I / O interface

[0073] 214: Network interface

[0074] 216: Network

[0075] 218: Database

[0076] 220: UI

[0077] 222: Semiconductor device production system

[0078] 224: Design Department

[0079] 226: Mask Department

[0080] 228: Semiconductor device processing plant

[0081] 230: Semiconductor device design layout

[0082] 232: Data Preparation Procedure

[0083] 234: Mask processing program

[0084] 236: Mask

[0085] 238: Semiconductor wafers

[0086] 240: Wafer processing procedures

[0087] 242: Semiconductor structure or semiconductor device DETAILED DESCRIPTION

[0088] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. The following disclosure describes specific examples of various components and their arrangements to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if this disclosure describes a first feature formed on or above a second feature, it means that it may include an embodiment in which the first feature and the second feature are in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the same reference symbols and / or marks may be reused in different examples of the following disclosure. These repetitions are for the purpose of simplicity and clarity, and are not intended to limit the specific relationship between the different embodiments and / or structures discussed.

[0089] Additionally, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and similar terms are used to facilitate describing the relationship of one element or feature to another element or feature in a diagram. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the drawings. The device may be rotated 90 degrees or in other orientations, and the spatially relative terms used herein should be interpreted accordingly.

[0090] When testing semiconductor devices at higher clock speeds, a relatively large number of transistors in the device are switching at the higher clock speed, increasing the current demand on the power grid. Consequently, this current demand can cause the device's power grid to droop, potentially causing the device to fail during at-speed testing or necessitating operation at a lower speed during testing. Often, application-specific test patterns are used to detect power grid droop in a device. For example, functional test patterns can be used for power detection, current measurement, and heat generation testing.

[0091] Different sets of test patterns can also be used to stress a semiconductor device. For example, design-for-test (DFT) test patterns can be used to test a semiconductor device. The DFT test pattern is clocked into the semiconductor device during a scan phase and clocked through the semiconductor device during a capture phase. The test results are clocked out of the semiconductor device during another scan phase. A clock controller clocks the DFT test pattern into, through, and out of the semiconductor device. However, the number of capture pulses that a clock controller of the semiconductor device can provide is limited by the number of shift registers within the clock controller, which are used to provide an active clock enable signal. This makes it impossible for the clock controller to provide capture pulses continuously. The shift registers are used to provide an active clock enable signal. Capture pulses can only be provided when the clock enable signal is active. This can result in a toggle rate that cannot be achieved within a capture cycle, imperfect current measurement, and imperfect heat generation.

[0092] Disclosed embodiments include a semiconductor device including an on-chip clock controller (OCC) that provides multiple shift pulses to shift test patterns into the device and test results out of the device. The OCC also provides multiple capture pulses for at-speed testing, such as at-speed testing of the device using DFT test patterns. The OCC controls the number of clock pulses and the clock speed for shifting test patterns into the device, capturing test results, and shifting test results out of the device. In the OCC, the number of clock pulses (e.g., the number of shift pulses and the number of capture pulses) can differ from or exceed the number of shift registers. In some embodiments, multiple test patterns with high or maximum capture toggle rates are shifted into the device to achieve switching / thermal power requirements with fewer shift pulses and capture pulses. In some embodiments, multiple test patterns are shifted into the device using shift pulses, which are slow clock pulses followed by capture pulses, which are fast clock pulses exceeding the number of shift registers in the OCC. In some embodiments, a displacement pulse is used to shift multiple test patterns into the device, and the above-mentioned displacement pulse is a slow clock pulse. The capture pulse is immediately followed by the above-mentioned slow clock pulse. The above-mentioned capture pulse is a fast clock pulse and is further immediately followed by the displacement pulse which can be a slow clock pulse or a fast clock pulse. In some embodiments, the above-mentioned displacement pulse which can be a slow clock pulse or a fast clock pulse is further immediately followed by the capture pulse which can be a fast clock pulse.

[0093] Disclosed embodiments include an OCC configured to provide an increased number of fast clock pulses or slow clock pulses without increasing the number of shift registers in the OCC. Furthermore, the OCC can be programmed to provide different sequences of shift pulses and capture pulses. Furthermore, in some embodiments, the OCC is configured to shift in multiple test patterns at a fast clock speed.

[0094] The disclosed embodiments further provide a method for acquiring power setting information for a semiconductor device. The method includes providing an OCC to control multiple clock speeds for shifting multiple test patterns and multiple capture results; executing an automatic test pattern generation (ATPG) process to generate multiple test patterns and report the capture power; selecting a test pattern based on the capture power or a sequence pattern; updating multiple signals to the OCC for use in a shift phase and a capture phase; executing a simulation to generate a vector change data (VCD) file; obtaining the capture power from the VCD file; determining whether the capture power reaches a required power, and repeating the steps of selecting, updating, executing, obtaining, and determining whether the capture power reaches the required power if the capture power does not reach the required power; and preparing an input signal to automatic test equipment (ATE) if the capture power reaches the required power.

[0095] The disclosed embodiments have several advantages, including managing the number and sequence of displacement pulses and capture pulses, achieving multiple power settings with a single test, and locking any testable path of a device for measurement and testing.

[0096] Figure 1 FIG2 is a schematic diagram conceptually illustrating a semiconductor device 20 according to some embodiments. The semiconductor device 20 includes an OCC 22. The OCC 22 receives a speed enable signal (SE) and a mode signal, and provides one or more clock output signals OUT. Furthermore, the OCC 22 generates a fast clock enable signal and a slow clock enable signal. In some embodiments, the OCC 22 generates a fast clock signal and a slow clock signal. In other embodiments, the OCC 22 receives a fast clock signal and a slow clock signal from outside the OCC 22.

[0097] In some embodiments, OCC 22 provides a second fast clock enable signal and a second slow clock enable signal in the clock output signal OUT. The second fast clock enable signal is generated based on the speed enable signal, the mode signal, and the fast clock enable signal, and can be used to gate the fast clock signal. The second slow clock enable signal is generated based on the speed enable signal, the mode signal, and the slow clock enable signal, and can be used to gate the slow clock signal.

[0098] In some embodiments, OCC 22 provides a clock output signal OUT. Clock output signal OUT includes a plurality of shift pulses for shifting a test pattern or I / O sequence pattern into semiconductor device 20 and shifting test results out of semiconductor device 20. Clock output signal OUT also includes a plurality of capture pulses for operating semiconductor device 20 by clocking the test pattern or I / O sequence pattern in semiconductor device 20. OCC 22 controls the number and clock speed of clock pulses used as shift pulses and capture pulses. In some embodiments, the capture pulses are at-speed capture pulses used to clock DFT test patterns (e.g., DFT transition / AC test patterns) in semiconductor device 20.

[0099] In these embodiments, the fast clock enable signal enables OCC 22 to provide a fast clock in the clock output signal OUT, where the number of clock pulses is limited by the number of shift registers in OCC 22 that provide an active fast clock enable signal. Furthermore, in some embodiments, the slow clock enable signal enables OCC 22 to provide a slow clock in the clock output signal OUT, where the number of clock pulses is limited by the number of shift registers in OCC 22 that provide an active slow clock enable signal. In some embodiments, OCC 22 includes five shift registers for providing the active fast clock enable signal, limiting OCC 22 to providing only five fast clock pulses. In some embodiments, OCC 22 includes five shift registers for providing the active slow clock enable signal, limiting OCC 22 to providing only five slow clock pulses. In some embodiments, the same shift register is used to provide both the fast clock enable signal and the slow clock enable signal.

[0100] OCC 22 is configured to override the fast clock enable signal based on the mode signal and the speed enable signal to provide a fast clock in the clock output signal OUT, wherein the number of clock pulses may exceed the number of shift registers in OCC 22. OCC 22 can use the mode signal and the speed enable signal to provide any number of consecutive fast clock pulses. Furthermore, in some embodiments, OCC 22 is configured to override the slow clock enable signal based on the mode signal and the speed enable signal to provide a slow clock in the clock output signal OUT, wherein the number of clock pulses may exceed the number of shift registers in OCC 22. OCC 22 can use the mode signal and the speed enable signal to provide any number of consecutive slow clock pulses.

[0101] When operating OCC 22, conflicting or contradictory signals (e.g., conflicting fast / slow clock enable signals) are not generated by OCC 22. In some embodiments, the speed enable signal is provided via an input / output (IO) pad. In some embodiments, the mode signal is provided via an IO pad. In some embodiments, the mode signal is programmed into a flip-flop (e.g., a D-type flip-flop in semiconductor device 20) to set the mode.

[0102] The OCC 22 includes a plurality of logic circuits and / or other circuits for performing the various functions of the OCC 22. In some embodiments, the OCC 22 includes a plurality of logic gates, such as a plurality of AND gates, a plurality of OR gates, a plurality of NAND gates, a plurality of NOR gates, a plurality of inverters (INV), and / or a plurality of other logic gates to perform the various functions of the OCC 22. In other embodiments, the OCC 22 includes other circuits (e.g., a plurality of multiplexers and / or programmable logic) to perform the various functions of the OCC 22.

[0103] In some embodiments, OCC 22 includes a first clock circuit configured to provide a second fast clock enable signal based on a mode signal, a speed enable signal, and a fast clock enable signal, and to provide a second slow clock enable signal based on the mode signal, the speed enable signal, and the slow clock enable signal. In some embodiments, OCC 22 includes a second clock circuit configured to receive the second fast clock enable signal and the second slow clock enable signal and provide a clock output signal OUT.

[0104] Figure 2A and Figure 2B To conceptually describe some embodiments Figure 1Schematic diagrams of multiple examples of semiconductor devices 20. Figure 2A To conceptually illustrate some embodiments Figure 1 A schematic diagram of an example of a semiconductor device 20 is shown in FIG. Figure 2A In FIG. 2 , the OCC 22 of the semiconductor device 20 includes a first clock circuit 28 . Figure 2B To conceptually illustrate some embodiments Figure 1 A schematic diagram of an example of a semiconductor device 20 is shown in FIG. Figure 2B In the examples, OCC 22 of semiconductor device 20 includes a first clock circuit 28 and a second clock circuit 30. In these examples, semiconductor device 20 includes a system on chip (SOC) 24, which includes a block circuit 26 (BLOCK1). OCC 22 is disposed within block circuit 26. In other embodiments, semiconductor device 20 includes OCC 22 but does not have SOC 24 and / or block circuit 26.

[0105] exist Figure 2A In the embodiment, the OCC 22 includes a first clock circuit 28, and Figure 2B In the embodiment, OCC 22 includes a first clock circuit 28 electrically connected to a second clock circuit 30, and second clock circuit 30 provides a clock output signal OUT. First clock circuit 28 includes a first AND gate 32 and a second AND gate 34. First AND gate 32 has a first non-inverting input terminal for receiving a mode signal and a second non-inverting input terminal for receiving a speed enable signal. Second AND gate 34 has a third non-inverting input terminal for receiving the mode signal and an inverting input terminal for receiving the speed enable signal. First AND gate 32 provides a first AND gate output signal, while second AND gate 34 provides a second AND gate output signal.

[0106] The first clock circuit 28 further includes a first OR gate 36 and a second OR gate 38. The first OR gate 36 receives the first AND gate output signal from the first AND gate 32 and a first fast clock enable signal, and provides a second fast clock enable signal. The second OR gate 38 receives the second AND gate output signal from the second AND gate 34 and a first slow clock enable signal, and provides a second slow clock enable signal. The first fast clock enable signal and the fast clock enable signal (such as Figure 1 ) are the same, and the first slow clock enable signal and the slow clock enable signal (as shown Figure 1 shown).

[0107] exist Figure 2BIn the embodiment, the second clock circuit 30 includes a third AND gate 40 and a fourth AND gate 42. The third AND gate 40 receives the second fast clock enable signal and the fast clock signal and provides a gated fast clock signal. The fourth AND gate 42 receives the second slow clock enable signal and the slow clock signal and provides a gated slow clock signal. The second clock circuit 30 further includes a third OR gate 44 that receives the gated fast clock signal and the gated slow clock signal and provides a clock output signal OUT.

[0108] Figure 2B The operation of the illustrated OCC 22 is as follows. This includes Figure 2A and Figure 2B The operation of the first clock circuit 28 described in Figure 2B . During operation, OCC 22 receives a mode signal and a speed enable signal. Furthermore, OCC 22 generates a first fast clock enable signal, a first slow clock enable signal, a fast clock signal, and a slow clock signal, and provides a clock output signal OUT. In other embodiments, OCC 22 receives a fast clock signal and a slow clock signal from an external source.

[0109] The OCC 22 controls the clock output signal OUT to oscillate at a fast clock speed of the fast clock signal or a slow clock speed of the slow clock signal. Alternatively, if both the second fast clock enable signal and the second slow clock enable signal are not at a high level, the OCC 22 controls the clock output signal OUT to not oscillate. In some embodiments, the speed enable signal is provided via an IO pad. In some embodiments, the mode signal is provided via an IO pad. In some embodiments, the mode signal is programmed into a flip-flop 46 (e.g., a D-type flip-flop (DFF)) to set the mode.

[0110] Assuming that the multiple input signals are non-inverting, if the mode signal is low and the first fast clock enable signal is high, the second fast clock enable signal is high, and the clock output signal OUT oscillates at the fast clock speed of the fast clock signal. The first fast clock enable signal enables OCC 22 to provide the fast clock speed in the clock output signal OUT, where the number of clock pulses is limited by the number of shift registers within OCC 22 used to provide the high-level first fast clock enable signal.

[0111] Furthermore, if the mode signal is at a low level and the first slow clock enable signal is at a high level, the second slow clock enable signal is at a high level, and the clock output signal OUT oscillates at the slow clock speed of the slow clock signal. The first slow clock enable signal enables OCC 22 to provide the slow clock speed in the clock output signal OUT, where the number of clock pulses is limited by the number of shift registers within OCC 22 used to provide the high-level first slow clock enable signal.

[0112] In some embodiments, OCC 22 includes five shift registers to provide a high-level first fast clock enable signal, limiting OCC 22 to providing only five fast clock pulses. In some embodiments, OCC 22 includes five shift registers to provide a high-level first slow clock enable signal, limiting OCC 22 to providing only five slow clock pulses. In some embodiments, the same shift register is used to provide both the first fast clock enable signal and the first slow clock enable signal.

[0113] The OCC 22 is configured to overwrite the first fast clock enable signal based on the mode signal and the speed enable signal to provide a fast clock in the clock output signal OUT, wherein the number of pulses of the fast clock may exceed the number of shift registers in the OCC 22. If the mode signal is high and the speed enable signal is high, the OCC 22 controls the clock output signal OUT to oscillate at the fast clock speed of the fast clock signal.

[0114] Furthermore, the OCC 22 is configured to overwrite the first slow clock enable signal based on the mode signal and the speed enable signal to provide a slow clock in the clock output signal OUT, wherein the number of pulses of the slow clock may exceed the number of shift registers in the OCC 22. If the mode signal is high and the speed enable signal is low, the OCC 22 controls the clock output signal OUT to oscillate at the slow clock speed of the slow clock signal.

[0115] Furthermore, if the mode signal is low, the first speed enable signal is low, and the first slow clock enable signal is low, the second fast enable signal is low and the second slow clock enable signal is low, so that the clock output signal OUT does not oscillate.

[0116] Figure 3 FIG. 5 is a diagram conceptually illustrating a waveform 50 provided in the clock output signal OUT of the OCC 22 for testing the semiconductor device 20 according to some embodiments. The waveform 50 includes a shift-in phase 52, a capture phase 54, and a shift-out phase 56.

[0117] Assuming that the multiple input signals are non-inverting, during the shift-in phase 52, the mode signal is high and the speed enable signal is low, causing OCC 22 to provide a slow clock for the slow clock signal in the clock output signal OUT. Multiple test patterns and / or 0 / 1 sequence patterns (e.g., sequence pattern 01010) are shifted into semiconductor device 20. The mode signal and the speed enable signal overwrite the first slow clock enable signal to provide a slow clock in the clock output signal OUT. The number of pulses in the slow clock may exceed the number of shift registers in OCC 22. In some embodiments, the test patterns may be multiple DFT test patterns.

[0118] Next, during the capture phase 54, the mode signal is high and the speed enable signal is high, causing OCC 22 to provide a fast clock for the fast clock signal in the clock output signal OUT. A test pattern or a 0 / 1 sequence pattern is clocked through semiconductor device 20 to operate semiconductor device 20 at the operable speed of semiconductor device 20 (i.e., at speed). The mode signal and the speed enable signal overwrite the first fast clock enable signal to provide a fast clock in the clock output signal OUT, where the number of pulses of the fast clock may exceed the number of shift registers in OCC 22. In this example, OCC 22 provides 15 at-speed capture pulses. In other embodiments, OCC 22 may provide another number of capture pulses, such as 16 or more pulses. In some embodiments, increasing the number of at-speed capture pulses may increase the power consumption of semiconductor device 20.

[0119] During the shift-out phase 56, the mode signal is high and the speed enable signal is low, causing OCC 22 to provide a slow clock of the slow clock signal in the clock output signal OUT. The test results are shifted out of semiconductor device 20. The mode signal and the speed enable signal overwrite the first slow clock enable signal to provide a slow clock in the clock output signal OUT, where the number of pulses of the slow clock may exceed the number of shift registers in OCC 22.

[0120] Figure 4 FIG2 is a diagram conceptually illustrating another waveform 60 provided by the clock output signal OUT of the OCC 22 and used for testing the semiconductor device 20 according to some embodiments. The waveform 60 includes a first shift-in phase 62, a first capture phase 64, a second shift-in phase 66, a second capture phase 68, a third shift-in phase 70, a third capture phase 72, and a shift-out phase 74.

[0121] Assuming that the multiple input signals are non-inverting, during the first shift-in phase 62, the mode signal is high and the speed enable signal is low, causing OCC 22 to provide a slow clock for the slow clock signal in the clock output signal OUT. A test pattern and / or a 0 / 1 sequence pattern is shifted into semiconductor device 20. The mode signal and the speed enable signal overwrite the first slow clock enable signal to provide a slow clock in the clock output signal OUT. The number of pulses of the slow clock is selected to shift the test pattern and / or the 0 / 1 sequence pattern into semiconductor device 20. The number of pulses of the slow clock can be any number and is not limited by the number of shift registers in OCC 22. In some embodiments, the test pattern is a DFT test pattern.

[0122] Next, during the first capture phase 64, the mode signal is high and the speed enable signal is high, causing OCC 22 to provide a fast clock for the fast clock signal in the clock output signal OUT. A test pattern or a 0 / 1 sequence pattern is clocked through semiconductor device 20 to operate semiconductor device 20 at the operational speed of semiconductor device 20 (i.e., at the same speed). The mode signal and the speed enable signal overwrite the first fast clock enable signal to provide a fast clock in the clock output signal OUT, where the number of pulses of the fast clock can be any number, such as more or less than the number of shift registers of OCC 22. In this example, OCC 22 provides five at-speed fast clock pulses. In some embodiments, OCC 22 provides another number of fast clock pulses, such as more than five fast clock pulses.

[0123] During the second shift-in phase 66, the mode signal is high and the speed enable signal is low, causing OCC 22 to provide a slow clock of the slow clock signal in the clock output signal OUT. Multiple pulses of the slow clock shift the test pattern and / or sequence pattern through multiple flip-flops in semiconductor device 20 to change the state of semiconductor device 20. The mode signal and the speed enable signal overwrite the first slow clock enable signal to provide the slow clock in the clock output signal OUT. The number of pulses of the slow clock is selected to shift the test pattern and / or 0 / 1 sequence pattern into a selected number of flip-flops. Any number of slow clock pulses can be selected, such that the number of slow clock pulses is not limited by the number of shift registers in OCC 22. In this example, OCC 22 provides three slow clock pulses in the second shift-in phase 66. In other embodiments, OCC 22 provides another number of slow clock pulses in the second shift-in phase 66.

[0124] By providing some slow clock pulses in the second shift-in phase 66, the voltage of the power grid has time to reach a stable state. Furthermore, changing the state of the flip-flop in the semiconductor device 20 prepares the semiconductor device 20 to enter the next synchronous acquisition phase.

[0125] Next, during the second capture phase 68, the mode signal is high and the speed enable signal is high, causing the OCC 22 to provide a fast clock for the fast clock signal in the clock output signal OUT. A test pattern or a 0 / 1 sequence pattern is clocked through the semiconductor device 20 to operate the semiconductor device 20 at the operational speed (i.e., at the same speed) of the semiconductor device 20. The mode signal and the speed enable signal overwrite the first fast clock enable signal to provide a fast clock in the clock output signal OUT, where the number of fast clock pulses can be any number, such as more or less than the number of shift registers in the OCC 22. In this example, the OCC 22 provides five at-speed fast clock pulses. In other embodiments, the OCC 22 can provide another number of fast clock pulses, such as more than five fast clock pulses.

[0126] During the third shift-in phase 70, the mode signal is high and the speed enable signal is low, causing OCC 22 to provide a slow clock of the slow clock signal in the clock output signal OUT. Multiple pulses of the slow clock shift the test pattern and / or sequence pattern in the flip-flops of semiconductor device 20 to change the state of semiconductor device 20. The mode signal and the speed enable signal overwrite the first slow clock enable signal to provide the slow clock in the clock output signal OUT. The number of pulses of the slow clock is selected to shift the test pattern and / or 0 / 1 sequence pattern in a selected number of flip-flops. Any number of slow clock pulses can be selected, such that the number of slow clock pulses is not limited by the number of shift registers in OCC 22. In this example, OCC 22 provides three slow clock pulses in the third shift-in phase 70. In other embodiments, OCC 22 provides another number of slow clock pulses in the third shift-in phase 70.

[0127] By providing some slow clock pulses in the third shift-in phase 70, the voltage of the power grid has time to reach a stable state. Furthermore, changing the state of the flip-flop in the semiconductor device 20 prepares the semiconductor device 20 to enter the next synchronous acquisition phase.

[0128] Next, during the third capture phase 72, the mode signal is high and the speed enable signal is high, causing the OCC 22 to provide a fast clock for the fast clock signal in the clock output signal OUT. A test pattern or a 0 / 1 sequence pattern is clocked through the semiconductor device 20 to operate the semiconductor device 20 at the operational speed (i.e., at the same speed) of the semiconductor device 20. The mode signal and the speed enable signal overwrite the first fast clock enable signal to provide a fast clock in the clock output signal OUT, where the number of fast clock pulses can be any number, such as more or less than the number of shift registers in the OCC 22. In this example, the OCC 22 provides five at-speed fast clock pulses. In other embodiments, the OCC 22 can provide another number of fast clock pulses, such as more than five fast clock pulses.

[0129] During the shift-out phase 74, the mode signal is high and the speed enable signal is low, causing OCC 22 to provide a slow clock of the slow clock signal in the clock output signal OUT. The test result is shifted out of semiconductor device 20. The mode signal and the speed enable signal overwrite the first slow clock enable signal to provide a slow clock in the clock output signal OUT. Any number of slow clock pulses can be provided, and the number of slow clock pulses can exceed the number of shift registers in OCC 22.

[0130] In other embodiments, any number of shift-in phases and retrieval phases may be provided for testing semiconductor device 20. Furthermore, in other embodiments, any number of clock pulses may be provided in each shift-in phase and each retrieval phase.

[0131] By providing multiple shift-in phases between multiple capture phases, the switching rate (i.e., the number of times the flip-flop switches in one capture cycle) can be increased, thereby increasing the power consumption of the semiconductor device 20. In some embodiments, providing multiple shift-in phases with multiple slow clock speeds between multiple capture phases with multiple fast clock speeds can increase the switching rate (power consumption) more than simply increasing the number of fast clock pulses in a single capture phase (e.g., Figure 3 The switching rate is shown).

[0132] Figure 5FIG2 is a diagram conceptually illustrating a waveform 80 according to some embodiments. The waveform 80 includes a second shift-in phase 86 between a first capture phase 84 and a second capture phase 88. The second shift-in phase 86 includes multiple fast clock pulses. The waveform 80 is provided by the clock output signal OUT of the OCC 22 and is used to test the semiconductor device 20. The waveform 80 includes a first shift-in phase 82, a first capture phase 84, a second shift-in phase 86, a second capture phase 88, and a shift-out phase 90. In some embodiments, the waveform 80 is used for heat generation testing of the semiconductor device 20.

[0133] Assuming that the multiple input signals are non-inverting, during the first shift-in phase 82, the mode signal is high and the speed enable signal is low, causing OCC 22 to provide a slow clock for the slow clock signal in the clock output signal OUT. A test pattern and / or a 0 / 1 sequence pattern is shifted into semiconductor device 20. The mode signal and the speed enable signal overwrite the first slow clock enable signal to provide a slow clock in the clock output signal OUT. The number of pulses of the slow clock is selected to shift the test pattern and / or the 0 / 1 sequence pattern into semiconductor device 20. The number of pulses of the slow clock can be any number and is not limited by the number of shift registers in OCC 22. In some embodiments, the test pattern is a DFT test pattern.

[0134] Next, during the first capture phase 84, the mode signal is high and the speed enable signal is high, causing the OCC 22 to provide a fast clock for the fast clock signal in the clock output signal OUT. A test pattern or a 0 / 1 sequence pattern is clocked through the semiconductor device 20 to operate the semiconductor device 20 at the operable speed of the semiconductor device 20 (i.e., at the same speed). The mode signal and the speed enable signal overwrite the first fast clock enable signal to provide a fast clock in the clock output signal OUT. The OCC 22 can provide any number of fast clock pulses, such as more or less than the number of shift registers of the OCC 22. In this example, the OCC 22 provides five at-speed fast clock pulses. In some embodiments, the OCC 22 provides another number of fast clock pulses, such as more than five fast clock pulses.

[0135] During the second shift-in phase 86, the mode signal is high and the speed enable signal is high, causing OCC 22 to provide a fast clock of the fast clock signal in the clock output signal OUT. In some embodiments, the fast clock pulse shifts the test pattern and / or sequence pattern through the flip-flops of the semiconductor device 20 to change the state of the semiconductor device 20. In other embodiments, the fast clock pulse in the second shift-in phase 86 is provided to increase power consumption, such that the fast clock pulse may or may not shift the test pattern and / or sequence pattern through the flip-flops of the semiconductor device 20 to change the state of the semiconductor device 20.

[0136] During the second shift-in phase 86, the mode signal and the speed enable signal overwrite the first fast clock enable signal to provide the fast clock in the clock output signal OUT. Any number of fast clock pulses can be selected such that the number of fast clock pulses is not limited by the number of shift registers in the OCC 22. In this example, the OCC 22 provides five fast clock pulses during the second shift-in phase 86. In other embodiments, the OCC 22 provides another number of fast clock pulses during the second shift-in phase 86, such as six fast clock pulses, 12 fast clock pulses, 24 fast clock pulses, or another number of fast clock pulses.

[0137] By providing a fast clock pulse in the second shift-in phase 86 , the power consumption of the semiconductor device 20 can be increased, and in some embodiments, the states of flip-flops of the semiconductor device 20 are changed to prepare the semiconductor device 20 for entering the next synchronous capture phase.

[0138] Next, during the second capture phase 88, the mode signal is high and the speed enable signal is high, causing the OCC 22 to provide a fast clock for the fast clock signal in the clock output signal OUT. A test pattern or a 0 / 1 sequence pattern is clocked through the semiconductor device 20 to operate the semiconductor device 20 at the operable speed of the semiconductor device 20 (i.e., at the same speed). The mode signal and the speed enable signal overwrite the first fast clock enable signal to provide a fast clock in the clock output signal OUT, where the number of pulses of the fast clock can be any number, such as more or less than the number of shift registers in the OCC 22. In this example, the OCC 22 provides five at-speed fast clock pulses. In other embodiments, the OCC 22 can provide another number of fast clock pulses, such as more than five fast clock pulses.

[0139] During the shift-out phase 90, the mode signal is high and the speed enable signal is low, causing the OCC 22 to provide a slow clock of the slow clock signal in the clock output signal OUT. The test result or the remaining pattern is shifted out of the semiconductor device 20. The mode signal and the speed enable signal overwrite the first slow clock enable signal to provide the slow clock in the clock output signal OUT. Any number of slow clock pulses can be provided, and the number of slow clock pulses can be different from the number of shift registers in the OCC 22.

[0140] In other embodiments, any number of shift-in phases and capture phases may be provided by a waveform for testing semiconductor device 20. Furthermore, in other embodiments, any number of clock pulses may be provided for each shift-in phase and each capture phase.

[0141] By providing a shift-in phase between multiple capture phases, the switching rate (i.e., the number of times the flip-flop switches in one capture cycle) can be increased, thereby increasing the power consumption of the semiconductor device 20. Furthermore, in some embodiments, providing a shift-in phase with a fast clock pulse between multiple capture phases with a fast clock pulse can increase the switching rate (power consumption) of the semiconductor device 20. Furthermore, providing a shift-in phase with a fast clock pulse between multiple capture phases with a fast clock pulse can increase the switching rate (power consumption) of the semiconductor device 20, making the switching rate higher than Figure 3 The waveform 50 and Figure 4 The switching rate of the waveform 60.

[0142] Figure 6 This is a schematic diagram conceptually describing a method for acquiring power profile information of a semiconductor device according to some embodiments. In some embodiments, the semiconductor device and Figure 1 In some embodiments, the semiconductor device is the same as the semiconductor device 20 of FIG.

[0143] In operation 100, the capture method includes providing an OCC for controlling a clock speed for shifting a plurality of test patterns (and / or a plurality of 0 / 1 sequence patterns) and capturing a plurality of results. In some embodiments, the OCC provides a plurality of shift pulses for shifting the test patterns and / or 0 / 1 sequence patterns into the device and for shifting the test results out of the device. Furthermore, the OCC provides a plurality of capture pulses for use in a same-speed test, such as a same-speed test of a semiconductor device using a DFT test pattern. The OCC controls the number of clock pulses and the clock speed for shifting the test patterns and / or 0 / 1 sequence patterns into the device, capturing the results, and shifting the test results out of the device. In some embodiments, the OCC may be used with Figure 1In some embodiments, the above OCC can be the same as Figure 2A In some embodiments, the above OCC can be the same as Figure 2B The same as OCC 22.

[0144] In some embodiments, the acquisition method includes providing an OCC that provides at least four different clocks, including a slow clock, a fast clock, switching between a slow clock and a fast clock, and providing a clock with at most a limited number of clock pulses based on the number of shift registers in the OCC.

[0145] The OCC (e.g., OCC 22) is configured to override the fast clock enable signal with the mode signal and the speed enable signal to provide a fast clock in the clock output signal OUT, wherein the number of pulses of the fast clock can be any number and can exceed the number of shift registers in the OCC. The OCC can use the mode signal and the speed enable signal to provide a fast clock with any number of pulses in the clock output signal OUT. Furthermore, in some embodiments, the OCC is configured to override the slow clock enable signal with the mode signal and the speed enable signal to provide a slow clock in the clock output signal OUT, wherein the number of pulses of the slow clock can be any number and can exceed the number of shift registers in the OCC. The OCC can use the mode signal and the speed enable signal to provide a slow clock with any number of pulses in the clock output signal OUT.

[0146] In operation 102, the capture method includes executing an ATPG process to generate a plurality of test patterns and reporting the captured power. The ATPG process generates test patterns for testing semiconductor devices. Furthermore, the ATPG process reports a switching rate or switching ratio that represents the captured power.

[0147] Table 1 below conceptually illustrates a power analysis summary of an ATPG process performed on a semiconductor device design, according to some embodiments. The semiconductor device design has 199,253 scan cells, and the generated test patterns are numbered from 0 to 19,120. The average clock cycle to load a test pattern is 258 clock cycles, and the average number of captured toggles is 21,527.72, or a toggle rate of approximately 10.8%. Using pattern number 13,986, the peak number of captured toggles is 44,198, or a toggle rate of approximately 22.18%.

[0148] Table 1

[0149]

[0150] Reference Figure 6In operation 104, the acquisition method includes selecting a 0 / 1 sequence pattern or a test pattern based on the acquisition power. In some embodiments, the test pattern that produces the highest toggle rate or toggle rate peak is selected (e.g., test pattern 13986 that produces a toggle rate peak of 22.18%). In some embodiments, to achieve a higher toggle rate or at least one different toggle rate, a 0 / 1 sequence pattern is selected.

[0151] In operation 106, the capture method includes updating a plurality of signals to an OCC for use in a shift phase and a capture phase. In some embodiments, updating the signals to the OCC includes providing or encoding a mode signal and a speed enable signal to provide a fast clock in the clock output signal OUT during the capture phase. In some embodiments, updating the signals to the OCC includes providing or encoding a mode signal and a speed enable signal to provide a fast clock or a slow clock in the clock output signal OUT during the capture phase. In some embodiments, updating the signals to the OCC includes activating a scan enable signal (not shown) to switch to shifting a pattern into or out of the semiconductor device. In some embodiments, updating the signals to the OCC includes deactivating a scan enable signal (not shown) to switch to a capture phase to operate the semiconductor device.

[0152] In operation 108 , the capture method includes executing a plurality of simulations using an electronic design automation (EDA) tool to generate a VCD file for a capture cycle. The VCD file includes vector transformation data for the capture cycle.

[0153] In operation 110, the capture method includes obtaining a captured power (e.g., slew rate) from a VCD file of a capture cycle using the aforementioned EDA tool or another EDA tool. In some embodiments, the VCD file is loaded into a PrimeTimePower eXtension (PTPX) (EDA) tool to obtain information about the number of switching times of the semiconductor device under test. In some embodiments, power is calculated based on clock cycles and a capture window, where the slew rate percentage is equal to the number of switching times per power net multiplied by the clock cycle divided by the capture window.

[0154] In operation 112, the extraction method includes determining whether the extracted power meets the power requirement, and if the extracted power does not meet the power requirement, repeating the steps of selecting, updating, executing, obtaining, and determining whether the extracted power meets the desired power. In some embodiments, if the extracted power is less than the power requirement, selecting a test pattern and updating the signal to the OCC includes changing the test pattern or sequence pattern to increase the extracted power or increasing the number of shift pulses between multiple extraction pulses. Furthermore, in some embodiments, if the extracted power is greater than the power requirement, selecting a test pattern and updating the signal to the OCC includes changing the test pattern or sequence pattern to reduce the extracted power or reducing the number of shift pulses of a fast clock or utilizing slow shift pulses.

[0155] In operation 114, the acquisition method includes preparing an input signal for the ATE when the acquisition power reaches the power requirement. In some embodiments, when the acquisition power is equal to the power requirement, preparing the input signal for the ATE includes utilizing a Standard Test Interface Language (STIL) pattern or converting a VCD into a Waveform Generation Language (WGL) for the ATE.

[0156] Figure 7 is a schematic diagram conceptually describing some embodiments. Figure 7 A graph of slew rate versus number of cycles or pulses for a maximum power pattern (MPP) is shown, with number of pulses on an x-axis 122 and slew rate on a y-axis 124 .

[0157] In a graph of the switching rate 126 of a plurality of fast-capture pulses, the switching rate 126 reaches a peak of about 13% within the first five pulses and then decreases along a long, smooth curve to about 2%. Figure 3 50. Thus, the slew rate 126 peaks at 13% early in the acquisition phase and then steadily decreases to a relatively constant slew rate of 2%.

[0158] In a graph of the slew rates 128 for the multiple slow displacement clock speeds and the multiple fast acquisition clock speeds, the slew rate 128 peaks at approximately 13% within the first five pulses, then drops below the slew rate 126 for the fast acquisition pulses, and then rebounds to approximately 5% at 18 pulses. The slew rates 128 for the slow displacement clock speed and the fast acquisition clock speed then follow a smooth curve down to approximately 2% at 60 pulses, then rebound to 3% at 64 pulses, and then rebound to 4% at approximately 121 pulses. The slow displacement clock speed and the fast acquisition clock speed are represented by analogy. Figure 4 A waveform 60 is provided wherein the shift phase between the capture phases causes a rebound in the switching rate 128 between the slow shift clock speed and the fast capture clock speed.

[0159] After an initial slew rate peak of 13%, the slew rate 126 of the fast capture pulse and the slew rate 128 of the slow shift clock speed and the fast capture clock speed remain below a functional limit 130 of approximately 5%, which is the value achieved during functional testing using test patterns in the Dhrystone test.

[0160] In a graph of the switching rate 132 of a plurality of dynamic (variable) fast-moving pulses between a plurality of fast-acquisition pulses, the switching rate 132 reaches a peak of 13% within the first five pulses, then drops to a functional limit 130 of about 5%, and then rebounds to about 6% at 16 pulses before decreasing to about 3% along a smooth curve. The dynamic (variable) fast-moving pulses between the fast-acquisition pulses are similar to Figure 5 A waveform of waveform 80 is provided.

[0161] In a graph of the switching rate 134 of the six fast incoming pulses between the fast acquisition pulses, the switching rate 134 reaches a peak of 13% within the first five pulses, then drops to a functional limit 130 of about 5%, and then rebounds to about 7% at 16 pulses. The switching rate 134 of the six fast incoming pulses between the fast acquisition pulses then drops to about 3% at 46 pulses along a smooth curve, then rebounds to 6% at about 52 pulses, and then drops below 4%. The six fast incoming pulses between the fast acquisition pulses are similarly Figure 5 A waveform of waveform 80 is provided.

[0162] In the long term, over multiple pulses, both the toggle rate 132 of the dynamic (variable) fast-in pulses between fast-capture pulses and the toggle rate 134 of the six fast-in pulses between fast-capture pulses drop below the functional limit 130 of approximately 5%.

[0163] In a graph of the switching rate 136 of 12 fast incoming pulses between multiple fast acquisition pulses, the switching rate 136 reaches a peak of 13% within the first five pulses, then drops to a functional limit 130 of about 5%, and then rebounds to about 7% at 18 pulses. Thereafter, the switching rate 136 of the 12 fast incoming pulses between the fast acquisition pulses drops along a smooth curve to about 3% at 46 pulses, then rebounds to 8% at about 58 pulses, and then drops to above 5%. The 12 fast incoming pulses between the fast acquisition pulses are formed by similar Figure 5 A waveform of waveform 80 is provided.

[0164] In a graph of the switching rate 138 of 24 fast incoming pulses between multiple fast acquisition pulses, the switching rate 138 reaches a peak of 13% within the first five pulses, then drops to a functional limit 130 of about 5%, and then rebounds to about 7% at 18 pulses. Thereafter, the switching rate 138 of the 24 fast incoming pulses between the fast acquisition pulses drops along a smooth curve to about 3% at 46 pulses, then rebounds to 11% at about 67 pulses, and then drops to above 8% at 142 pulses. The 24 fast incoming pulses between the fast acquisition pulses are formed by similar Figure 5 A waveform of waveform 80 is provided.

[0165] Multiple high-speed clock pulses (such as Figure 5 Furthermore, over the long term, and over multiple pulses, the switching rate 136 for 12 fast-moving-in pulses between fast-retrieval pulses and the switching rate 138 for 24 fast-moving-in pulses between fast-retrieval pulses remain above the functional limit 130 of approximately 5%.

[0166] Figure 8 is a schematic diagram conceptually describing some embodiments. Figure 8 A graph of toggle rate versus period or pulse number for a chain (0 / 1) pattern is shown, with pulse number on an x-axis 152 and toggle rate on a y-axis 154 .

[0167] In a graph of the switching rate 156 of the six fast-moving pulses between the fast-capture pulses, the switching rate 156 rises to 7% within the first five pulses, then drops to about 3% at 15 pulses, and then rebounds to about 8% at 18 pulses. Thereafter, the switching rate 156 drops along a smooth curve to about 3% at 46 pulses, then rebounds to between 7% and 8% at 52 pulses, and then drops to a switching rate of about 5%, which is close to the functional limit 130 of about 5%. The six fast-moving pulses between the fast-capture pulses are represented by similar Figure 5 A waveform of waveform 80 is provided.

[0168] In a graph of the switching rate 158 of 12 fast-moving pulses between multiple fast-capture pulses, the switching rate 158 rises to 7% within the first five pulses, then drops to about 3% at 15 pulses, and then rebounds to about 8% at 18 pulses. Thereafter, the switching rate 158 drops along a smooth curve to about 3% at 46 pulses, then rebounds to 11% at about 58 pulses, and then drops to above 6%, which is higher than the functional limit 130 of about 5%. The 12 fast-moving pulses between the fast-capture pulses are similar to Figure 5A waveform of waveform 80 is provided.

[0169] In a graph of the switching rate 160 of 24 fast-moving pulses between multiple fast-capture pulses, the switching rate 160 rises to 7% within the first five pulses, then drops to about 3% at 15 pulses, and then rebounds to about 8% at 18 pulses. Thereafter, the switching rate 160 drops to about 3% at 46 pulses along a smooth curve, then rebounds to about 18% at about 67 pulses, and then drops to about 11%, which is higher than the functional limit 130 of about 5%. The 24 fast-moving pulses between the fast-capture pulses are similar to Figure 5 A waveform of waveform 80 is provided.

[0170] For the switching rates 156, 158, and 160 of the (0 / 1) pattern, multiple high-speed clock pulses (such as Figure 5 Furthermore, over the long term, and over multiple pulses, the slew rate 156 for 6 fast incoming pulses between fast acquisition pulses, the slew rate 158 for 12 fast incoming pulses between fast acquisition pulses, and the slew rate 160 for 24 fast incoming pulses between fast acquisition pulses remain above the functional limit 130 of approximately 5%.

[0171] Figure 9 is a schematic diagram conceptually describing some embodiments. Figure 9 Graphs of toggle rate for a maximum power pattern and a chain (0 / 1) pattern versus number of cycles or pulses, with number of pulses on an x-axis 172 and toggle rate on a y-axis 174 .

[0172] In a graph of the maximum power pattern of 24 fast-moving pulses between multiple fast-acquisition pulses, the slew rate 176 reaches a peak of 13% within the first five pulses, then drops to the functional limit 130 of about 5%, and then rebounds to about 7% at 18 pulses. Thereafter, the slew rate 176 drops along a smooth curve to about 3% at 46 pulses, then rebounds to about 10% to 11% (10.4%) at about 67 pulses, and then drops to about 7% at 142 pulses, which is higher than the functional limit 130 of about 5%. The 24 fast-moving pulses between the fast-acquisition pulses are similarly Figure 5 A waveform of waveform 80 is provided.

[0173] In a graph of the toggle rate 178 of the (0 / 1) pattern of 24 fast-moving-in pulses between multiple fast-capture pulses, the toggle rate 178 reaches 7% within the first five pulses, then drops to about 3% at 15 pulses, and then rebounds to about 8% at 18 pulses. Thereafter, the toggle rate 178 drops along a smooth curve to about 3% at 46 pulses, then rebounds to 18% at about 67 pulses, and then drops to about 11% at 142 pulses, which is higher than the functional limit 130 of about 5%. The 24 fast-moving-in pulses between the fast-capture pulses are formed by similar Figure 5 A waveform of waveform 80 is provided.

[0174] During the first five pulses, the toggle rate 176 of the maximum power pattern of 24 fast incoming pulses between the fast capture pulses has a higher toggle rate of 13%, compared to the toggle rate 178 of the concatenated (0 / 1) pattern of 24 fast incoming pulses between the fast capture pulses, which has a toggle rate of 7%. This is because the maximum power pattern is biased to catch device defects, while the concatenated (0 / 1) pattern is not biased to catch device defects. Therefore, the toggle rate 176 of the maximum power pattern of 24 fast incoming pulses between the fast capture pulses is used to achieve a higher toggle rate with a smaller number of pulses.

[0175] However, after multiple pulses, the toggle rate 178 of the refined (0 / 1) pattern of the 24 rapidly incoming pulses between the rapidly captured pulses has a higher toggle rate of 18%, or 7.6%, compared to the toggle rate 176 of the maximum power pattern of the 24 rapidly incoming pulses between the rapidly captured pulses, which has a toggle rate of approximately 10.4%. Furthermore, after multiple pulses, the toggle rate 178 of the refined (0 / 1) pattern of the 24 rapidly incoming pulses between the rapidly captured pulses has a higher toggle rate of 11%, or 4%, compared to the toggle rate 176 of the maximum power pattern of the 24 rapidly incoming pulses between the rapidly captured pulses, which has a toggle rate of approximately 7%. Therefore, the toggle rate 178 of the refined (0 / 1) pattern of the 24 rapidly incoming pulses between the rapidly captured pulses is used to achieve a higher toggle rate in situations with a larger number of pulses, such as for heat generation.

[0176] Figure 10This is a block diagram conceptually illustrating an example of a computer system 200 configured to provide the semiconductor devices and methods of the present disclosure, according to some embodiments. Some or all of the design, layout, and production of semiconductor devices (also referred to as semiconductor circuits) may be performed by the computer system 200. In some embodiments, the computer system 200 comprises an electronic design automation (EDA) system. In some embodiments, the semiconductor devices are integrated circuits (ICs).

[0177] In some embodiments, computer system 200 is a general-purpose computing device comprising a processor 202 and a non-transitory computer-readable storage medium 204. Computer-readable storage medium 204 may be encoded, for example, as computer stored program code (e.g., a plurality of executable instructions 206). Processor 202 executes instructions 206 to provide (at least a portion of) a design tool to implement some or all of the functions of computer system 200, such as pre-layout simulation, post-layout simulation, routing, rerouting, and final layout for production. Furthermore, a plurality of production tools 208 are configured to further perform layout and actual implementation of the above designs and produce semiconductor devices. In some embodiments, processor 202 executes instructions 206 to provide (at least a portion of) a design tool to implement some or all of the functions of computer system 200. In some embodiments, computer system 200 comprises a commercial router. In some embodiments, computer system 200 comprises an automatic place and route (APR) system.

[0178] Processor 202 is electrically coupled to computer-readable storage medium 204 via a bus 210. Processor 202 is also electrically coupled to an input / output (I / O) interface 212 via bus 210. A network interface 214 is also electrically coupled to processor 202 via bus 210. Network interface 214 is connected to a network 216, enabling processor 202 and computer-readable storage medium 204 to connect to a plurality of external components via network 216. Processor 202 is configured to execute computer program code or instructions 206 encoded in computer-readable storage medium 204, causing computer system 200 to perform some or all of the functions of computer system 200, such as providing the semiconductor devices and methods of the present disclosure or other functions of computer system 200. In some embodiments, processor 202 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0179] In some embodiments, the computer-readable storage medium 204 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system, apparatus, or device. For example, the computer-readable storage medium 204 may include a semiconductor or solid-state memory, a magnetic tape, a removable computer disk, a random-access memory (RAM), a read-only memory (ROM), a hard disk, and / or an optical disk. In some embodiments utilizing optical disks, the computer-readable storage medium 204 may include a compact disk read-only memory (CD-ROM), a compact disk read / write memory (CD-R / W), and / or a digital video disk (DVD).

[0180] In some embodiments, computer-readable storage medium 204 stores computer program code or instructions 206 configured to cause system 200 to perform some or all of the functions of system 200. In some embodiments, computer-readable storage medium 204 also stores information that facilitates the performance of some or all of the functions of system 200. In some embodiments, computer-readable storage medium 204 stores a database 218 that includes one or more component libraries, digital circuit unit libraries, and databases.

[0181] System 200 includes an I / O interface 212 for coupling to external circuitry. In some embodiments, I / O interface 212 includes a keyboard, a keypad, a mouse, a trackball, a trackpad, a touch screen, and / or cursor keys for transmitting information and commands to processor 202.

[0182] Network interface 214 is coupled to processor 202 and allows system 200 to communicate with network 216, which in turn connects to one or more other computer systems. Network interface 214 can include a wireless network interface such as Bluetooth, wireless fidelity (WIFI), worldwide interoperability for microwave access (WIMAX), general packet radio service (GPRS), or wideband code division multiple access (WCDMA); or it can include a wired network interface such as Ethernet, universal serial bus (USB), or IEEE-1364. In some embodiments, some or all of the functionality of system 200 can be implemented on two or more systems similar to system 200.

[0183] System 200 is configured to receive information via I / O interface 212. The information received by I / O interface 212 includes one or more instructions, data, design rules, component and unit libraries, and / or other parameters processed by processor 202. Furthermore, system 200 is configured to receive information related to a user interface (UI) via I / O interface 212. This UI information may be stored in the form of a UI 220 in computer-readable storage medium 204.

[0184] In some embodiments, some or all of the functionality of system 200 may be implemented by a separate software application used by a processor to execute programs. In some embodiments, some or all of the functionality of system 200 may be implemented in a software application that is part of an external software application. In some embodiments, some or all of the functionality of system 200 is implemented as a plug-in to a software application. In some embodiments, at least one functionality of system 200 is implemented by a software application that is part of a unique EDA tool. In some embodiments, some or all of the functionality of system 200 is implemented by a software application used by system 200. In some embodiments, a layout diagram is generated using a tool (e.g., VIRTUOSO provided by CADENCE Design Systems, Inc. or other suitable layout generation tool).

[0185] In some embodiments, wiring, layout, and other processes are implemented as multiple functions of a program stored in a non-transitory computer-readable recording medium. For example, a non-transitory computer-readable recording medium includes (but is not limited to) external / removable and / or internal / built-in memory or storage unit, such as one or more optical discs (e.g., a digital video disc (DVD) or a digital versatile disc (DVD)), a magnetic disk (e.g., a hard disk), a semiconductor memory (e.g., a ROM and a RAM), a memory card, and the like.

[0186] As described above, various embodiments of the system 200 include a production tool 208 for implementing the production process of the system 200. For example, based on the final layout, a plurality of photolithographic masks may be formed and used to produce semiconductor devices using the production tool 208.

[0187] Reference Figure 11 , combined with Figure 11 More embodiments of the device production process are disclosed, wherein Figure 11 FIG2 is a block diagram of a semiconductor device production system 222 and a related semiconductor device production process according to some embodiments. In some embodiments, the production system 222 is used to produce one or more semiconductor masks and / or at least one component in a layer of a semiconductor device based on a layout.

[0188] exist Figure 11In the present disclosure, semiconductor device production system 222 includes multiple entities, such as a design house 224, a mask house 226, and a semiconductor device fabrication / fab 228. These entities interact with each other during the design, development, and production cycles and / or services associated with producing semiconductor devices (such as the semiconductor devices described herein). The entities in semiconductor device production system 222 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a plurality of different networks, such as an intranet and the internet. The communication network includes multiple wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, a larger company may have two or more design houses 224, mask houses 226, and semiconductor device fabrication / fabs 228. In some embodiments, the two or more design houses 224, mask houses 226, and semiconductor device fabrication / fabs 228 are co-located in a common facility and utilize common resources.

[0189] The design department (or design team) 224 generates a semiconductor device design layout 230. The semiconductor device design layout 230 includes a plurality of geometric patterns or semiconductor device design layouts designed for a semiconductor device. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that comprise the various components of the semiconductor device to be manufactured. These layers combine to form various features of the semiconductor device. For example, a portion of the semiconductor device design layout 230 includes a plurality of semiconductor device features to be formed in a semiconductor substrate (e.g., a semiconductor wafer) and in various material layers located above the semiconductor substrate. For example, the semiconductor device features may be diagonal vias, active regions or regions, gate electrodes, sources, drains, metal lines, local vias, and openings for bond pads. The design department 224 generates the semiconductor device design layout 230 using a design program. The semiconductor device design layout 230 is presented in one or more data files containing information about the geometric patterns. For example, the semiconductor device design layout 230 may be displayed in a GDSII file format or a DFII file format. In some embodiments, the design process includes one or more of an analog circuit design, a digital circuit design, a logic circuit design, a standard cell circuit design, a power distribution network (PDN) design, and an actual layout design, wherein the PDN design includes a power via design, a power voltage path design, a reference voltage path design, a placement process, and a routing process.

[0190] The mask department 226 includes a data preparation program 232 and a mask processing program 234. The mask department 226 uses the semiconductor device design layout 230 to produce one or more masks 236 for producing multiple layers of semiconductor devices or semiconductor structures. The mask department 226 executes the mask data preparation program 232, wherein the semiconductor device design layout 230 is converted into a representative data file (RDF). The mask data preparation program 232 provides the RDF to the mask processing program 234. The mask processing program 234 includes a mask writer for converting the RDF into an image on a substrate (such as a mask (reticle) 236 or a semiconductor wafer 238). The mask data preparation program 232 controls the semiconductor device design layout 230 to comply with the characteristics of the mask writer and / or the standards of the semiconductor device processing plant 228. In Figure 11 In FIG, the reticle data preparation program 232 and the reticle processing program 234 are described as separate elements. In some embodiments, the reticle data preparation program 232 and the reticle processing program 234 may be collectively referred to as a reticle data preparation program.

[0191] In some embodiments, the mask data preparation process 232 includes an optical proximity correction (OPC) that utilizes lithography enhancement techniques to compensate for image errors, such as those due to diffraction, interference, other process effects, and the like. OPC adjusts the semiconductor device design layout 230. In some embodiments, the mask data preparation process 232 includes further resolution enhancement techniques (RET), such as off-axis illumination, secondary resolution assist features, phase-shifted masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also utilized to treat OPC as an inverse image problem.

[0192] In some embodiments, the mask data preparation process 232 includes a mask rule checker (MRC) to check the semiconductor device design layout 230 after it has been processed in an OPC process. The OPC process has a set of mask production rules, including certain geometric and / or connection constraints, to ensure that the semiconductor device design layout 230 has sufficient margin to account for semiconductor process variability or the like. In some embodiments, the MRC modifies the semiconductor device design layout 230 to compensate for the constraints of the mask processing process 234, which may erase the changes made by the OPC to meet the mask production rules.

[0193] In some embodiments, the mask data preparation program 232 includes lithography process checking (LPC) to simulate the process to be implemented by the semiconductor device fabrication plant 228. The LPC simulates this process based on the semiconductor device design layout diagram 230 to generate a simulated production device. The process parameters in the LPC simulation may include parameters related to multiple processes in the semiconductor device production cycle, parameters related to the tools for producing semiconductor devices, and / or other production process embodiments. The LPC considers multiple factors, such as top view image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and the like or combinations of the above factors. In some embodiments, after the LPC generates a simulated production device, if the simulated device fails to meet the design rules, the OPC and / or MRC will be repeatedly performed to further improve the semiconductor device design layout diagram 230.

[0194] The reticle data preparation process 232 described above is simplified for clarity. In some embodiments, the data preparation process 232 includes additional features, such as a logic operation (LOP), to modify the semiconductor device design layout 230 according to manufacturing rules. Furthermore, the processes applied to the semiconductor device design layout 230 during the data preparation process 232 can be executed in a variety of different orders.

[0195] After the mask data preparation process 232 and during the mask processing process 234, a mask 236 or a set of masks 236 are produced based on the modified semiconductor device design layout 230. In some embodiments, the mask processing process 234 includes performing one or more lithographic exposures based on the semiconductor device design layout 230. In some embodiments, an electron beam (e-beam) or multiple electron beams from a mechanism are used to form a pattern on a mask (photomask or reticle) 236 based on the modified semiconductor device design layout 230. The mask 236 can be formed using a variety of techniques. In some embodiments, the mask 236 is formed using a binary technique. In some embodiments, a mask pattern includes multiple opaque regions and multiple transparent regions. A radiation beam (e.g., an ultraviolet beam (UV beam)) used to expose an image-sensitive material layer (e.g., photoresist) attached to the wafer surface is blocked by the opaque regions and passes through the transparent regions. In one example, a binary mask version of mask 236 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) attached to the surface of the opaque regions of the binary mask. In another example, mask 236 is formed using a phase shifting technique. In a phase shift mask (PSM) version of mask 236, different features of the pattern formed on the PSM are configured to have appropriate phase differences to enhance resolution and image quality. In various examples, the PSM can be an attenuated PSM or an alternate PSM. The one or more masks produced by mask processing process 234 are used in various processes. For example, such one or more masks are used in an ion implantation process to form different doped regions in semiconductor wafer 238, in an etching process to form different etched regions in semiconductor wafer 238, and / or in other suitable processes.

[0196] Semiconductor device fabrication facility 228 includes wafer processing facilities 240. Semiconductor device fabrication facility 228 is a semiconductor device manufacturing industry that includes one or more production facilities for processing a variety of different semiconductor device products. In some embodiments, semiconductor device fabrication facility 228 is a semiconductor wafer foundry. For example, one facility may provide front-end of line (FEOL) processing for multiple semiconductor device products, a second facility may provide back-end of line (BEOL) processing for wiring and packaging of semiconductor device products, and a third facility may provide other services for the foundry industry.

[0197] The semiconductor device fabrication facility 228 utilizes one or more masks 236 produced by the mask department 226 to fabricate the semiconductor structure or semiconductor device 242 of the present disclosure. Thus, the semiconductor device fabrication facility 228 at least indirectly utilizes the semiconductor device design layout 230 to fabricate the semiconductor structure or semiconductor device 242 of the present disclosure. Furthermore, the semiconductor wafer 238 includes a silicon substrate or other suitable substrate having multiple material layers formed thereon, and further includes one or more differently doped regions, dielectric features, multi-level interconnects, and the like (formed by sub-fabrication operations). In some embodiments, the semiconductor wafer 238 processed by the semiconductor device fabrication facility 228 utilizing the one or more masks 236 is used to form the semiconductor structure or semiconductor device 242 of the present disclosure. In some embodiments, the semiconductor device fabrication process includes performing one or more lithographic exposures based at least indirectly on the semiconductor device design layout 230.

[0198] Disclosed embodiments include a semiconductor device including an OCC for providing a plurality of shift pulses for shifting a plurality of test patterns into or out of the device and a plurality of capture pulses for operating the device at at-speed. The OCC controls the number of clock pulses and the clock speed during the shift and capture phases. The number of clock pulses, such as the number of shift pulses and the number of capture pulses, can be any number of pulses and can exceed the number of shift registers in the OCC. In some embodiments, the test patterns are shifted into the device using shift pulses, and the device is operated using capture pulses, wherein the shift pulses are slow clock pulses and the capture pulses are fast clock pulses, and the number of fast clock pulses exceeds the number of shift registers in the OCC. In some embodiments, the test patterns are shifted into the device using shift pulses, wherein the shift pulses are slow clock pulses, and the device is operated using capture pulses, wherein the capture pulses are fast clock pulses followed by the shift pulses, wherein the shift pulses are slow clock pulses followed by more capture pulses, and wherein the capture pulses are fast clock pulses. In some embodiments, a test pattern is shifted into the device using a shift pulse, which is a slow clock pulse, and the device is operated using a capture pulse, which is a fast clock pulse immediately followed by the shift pulse, which is a fast clock pulse immediately followed by more capture pulses, which are fast clock pulses. In some embodiments, a test pattern that provides a maximum slew rate is shifted into the semiconductor device to provide a maximum slew rate in the shortest possible time. In some embodiments, a test pattern having a linked (0 / 1) pattern is shifted into the semiconductor device to provide a maximum slew rate for a longer period of time (e.g., for heat generation).

[0199] The disclosed embodiments further provide a method for acquiring power profile information on a semiconductor device. The method includes providing an OCC to control a clock speed for shifting multiple test patterns and capturing results; executing an automatic test pattern generation (ATPG) process to generate test patterns and report captured power; selecting a sequence of patterns or one of the test patterns based on the captured power; updating multiple signals to the OCC for use in a shift phase and a capture phase; executing a simulation to generate a vector change data (VCD) file; obtaining the captured power from the VCD file; determining whether the captured power meets a power requirement, and if the captured power does not meet the power requirement, repeating the steps of selecting, updating, executing, obtaining, and determining whether the captured power meets the power requirement; and preparing an input signal to automatic test equipment (ATE) if the captured power meets the power requirement.

[0200] Benefits of the disclosed embodiments include providing any number of fast or slow clock pulses without increasing the number of shift registers in the OCC, managing the sequence of multiple shift phases and multiple acquisition phases, acquiring multiple power profiles with a single test, and targeting any testable path of a semiconductor device for measurement and testing.

[0201] According to some embodiments, a semiconductor device includes an OCC configured to provide a clock output signal. The OCC is also configured to receive a mode signal and a speed enable signal and generate a first fast clock enable signal and a first slow clock enable signal. The OCC is configured to overwrite the first fast clock enable signal based on the mode signal and the speed enable signal to provide a fast clock in the clock output signal. The OCC is also configured to overwrite the first slow clock enable signal based on the mode signal and the speed enable signal to provide a slow clock in the clock output signal.

[0202] According to some embodiments, the OCC includes a first clock circuit configured to provide a second fast clock enable signal based on the mode signal, the speed enable signal, and the first fast clock enable signal, and to provide a second slow clock enable signal based on the mode signal, the speed enable signal, and the first slow clock enable signal. The OCC further includes a second clock circuit configured to receive the second fast clock enable signal and the second slow clock enable signal and provide the clock output signal.

[0203] According to some embodiments, the OCC includes a first clock circuit and a second clock circuit, wherein the first clock circuit includes a first AND gate and a second AND gate, the first AND gate having a first non-inverting input terminal and a second non-inverting input terminal, the second AND gate having a third non-inverting input terminal and an inverting input terminal, the first non-inverting input terminal and the third non-inverting input terminal receiving the mode signal, the second non-inverting input terminal and the inverting input terminal receiving the speed enable signal, wherein the first AND gate provides a first AND gate output signal, and the second AND gate provides a second AND gate output signal.

[0204] According to some embodiments, the first clock circuit includes a first OR gate and a second OR gate. The first OR gate receives the first AND gate output signal and the first fast clock enable signal and provides a second fast clock enable signal, while the second OR gate receives the second AND gate output signal and the first slow clock enable signal and provides a second slow clock enable signal. According to some embodiments, the second clock circuit receives the second fast clock enable signal, the second slow clock enable signal, a fast clock signal, and a slow clock signal and provides the clock output signal.

[0205] According to some embodiments, the second clock circuit includes a third AND gate and a fourth AND gate, wherein the third AND gate receives the second fast clock enable signal and the fast clock signal and provides a gated fast clock signal, and the fourth AND gate receives the second slow clock enable signal and the slow clock signal and provides a gated slow clock signal. The second clock circuit further includes a third OR gate for receiving the gated fast clock signal and the gated slow clock signal and providing the clock output signal.

[0206] According to some embodiments, when the mode signal is at a high level and the speed enable signal is at a high level, the OCC controls the clock output signal to oscillate at a fast clock speed. According to some embodiments, when the mode signal is at a high level and the speed enable signal is at a low level, the OCC controls the clock output signal to oscillate at a slow clock speed. According to some embodiments, the OCC controls the clock output signal to oscillate at the fast clock speed using the first fast clock enable signal at a high level, and controls the clock output signal to oscillate at the slow clock speed using the first slow clock enable signal at a high level.

[0207] According to other embodiments, a clock control circuit includes a first AND gate having a first non-inverting input and a second non-inverting input, the first non-inverting input being configured to receive a mode signal, and the second non-inverting input being configured to receive a speed enable signal; a second AND gate having a third non-inverting input and an inverting input, the third non-inverting input being configured to receive the mode signal, and the inverting input being configured to receive the speed enable signal; a first OR gate being configured to receive a first fast clock enable signal and a first AND gate output signal from the first AND gate, and being configured to output a second fast clock enable signal; and a second OR gate being configured to receive a first slow clock enable signal and a second AND gate output signal from the second AND gate, and being configured to output a second slow clock enable signal.

[0208] According to other embodiments, the clock control circuit further includes a third AND gate configured to receive the second fast clock enable signal and a fast clock signal, and configured to output a gated fast clock signal. According to other embodiments, the clock control circuit further includes a fourth AND gate configured to receive the second slow clock enable signal and a slow clock signal, and configured to provide a gated slow clock signal. According to other embodiments, the clock control circuit further includes a third OR gate configured to receive the gated fast clock signal and the gated slow clock signal, and configured to output a clock output signal.

[0209] According to yet other disclosed embodiments, a capture method for obtaining power file data on a semiconductor device includes: providing an OCC to control multiple clock speeds for shifting test patterns and capturing results; executing an ATPG process to generate multiple test patterns and report the capture power; selecting a sequence pattern, or selecting one of the test patterns based on the capture power; updating multiple signals to the OCC for multiple shift stages and multiple capture stages; utilizing an EDA tool to execute multiple simulations to generate a vector change data file for a capture cycle; utilizing the EDA tool or other EDA tools to obtain the capture power from the vector change data file for the capture cycle; determining whether the capture power meets the power requirement, and if the capture power does not meet the power requirement, repeating the multiple operations of selecting, updating, executing, obtaining, and determining whether the capture power meets the power requirement; and preparing an input signal to an ATE if the capture power meets the power requirement.

[0210] According to yet other disclosed embodiments, providing the OCC includes providing the OCC to provide at least four different clocks, including a slow clock, a fast clock, switching between a fast clock and a slow clock, and a clock providing a limited number of pulses. According to yet other disclosed embodiments, updating the signal to the OCC includes encoding a speed enable signal to provide a fast clock or activating a scan enable signal to shift in the test pattern.

[0211] According to yet other disclosed embodiments, if the extraction power is less than the power requirement, selecting one of the test patterns and updating the signal to the OCC includes changing the test pattern or the sequence pattern to increase the extraction power or increase the number of shift pulses between the extraction pulses, and if the extraction power is greater than the power requirement, selecting one of the test patterns and updating the signal to the OCC includes changing the test pattern or the sequence pattern to decrease the extraction power or reduce the number of fast clock shift pulses or utilize slow clock shift pulses. According to yet other disclosed embodiments, if the extraction power meets the power requirement, preparing the input signal includes utilizing a plurality of standard test interface language patterns or converting from vector change data to a waveform generation language for automatic test equipment.

[0212] This disclosure outlines numerous embodiments so that those skilled in the art may better understand the present disclosure from various perspectives. Those skilled in the art should understand and readily utilize this disclosure as a basis for designing or modifying other processes and structures that achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of this disclosure. Various changes, substitutions, or modifications may be made to this disclosure without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that: include: An on-chip clock controller is configured to provide a clock output signal, is configured to receive a mode signal and a speed enable signal, and is configured to generate a first fast clock enable signal and a first slow clock enable signal, The on-chip clock controller is configured to overwrite the first fast clock enable signal based on the mode signal and the speed enable signal to provide a fast clock in the clock output signal, and is configured to overwrite the first slow clock enable signal based on the mode signal and the speed enable signal to provide a slow clock in the clock output signal.

2. The semiconductor device according to claim 1, wherein The on-chip clock controller includes a first clock circuit and a second clock circuit. The first clock circuit is configured to provide a second fast clock enable signal based on the mode signal, the speed enable signal, and the first fast clock enable signal, and is configured to provide a second slow clock enable signal based on the mode signal, the speed enable signal, and the first slow clock enable signal. The second clock circuit receives the second fast clock enable signal and the second slow clock enable signal and provides the clock output signal.

3. The semiconductor device according to claim 1, wherein The on-chip clock controller further comprises: a first clock circuit, comprising: a first AND gate having a first non-inverting input terminal and a second non-inverting input terminal, wherein the first non-inverting input terminal receives the mode signal, and the second non-inverting input terminal receives the speed enable signal; a second AND gate having a third non-inverting input terminal and an inverting input terminal, wherein the third non-inverting input terminal receives the mode signal, and the inverting input terminal receives the speed enable signal; a first OR gate, configured to receive a first AND gate output signal and the first fast clock enable signal, and provide a second fast clock enable signal; and a second OR gate for receiving a second AND gate output signal and the first slow clock enable signal and providing a second slow clock enable signal; and a second clock circuit, comprising: a third AND gate for receiving the second fast clock enable signal and a fast clock signal and providing a gated fast clock signal; a fourth AND gate, configured to receive the second slow clock enable signal and a slow clock signal, and provide a gated slow clock signal; and a third OR gate for receiving the gated fast clock signal and the gated slow clock signal and providing the clock output signal; The first AND gate provides the first AND gate output signal, the second AND gate provides the second AND gate output signal, and the second clock circuit receives the second fast clock enable signal, the second slow clock enable signal, the fast clock signal, and the slow clock signal, and provides the clock output signal.

4. The semiconductor device according to claim 1, wherein When the mode signal is at a high level and the speed enable signal is at a high level, the on-chip clock controller controls the clock output signal to oscillate at a fast clock speed.

5. The semiconductor device according to claim 1, wherein When the mode signal is at a high level and the speed enable signal is at a low level, the on-chip clock controller controls the clock output signal to oscillate at a slow clock speed.

6. The semiconductor device according to claim 1, wherein The on-chip clock controller controls the clock output signal to oscillate at a fast clock speed using the first fast clock enable signal at a high level, and controls the clock output signal to oscillate at a slow clock speed using the first slow clock enable signal at a high level.

7. A clock control circuit, characterized in that: include: a first AND gate having a first non-inverting input terminal and a second non-inverting input terminal, wherein the first non-inverting input terminal is configured to receive a mode signal, and the second non-inverting input terminal is configured to receive a speed enable signal; a second AND gate having a third non-inverting input terminal and an inverting input terminal, wherein the third non-inverting input terminal is configured to receive the mode signal, and the inverting input terminal is configured to receive the speed enable signal; a first OR gate configured to receive a first fast clock enable signal and a first AND gate output signal from the first AND gate, and configured to output a second fast clock enable signal; as well as A second OR gate is configured to receive a first slow clock enable signal and a second AND gate output signal from the second AND gate, and is configured to output a second slow clock enable signal.

8. The clock control circuit according to claim 7, wherein: The device further includes a third AND gate configured to receive the second fast clock enable signal and a fast clock signal, and configured to output a gated fast clock signal.

9. The clock control circuit according to claim 8, wherein: The invention further includes a fourth AND gate configured to receive the second slow clock enable signal and a slow clock signal, and configured to provide a gated slow clock signal.

10. The clock control circuit according to claim 9, wherein: The invention further includes a third OR gate configured to receive the gated fast clock signal and the gated slow clock signal, and configured to output a clock output signal.

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