Semiconductor device

Abstract

A semiconductor device includes an n-type buried layer, a first N-well region, a p-type body region, a first source / drain region, a second source / drain region, a gate structure, a second N-well region and a first silicide region. The n-type buried layer is located in the substrate. The first N-well region is located above the n-type buried layer. The p-type body region is adjacent to the first N-well region. The first source / drain region is located in the first N-well region. The second source / drain region is located in the p-type body region. The gate structure extends across a boundary of the first N-well region and the p-type body region. The second N well region is located above the n-type buried layer. And the first silicide region and the second N well region form Schottky contact.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device with reverse current protection. Background Art

[0002] The semiconductor industry is experiencing rapid growth due to the increasing integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). This increase in integration density is largely due to the scaling of semiconductor process nodes (e.g., downscaling to nodes below 20 nanometers). As semiconductor devices continue to scale, new technologies are needed to maintain the performance of electronic components from one generation to the next. For example, low on-resistance and high breakdown voltage of transistors are desirable for various high-power applications. Utility Model Content

[0003] In some embodiments, a semiconductor device includes an n-type buried layer in a substrate; a first N-well region overlying the n-type buried layer; a p-type body region adjacent to the first N-well region; a first source / drain region in the first N-well region; a second source / drain region in the p-type body region; a gate structure extending across a boundary between the first N-well region and the p-type body region; a second N-well region overlying the n-type buried layer; and a first silicide region forming a Schottky contact with the second N-well region.

[0004] In some embodiments, a semiconductor device includes an n-type buried layer in a substrate; a first N-well region overlying the n-type buried layer; a p-type body region adjacent to the first N-well region; a first source / drain region in the first N-well region; a second source / drain region in the p-type body region; a gate structure extending across a boundary between the first N-well region and the p-type body region; a second N-well region overlying the n-type buried layer; a p-type region overlying the second N-well region; and a first silicide region interfacing with the p-type region.

[0005] In some embodiments, a semiconductor device includes a buried layer located in a substrate, the buried layer having a first conductivity type; a first well region located above the buried layer, the first well region having the first conductivity type; an integral region having a second conductivity type and forming a PN junction with the first well region; a first source / drain region located in the first well region; a second source / drain region located in the body region; a gate structure extending across a boundary between the first well region and the body region; a second well region located above the buried layer, the second well region having the first conductivity type; and a first silicide region forming a Schottky contact with the second well region. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure are best understood from the following detailed description in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 is a cross-sectional view of an integrated circuit (IC) structure having a high-voltage (HV) transistor according to some embodiments of the present disclosure;

[0008] Figure 2 For example Figure 1 Equivalent circuit diagram of the IC structure shown;

[0009] Figure 3 For example Figure 1 A top view of the IC structure is shown;

[0010] Figures 4 to 14 cross-sectional views illustrating intermediate stages in the formation of an IC structure according to some embodiments of the present disclosure;

[0011] Figure 15A A cross-sectional view of an IC structure according to some embodiments of the present disclosure is shown;

[0012] Figure 15B Some embodiments according to the present disclosure are shown as follows Figure 15A An enlarged top view of a portion of the IC structure is shown;

[0013] Figure 16 A cross-sectional view of an IC structure according to some embodiments of the present disclosure is shown;

[0014] Figure 17 For example Figure 16 The equivalent circuit diagram of the IC structure is shown.

[0015]

Explanation of symbols

[0016] 102: semiconductor substrate

[0017] 103:STI area

[0018] 104: n-type buried layer

[0019] 105: p-type epitaxial layer

[0020] 106a-106e: P-well region

[0021] 108a-108d: N-well region

[0022] 110a, 110b: deep P-well region

[0023] 112: p-type body region

[0024] 114d, 114s: n-type source / drain regions

[0025] 116: Gate electrode

[0026] 117: Gate dielectric layer

[0027] 118a~118e: heavily doped p-type region

[0028] 120, 122: Gate spacer

[0029] 124: RPO layer

[0030] 126: Silicide region

[0031] 128:Metal contact

[0032] 130: Inductive load

[0033] 131, 132: ILD layer

[0034] 134:Metal through hole

[0035] 136: Metal wire

[0036] 202: p-type doped region

[0037] 302, 304: p-type region

[0038] D1, D2: body diode

[0039] D3: Schottky diode

[0040] D4: PN diode

[0041] Deep PW: Deep P well region

[0042] GS1, GS2: Gate structure

[0043] IMP1, IMP5: n-type ion implantation process

[0044] IMP2, IMP3, IMP4: p-type ion implantation process

[0045] M1~M5: Patterned mask layer

[0046] N+: n-type source / drain region

[0047] NBL: n-type buried layer

[0048] NW: N well region

[0049] O1~O5: Open

[0050] OD: Active Zone

[0051] P+: heavily doped p-type region

[0052] P1, P2: Path

[0053] P-body: p-type body region

[0054] P-sub: p-type silicon substrate

[0055] PW: P well region

[0056] T1, T2: HV transistors

[0057] T3: Parasitic PNP transistor

[0058] VIN: Input voltage terminal

[0059] X, Y: direction DETAILED DESCRIPTION

[0060] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features so that the first and second features may not be in direct contact. In addition, the disclosure may repeat element symbols or letters in various examples. This repetition is for simplicity and clarity and does not, in itself, specify the relationship between the various embodiments or configurations discussed.

[0061] In addition, for ease of description, spatially relative terms such as "below," "beneath," "below," "above," and "above" may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientations depicted in the accompanying drawings. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. As used herein, "about," "approximately," or "substantially" may generally mean within 20%, or within 10%, or within 5% of a given value or range. The values ​​given herein are approximate, meaning that the terms "about," "about," "approximately," or "substantially" may be inferred unless explicitly stated. However, those skilled in the art will recognize that the values ​​or ranges listed throughout the description are merely examples and may decrease as integrated circuits shrink.

[0062] In high-voltage applications, such as overcurrent protection switches, the operation of metal-oxide-semiconductor (MOS) transistors poses a challenge during the transition from the "on" state to the "off" state. The core of the problem lies in the behavior of the inductive load connected to the transistor. The inductive load stores magnetic energy during operation. When the MOS transistor is suddenly turned off, the stored magnetic energy will seek a dissipation path, thereby generating a reverse current. This reverse current mainly flows from the source terminal of the transistor to the drain terminal through the body diode inherent in the substrate with the IC structure. The large current flowing through the body diode induces a parasitic bipolar junction transistor (BJT) effect, specifically a parasitic PNP transistor generated by multiple doped regions (for example, including a P-well, an n-type buried layer, and a p-type substrate) within the substrate with the IC structure. This induction may cause undesirable leakage current, or in severe cases, may cause thermal damage to the device or even burn out.

[0063] To address the aforementioned issues, the present disclosure, in various embodiments, involves integrating a Schottky diode (SBD) or PN diode into an integrated circuit. This diode is placed in series with the n-type body layer (NBL) located directly below the transistor. Consequently, when the transistor is turned off, the impedance of the path associated with the NBL increases due to the presence of the series SBD or PN diode. This increased impedance alters the path of the reverse current, favoring it through a different circuit loop that is typically unrelated to the parasitic PNP transistor. By directing the reverse current through this alternative path, the parasitic PNP transistor does not turn on because the conditions that cause it to activate are alleviated. Consequently, the risks associated with leakage current and thermal damage are significantly reduced, thereby maintaining the integrity and functionality of the transistor in high-voltage applications.

[0064] Figure 1 A cross-sectional view of an integrated circuit (IC) structure having high-voltage (HV) transistors (e.g., adjacent HV transistors T1 and T2) according to some embodiments of the present disclosure is provided. HV transistors T1 and T2 are semiconductor devices used to switch or amplify high-voltage signals. These transistors T1 and T2 are designed to handle and control much higher electrical power than standard transistors, making them suitable for applications that require managing high voltage levels. The ability to operate at high voltages makes these transistors T1 and T2 useful in a variety of power electronic devices, including power supplies, inverters, and overcurrent protection circuits.

[0065] The HV transistors T1 and T2 are formed on a semiconductor substrate 102. The semiconductor substrate 102 may include a semiconductor wafer, such as a silicon wafer. Alternatively, the semiconductor substrate 102 may include other elemental semiconductors, such as germanium. The semiconductor substrate 102 may also include a compound semiconductor, such as silicon carbide, gallium arsenide, indium arsenide, and indium phosphide. In addition, the semiconductor substrate 102 may include an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium arsenide, and gallium indium phosphide. In some embodiments, the semiconductor substrate 102 includes a p-type silicon substrate (p-substrate). Figure 1 It is marked as "P-sub".

[0066] A plurality of isolation regions 103, such as shallow trench isolation (STI) regions or local oxidation of silicon (LOCOS) (or field oxide (FOX)) regions including isolation features, may be formed in the substrate 102 to define and electrically isolate the active regions, thereby preventing leakage current from flowing between adjacent active regions.

[0067] The n-type buried layer 104 is located in the substrate 102 and below the STI region 103. Figure 1 The NBL 104 is labeled "NBL" in the figure. This layer 104 is buried below other doped regions (e.g., well regions) in the substrate 102 and is therefore referred to as a "buried layer." In some embodiments, the NBL 104 is formed by implanting n-type dopants, such as phosphorus or arsenic, into predetermined regions within the substrate 102 to isolate the device from the substrate 102.

[0068] In the range of the STI region 103, a plurality of well regions are formed, including P well regions 106a to 106e (in Figure 1 Marked as "PW") and N well regions 108a-108d (in Figure 1 ). These well regions are doped regions, with P-well regions 106a-106e doped with p-type dopants (e.g., boron, boron fluoride, indium, etc.), and N-well regions 108a-108d doped with n-type dopants (e.g., phosphorus, arsenic, antimony, etc.). The P-well regions 106a-106e and the N-well regions 108a-108d are arranged alternately. In other words, the P-well regions 106a-106e and the N-well regions 108a-108d are arranged in an alternating order, meaning that in the horizontal direction of the entire substrate 102, each P-well region is followed by an N-well region, and vice versa. In some embodiments, HV transistor T1 has a footprint on N-well region 108b, and HV transistor T2 has a footprint on N-well region 108c.

[0069] In some embodiments, deep P-well regions 110a and 110b (in Figure 1Deep P-well regions (labeled "Deep PW") are formed deeper within substrate 102, further enhancing the isolation characteristics of the IC structure. Deep P-well regions 110a and 110b are buried beneath N-well regions 108b and 108c, respectively. These deep P-well regions 110a and 110b are heavily doped with p-type dopants and help prevent latch-up by providing robust isolation between n-type regions of the IC structure.

[0070] A p-type body region 112 is provided between the N-well region 108b and the N-well region 108c. The p-type body region 112 forms the channel region of the adjacent n-type HV transistors T1 and T2. Figure 1 The n-type source region 114s of the HV transistor T1 and the n-type source region 114s of the HV transistor T2 are formed in the p-type body region 112. The n-type drain region 114d of the HV transistor T1 and the n-type drain region 114d of the HV transistor T2 are formed in the N-well regions 108b and 108c, respectively. The n-type source region 114s and the n-type drain region 114d may be collectively referred to as the n-type source / drain region 114s / 114d. Figure 1 This allows electrons to flow from the source region to the drain region under the control of the corresponding gate electrode 116 of the HV transistor. Source / drain region may refer to the source region or the drain region individually or collectively, depending on the context.

[0071] The gate electrodes 116 of transistors T1 and T2 are disposed above the channel region defined by the p-type body region 112. In some embodiments, gate electrode 116 is formed of a conductive material, such as polysilicon or metal. Gate electrodes 116 are separated from the channel region within the p-type body region 112 by respective gate dielectric layers 117. These gate dielectric layers 117 may comprise silicon dioxide or a high-k material, isolating gate electrodes 116 and ensuring effective control of the transistors by modulating the electric field within the channel region. In some embodiments, the gate electrode 116 of transistor T1 extends laterally from above the p-type body region 112 to above the N-well region 108 b, while the gate electrode 116 of transistor T2 extends laterally from above the p-type body region 112 to above the N-well region 108 c. In some embodiments, gate electrode 116 extends from the p-type body region 112 to the N-well region 108 b or 108 c by a gate length in a range of approximately 0.7 μm to approximately 3 μm.

[0072] The sidewalls of the gate electrode 116 are enclosed by gate spacers 120 and 122 formed of a dielectric material, such as silicon nitride or oxide. The gate spacers 122 define the lateral boundaries of the source region 114s and protect the gate sidewalls during the ion implantation process, thereby maintaining the integrity of the gate structure.

[0073] In some embodiments, a resist protection oxide (RPO) layer 124 is formed over each gate electrode 116. The RPO layer 124 can serve as a silicide barrier during a subsequent self-aligned silicidation (also known as self-aligned polysilicide) process. More specifically, the RPO layer 124 covers surfaces where silicide will not form. More specifically, the RPO layer 124 covers portions of each gate electrode 116 and each N-well region 108 b and 108 c, while simultaneously exposing portions of each gate electrode 116 and each N-well region 108 b and 108 c to form silicide regions 126.

[0074] Heavily doped p-type regions 118a, 118b, 118d, and 118e are formed in the P-well regions 106a, 106b, 106d, and 106d, respectively. A heavily doped p-type region 118c is formed in the p-type body region 112 and is laterally located between the source regions 114s of the adjacent transistors T1 and T2. Figure 1 The dopant concentrations in these heavily doped p-type regions (labeled "P+") are appropriately controlled to form ohmic contacts with the metal elements in the corresponding metal silicide regions 126 and metal contacts 128. The dopant concentrations in these heavily doped p-type regions are carefully controlled to ensure minimal resistance to electron flow, thereby facilitating an efficient charge transfer process. An ohmic contact is an electrical junction between two materials (such as a semiconductor and a metal) through which current can flow easily in both directions without significant resistance. This type of contact has a linear current-voltage (IV) relationship, meaning that the resistance remains constant regardless of the direction of current flow. This is in contrast to a rectifying contact (such as a Schottky contact), where the IV characteristics are nonlinear and the contact acts more like a diode (also known as a Schottky diode (SBD)), allowing current to flow more easily in one direction.

[0075] The heavily doped p-type regions 118a-118e have a higher p-type impurity concentration than the P-well regions 106a-106e, thereby forming an ohmic contact with the heavily doped p-type regions 118a-118e. Similarly, the n-type drain region 114d has a higher n-type impurity concentration than the N-well regions 108a-108d, and the n-type source region 114s has a higher n-type impurity concentration than the p-type body region 112, thereby forming an ohmic contact with the n-type source / drain regions 114s / 114d. In some embodiments, the width of each source / drain region 114s / 114d ranges from approximately 0.4 μm to approximately 2 μm. In some embodiments, the width of the SIT region 103 between the drain region 114d and the heavily doped p-type region 118b ranges from approximately 6 μm to approximately 7 μm.

[0076] Silicide regions 126 are formed over n-type source / drain regions 114s / 114d, heavily doped p-type regions 118a-118e, N-well regions 108a, 108d, and gate electrode 116 to reduce contact resistance between these regions and overlying contacts 128. Contacts 128 are formed over respective silicide regions 126 to provide electrical connections between transistors T1 and T2 and other circuit elements. The source regions 114s of transistors T1 and T2 and the heavily doped p-type region 118c therebetween share the same silicide region 126 and contact 128.

[0077] exist Figure 1 In the embodiment, N-well region 108a is in direct contact with silicide region 126, while N-well region 108d is in direct contact with another silicide region 126. Because N-well regions 108a and 108d have a lower dopant concentration (i.e., impurity concentration) than source / drain regions 114s / 114d and heavily doped p-type regions 118a-118e, N-well regions 108a and 108d form Schottky contacts, rather than ohmic contacts, with the overlying metal elements in silicide region 126 and metal contact 128. In some embodiments, the ratio of the dopant concentration in source / drain regions 114s / 114d (i.e., N+ regions) to the dopant concentration in N-well regions 108a and 108d is in a range of approximately 10 to 1000. In other words, the dopant concentration in the N-well regions 108a and 108d is at least one order of magnitude lower than the dopant concentration in the source / drain regions 114s and 114d. Due to the difference in dopant concentration, the N-well regions 108a and 108d can form Schottky contacts with the overlying metal elements, while the source / drain regions 114s and 114d can form ohmic contacts with the overlying metal elements.

[0078] A Schottky contact refers to the junction formed between a metal and a semiconductor material. A Schottky contact exhibits unidirectional current flow characteristics, allowing electrons to move more freely in one direction than in the other, resulting in rectifying behavior. This behavior is primarily due to the difference in work function between the semiconductor (i.e., the semiconductor elements in N-well regions 108a, 108d) and the metal (i.e., the metal elements in silicide region 126 and metal contact 128). By utilizing a Schottky contact, a Schottky diode is created at the junction between the N-well regions 108a, 108d and the silicide region 126. Because the N-well regions 108a, 108d are in direct contact with the top surface of the NBL 104, the Schottky diode is connected in series with the NBL 104 to prevent the inadvertent activation of a parasitic PNP transistor (e.g., the PNP transistor formed by deep P-well regions 110a / 110b, NBL 104, and p-type substrate 102), as will be discussed in more detail below. In some embodiments where HV transistors T1 and T2 have an operating voltage of approximately 55 V, the lateral dimension of the Schottky diode is approximately 0.4 μm to approximately 0.6 μm. In other words, the width of the top surface of N-well region 108 a is in the range of approximately 0.4 μm to approximately 0.6 μm.

[0079] Figure 2 for Figure 1 The equivalent circuit diagram of the IC structure is shown. Figure 2 A high-voltage overcurrent protection switch circuit according to some embodiments of the present disclosure is illustrated. The circuit includes an HV transistor T1, whose source terminal (i.e., source region 114s) is electrically connected to an inductive load 130, and whose drain terminal is electrically connected to an input voltage terminal (VIN). The inductive load 130 is a two-terminal device, wherein a first terminal is connected to the source terminal of the HV transistor T1 and a second terminal is grounded. In some embodiments, the inductive load 130 is a coil or inductor that stores energy in the form of a magnetic field when current flows through it. This characteristic allows the operation of various devices and circuits, including boost converters, flyback converters, H-bridge motor drives, and LLC resonant converters. These applications utilize the characteristics of inductors to perform functions such as voltage conversion, energy transfer, and motor control. For example, a boost converter increases the input voltage to a higher output voltage, a flyback converter provides current isolation and voltage conversion, an H-bridge allows motor direction control, and an LLC resonant converter provides efficient power conversion while minimizing losses.

[0080] When HV transistor T1 is turned off, the magnetic energy stored in inductive load 130 seeks a dissipation path, causing reverse current to flow from inductive load 130 back to input voltage terminal VIN. This reverse current can take two paths, labeled P1 and P2. Path P1 passes through a body diode D1 formed by the PN junction of p-type body region 112 and N-well region 108b. Path P1 then passes through n-type drain region 114d and an overlying contact to input voltage terminal VIN. Path P2 passes through another body diode D2 formed by the PN junction of P-well region 106c and NBL 104. Path P2 then passes through N-well region 108a and an overlying contact to input voltage terminal VIN. When current flows along path P2, it may inadvertently activate parasitic PNP transistor T3 formed by deep P-well region 110b, NBL 104, and p-type substrate 102. The activation of parasitic PNP transistor T3 may result in undesirable leakage current. However, the presence of Schottky diode D3, formed by the semiconductor elements in N-well region 108a and the overlying metal elements, mitigates this risk. When Schottky diode D3 is connected in series with NBL 104 on path P2, the impedance of path P2 is significantly increased compared to path P1. This increased impedance effectively blocks current from flowing through path P2, thereby preventing activation of parasitic PNP transistor T3. Consequently, potential problems associated with leakage current are reduced.

[0081] Furthermore, when HV transistor T1 is turned on, the presence of Schottky diode D3 does not adversely affect circuit performance. This is because the forward voltage drop of Schottky diode D3 connected to the drain terminal of HV transistor T1 is low. In some embodiments, the forward voltage drop of Schottky diode D3 is in the range of approximately 0.1 volts to approximately 0.3 volts.

[0082] Figure 3 for Figure 1 A top view of an IC structure is shown. In the top view, the active region OD has a rectangular pattern extending along the X direction, and the gate electrode 116 has a rectangular pattern extending across the active region OD along the Y direction perpendicular to the X direction. The source / drain regions 114s / 114d and the heavily doped p-type region 118c are formed in the active region and extend along the Y direction. From a top view, the first STI region 103 has a continuous annular pattern surrounding the active region OD and the gate electrode 116. The heavily doped p-type regions 118 b and 118 d together form a continuous annular pattern surrounding the first STI region 103. The second STI region 103 has a continuous annular pattern surrounding the heavily doped p-type regions 118 b and 118 d. The N-well regions 108 a and 108 d together form a continuous annular pattern surrounding the second STI region 103. The third STI region 103 has a continuous annular pattern surrounding the N-well regions 108 a and 108 d. The heavily doped p-type regions 118 a and 118 e together form a continuous annular pattern surrounding the third STI region 103.

[0083] Figures 4 to 14 A cross-sectional view of an intermediate stage of IC structure formation according to some embodiments of the present disclosure is shown. In the various views and illustrative embodiments, like reference numerals are used to represent like elements. It should be understood that additional embodiments of the method may be used in the following embodiments. Figures 4 to 14 Additional operations are provided before, during, and after the processes shown, and some of the operations described below may be replaced or eliminated. The order of the operations / processes may be interchanged.

[0084] Figure 4 A cross-sectional view of the initial structure is shown. The initial structure includes a semiconductor substrate 102. The semiconductor substrate 102 may include a semiconductor wafer, such as a silicon wafer. Alternatively, the semiconductor substrate 102 may include other elemental semiconductors, such as germanium. The semiconductor substrate 102 may also include a compound semiconductor, such as silicon carbide, gallium arsenide, indium arsenide, and indium phosphide. In addition, the semiconductor substrate 102 may include an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium arsenide phosphide, and indium gallium phosphide. In some embodiments, the semiconductor substrate 102 includes a p-type silicon substrate (p-substrate). Figure 4 In some embodiments, the p-type substrate 102 has a thickness in a range of about 500 μm to about 10,000 μm and a resistivity in a range of about 10 ohm-cm to about 100 ohm-cm.

[0085] Figure 4 Also illustrated is an NBL 104 formed in substrate 102. NBL 104 can be formed, for example, by a lithography process followed by an ion implantation process. For example, a patterned mask layer can be formed over substrate 102 to define the location of NBL 104, which will be subsequently formed in substrate 102. The patterned mask layer can include an organic material, such as a photoresist material, and can be formed using a spin-coating process. The photoresist material is then patterned using a suitable lithography technique to form one or more openings extending through the patterned mask layer to expose target areas of substrate 102. For example, the photoresist material is irradiated (exposed) and developed to remove portions of the photoresist material. More specifically, a photomask (not shown) can be placed over the photoresist material, which can then be exposed to a radiation beam, such as ultraviolet (UV) light or an excimer laser, such as a krypton fluoride (KrF) excimer laser or an argon fluoride (ArF) excimer laser. For example, exposure of the photoresist material can be performed using an immersion lithography tool or an extreme ultraviolet light (EUV) tool to increase resolution and reduce the minimum achievable pitch. A bake or cure operation can be performed to harden the exposed photoresist material, and a developer can be used to remove the exposed or unexposed portions of the photoresist material, depending on whether a positive or negative photoresist is used.

[0086] Next, with the patterned mask layer in place, an n-type ion implantation process is performed to dope n-type impurities (e.g., phosphorus, arsenic, antimony, etc.) into the p-type substrate 102 to form the NBL 104. The n-type ion implantation is performed using the patterned mask layer as an implantation mask so that the NBL 104 has a top view pattern or geometry that inherits the top view pattern or geometry of the opening of the patterned mask layer. In this way, the top view pattern of the opening can be designed to define the desired top view pattern of the NBL 104. In some embodiments, the n-type ion implantation process of the NBL 104 is performed at a density of approximately 1E13 atoms / cm 2 to about 1E14 atoms / cm 2 The n-type impurities are implanted with a dosage of about 100 keV and an energy of about 50 keV to about 100 keV.

[0087] After forming the NBL 104, the patterned mask layer is removed, for example, using a plasma ashing process. In some embodiments, the plasma ashing process is performed such that the temperature of the photoresist mask is increased until the photoresist mask undergoes thermal decomposition and can be removed. However, any other suitable process, such as wet stripping, may be used.

[0088] Subsequently, a p-type epitaxial layer 105 is formed over the p-type substrate 102 and the NBL 104. In some embodiments, the p-type epitaxial layer 105 is a crystalline semiconductor material (e.g., silicon, germanium, or silicon germanium) formed using a suitable epitaxial growth method, such as vapor phase epitaxy (VPE), solid phase epitaxy (SPE), liquid phase epitaxy (LPE), metal-organic CVD (MOCVD), or molecular beam epitaxy (MBE). A dose of p-type impurities (e.g., boron, boron fluoride, indium, etc.) is introduced into the epitaxially grown material in situ during epitaxial growth or through an ion implantation process performed after epitaxial growth, or a combination thereof. In some embodiments, the p-type epitaxial layer 105 has a thickness ranging from about 5 μm to about 10 μm and a resistivity ranging from about 10 ohm-cm to about 100 ohm-cm, which helps prevent leakage and improve breakdown voltage.

[0089] After forming the p-type epitaxial layer 105, an isolation structure 103 is formed in the p-type epitaxial layer 105, such as an isolation feature, a shallow trench isolation (STI) region or a local oxidation of silicon (LOCOS) (or field oxide (FOX)) region, to define and electrically isolate the active regions, thereby preventing leakage current from flowing between adjacent active regions. As an example, the formation of the STI feature may include dry etching a trench in the substrate and filling the trench with an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. The filled trench may have a multi-layer structure, such as a thermal oxide liner layer filled with silicon nitride or silicon oxide. In some other embodiments, the STI structure may be created using a process sequence such as growing a pad oxide, forming a low pressure chemical vapor deposition (LPCVD) nitride layer, patterning the STI opening using a photoresist and a mask, etching a trench in the substrate, optionally growing a thermal oxide trench liner to improve the trench interface, filling the trench with CVD oxide, etching back and planarizing using a chemical mechanical polishing (CMP) process, and removing the silicon nitride using a nitride strip process.

[0090] exist Figure 5 In the embodiment of the present invention, a patterned mask layer M1 is formed over the p-type epitaxial layer 105 to define the location of the N-well region 108a to be formed in a subsequent implantation process. The patterned mask layer M1 may include an organic material, such as a photoresist material, and may be formed using a spin coating process. The photoresist material is then patterned using a suitable lithography technique to form one or more openings O1 extending through the patterned mask layer M1 to expose the N-well target region within the p-type epitaxial layer 105. For example, the photoresist material is irradiated (exposed) and developed to remove portions of the photoresist material. In more detail, a photomask (not shown) may be placed over the photoresist material, which may then be exposed to a radiation beam, such as an ultraviolet (UV) or excimer laser, such as a krypton fluoride (KrF) excimer laser or an argon fluoride (ArF) excimer laser. For example, exposure of the photoresist material can be performed using an immersion lithography tool or an extreme ultraviolet light (EUV) tool to increase resolution and reduce the minimum achievable pitch. A bake or cure operation can be performed to harden the exposed photoresist material, and a developer can be used to remove the exposed or unexposed portions of the photoresist material, depending on whether a positive or negative photoresist is used.

[0091] Next, with the patterned mask layer M1 in place, an n-type ion implantation process IMP1 is performed to dope n-type impurities (e.g., phosphorus, arsenic, antimony, etc.) into the p-type epitaxial layer 105 to form N-well regions 108a to 108d. These N-well regions 108a to 108d may be collectively referred to as N-well regions 108. The n-type ion implantation IMP1 is performed using the patterned mask layer M1 as an implantation mask so that the top view pattern or geometry of each N-well region 108 inherits the top view pattern or geometry of the corresponding opening O1 of the patterned mask layer M1. In this way, the top view pattern of the opening O1 can be designed to define the desired top view pattern of the N-well regions 108a to 108d. In some embodiments, the n-type ion implantation process IMP1 is performed at a rate of approximately 1E12 atoms / cm 2 to about 1E13 atoms / cm 2 The n-type impurities are implanted with a dosage of about 50 KeV and an energy of about 3000 KeV.

[0092] In some embodiments, the n-type impurity concentration of N-well regions 108a-108d is less than the n-type impurity concentration of NBL 104, for example, at least one order of magnitude lower. In some embodiments, the pattern of patterned mask layer M1 is designed so that all N-well regions 108a-108d vertically overlap with NBL 104. Specifically, the right sidewall boundary of NBL 104 is aligned with the right sidewall boundary of N-well region 108d, and the left sidewall boundary of NBL 104 is aligned with the left sidewall boundary of N-well region 108a. As a result, NBL 104 is electrically coupled to N-well regions 108a-108d, thereby allowing the Schottky diodes formed in N-well regions 108a and 108d to be electrically connected in series. In some embodiments, the depth P1 of each N-well region 108 is substantially the same as the thickness of p-type epitaxial layer 105. In other words, each N-well region 108 vertically extends through the entire thickness of the p-type epitaxial layer 105 and terminates at the top surface of the NBL 104 .

[0093] exist Figure 6 In the embodiment of the present invention, after forming the N-well region 108, the patterned mask layer M1 is removed, for example, using a plasma ashing process. In some embodiments, the plasma ashing process is performed such that the temperature of the photoresist mask M1 is increased until the photoresist mask M1 undergoes thermal decomposition and can be removed. However, any other suitable process, such as wet stripping, may be used.

[0094] Next, another patterned mask layer M2 is formed over the p-type epitaxial layer 105 to define the location of the p-well region 106 to be formed in subsequent processing. The patterned mask layer M2 may include an organic material, such as a photoresist material, and may be formed using a spin-coating process. The photoresist material is then patterned using a suitable lithography technique to form one or more openings O2 extending through the patterned mask layer M2, thereby exposing the p-well target region within the p-type epitaxial layer 105. For example, the photoresist material is irradiated (exposed) and developed to remove portions of the photoresist material. More specifically, a photomask (not shown) may be placed over the photoresist material, which may then be exposed to a radiation beam, such as ultraviolet (UV) light or an excimer laser, such as a krypton fluoride (KrF) excimer laser or an argon fluoride (ArF) excimer laser. Exposure of the photoresist material can be performed, for example, using an immersion lithography tool or an extreme ultraviolet light (EUV) tool to increase resolution and reduce the minimum achievable pitch. A bake or cure operation can be performed to harden the exposed photoresist material, and a developer can be used to remove the exposed or unexposed portions of the photoresist material, depending on whether a positive or negative photoresist is used.

[0095] Next, with the patterned mask layer M2 in place, a p-type ion implantation process IMP2 is performed to dope p-type impurities (e.g., boron, boron fluoride, indium, etc.) into the p-type epitaxial layer 105 to form P-well regions 106a-106e alternating with the N-well regions 108a-108d. The p-type ion implantation IMP2 is performed using the patterned mask layer M2 as an implantation mask so that the top view pattern or geometry of each P-well region 106 inherits the top view pattern or geometry of the corresponding opening O2 of the patterned mask layer M2. In this way, the top view pattern of the opening O2 can be designed to define the desired top view pattern of the P-well region 106. In some embodiments, a p-type ion implantation process IMP3 is performed at a rate of approximately 1E12 atoms / cm 2 to about 1E13 atoms / cm 2 The p-type impurities are implanted with a dosage of about 50 KeV to about 3000 KeV.

[0096] In some embodiments, the p-type impurity concentration of each of the p-well regions 106a-106e is lower than the n-type impurity concentration of the NBL 104, for example, by at least one order of magnitude. In some embodiments, the pattern of the patterned mask layer M2 is designed such that the p-well regions 106b, 106c, and 106d vertically overlap the NBL 104, while the p-well regions 106a and 106e do not overlap the NBL 104. In some embodiments, each p-well region 106 has a depth P2 that is substantially the same as the thickness of the p-type epitaxial layer 105. In other words, the p-well region 106 vertically extends through the entire thickness of the p-type epitaxial layer 105 and terminates at the top surface of the p-type substrate 102 or the top surface of the NBL 104. Because the n-well region 108 also vertically extends through the entire thickness of the p-type epitaxial layer 105, the bottom surface of the n-well region 108 is flush with the bottom surface of the p-well region 106. In some embodiments, after the ion implantation process, an annealing process may be performed on the substrate 102 to activate dopants in the well region.

[0097] exist Figure 7 In the embodiment of the present invention, after forming the P-well region 106, the patterned mask layer M2 is removed, for example, using a plasma ashing process. In some embodiments, the plasma ashing process is performed such that the temperature of the photoresist mask M2 is increased until the photoresist mask M2 undergoes thermal decomposition and can be removed. However, any other suitable process, such as wet stripping, may be used.

[0098] Next, another patterned mask layer M3 is formed over the p-type epitaxial layer 105 to define the locations of the deep P-well regions 110a and 110b to be formed in a subsequent implantation process. The patterned mask layer M3 may comprise an organic material, such as a photoresist material, and may be formed using a spin-coating process. The photoresist material is then patterned using a suitable lithography technique to form one or more openings O3 extending through the patterned mask layer M3, thereby exposing the deep P-well target region within the p-type epitaxial layer 105. For example, the photoresist material is irradiated (exposed) and developed to remove portions of the photoresist material. More specifically, a mask (not shown) may be placed over the photoresist material, which may then be exposed to a radiation beam, such as ultraviolet (UV) light or an excimer laser, such as a krypton fluoride (KrF) excimer laser or an argon fluoride (ArF) excimer laser. Exposure of the photoresist material can be performed, for example, using an immersion lithography tool or an extreme ultraviolet light (EUV) tool to increase resolution and reduce the minimum achievable pitch. A bake or cure operation can be performed to harden the exposed photoresist material, and a developer can be used to remove the exposed or unexposed portions of the photoresist material, depending on whether a positive or negative photoresist is used.

[0099] Next, with the patterned mask layer M3 in place, a p-type ion implantation process IMP3 is performed to dope p-type impurities (e.g., boron, boron fluoride, indium, etc.) into the p-type epitaxial layer 105 to form deep P-well regions 110a and 110b directly below the N-well regions 108b and 108c. The p-type ion implantation IMP3 is performed using the patterned mask layer M3 as an implantation mask so that the top view pattern or geometry of each deep P-well region 110a, 110b inherits the top view pattern or geometry of the corresponding opening O3 of the patterned mask layer M3. In this way, the top view pattern of the opening O3 can be designed to define the desired top view pattern of the deep P-well regions 110a, 110b. In some embodiments, the p-type ion implantation process IMP3 is performed at a rate of approximately 1E12 atoms / cm 2 to about 1E13 atoms / cm 2 The p-type impurities are implanted at a dose of about 1000 keV and an energy of about 200 keV to about 500 keV.

[0100] exist Figure 8 In the embodiment of the present invention, a p-type body region 112 is formed in the P-well region 106c. The p-type body region 112 can be formed by, for example, a lithography process followed by an ion implantation process. For example, a patterned mask layer can be formed over the substrate 102 to define the location of the p-type body region 112 to be subsequently formed in the substrate 102. The patterned mask layer can include an organic material, such as a photoresist material, and can be formed using a spin coating process. The photoresist material is then patterned using a suitable lithography technique to form one or more openings extending through the patterned mask layer to expose target areas of the substrate 102. For example, the photoresist material is irradiated (exposed) and developed to remove portions of the photoresist material. In more detail, a photomask (not shown) can be placed over the photoresist material, which can then be exposed to a radiation beam, such as an ultraviolet (UV) or excimer laser, such as a krypton fluoride (KrF) excimer laser or an argon fluoride (ArF) excimer laser. For example, exposure of the photoresist material can be performed using an immersion lithography tool or an extreme ultraviolet light (EUV) tool to increase resolution and reduce the minimum achievable pitch. A bake or cure operation can be performed to harden the exposed photoresist material, and a developer can be used to remove the exposed or unexposed portions of the photoresist material, depending on whether a positive or negative photoresist is used.

[0101] Next, with the patterned mask layer in place, a p-type ion implantation process is performed to dope p-type impurities (e.g., boron, boron fluoride, indium, etc.) into the P-well region 106c to form the p-type body region 112. The p-type ion implantation is performed using the patterned mask layer as an implantation mask so that the top view pattern or geometry of the p-type body region 112 inherits the top view pattern or geometry of the corresponding opening of the patterned mask layer. In this way, the top view pattern of the opening can be designed to define the desired top view pattern of the p-type body region 112. In some embodiments, the p-type ion implantation process is performed at a density of approximately 1E13 atoms / cm 2 to about 1E14 atoms / cm 2 The p-type impurities are implanted at a dose of 100 keV and an energy of about 30 keV to about 300 keV. In some embodiments, the width of the p-type body region 112 is in a range from about 1.1 μm to about 1.6 μm. Because the p-type body region 112 is implanted with the p-type impurities in two implantation steps, including the ion implantation process IMP2 and the ion implantation process for forming the p-type body region 112, the p-type body region 112 has a higher p-type impurity concentration than the P-well regions 106 a to 106 e.

[0102] After forming the p-type body region 112, gate structures GS1 and GS2 are formed over the substrate 102. Specifically, a gate dielectric layer 117 is formed over the p-type body region 112, and then a gate electrode 116 is formed over each gate dielectric layer 117. The gate dielectric layer 117 and the overlying gate electrode 116 collectively serve as the gate structure GS1, which extends from over the p-type body region 112 to over the N-well region 108 b. The gate dielectric layer 117 and the overlying gate electrode 116 collectively serve as the gate structure GS2, which extends from over the p-type body region 112 to over the N-well region 108 c. In some embodiments, gate structures GS1 and GS2 are formed by, for example, growing an oxide layer on the top surface of the p-type epitaxial layer 105 using a thermal oxidation process or an in-situ steam generation (ISSG) process, depositing a gate electrode layer over the oxide layer, and then patterning the gate electrode layer and the oxide layer into a gate electrode 116 and a gate dielectric layer 117 using appropriate lithography and etching techniques.

[0103] exist Figure 9In the embodiment of the present invention, gate spacers 120 and 122 are formed on opposite sidewalls of gate structures GS1 and GS2. Spacers 120 and 122 can be formed by, for example, conformally forming one or more layers of spacer material on p-type epitaxial layer 105 using a suitable deposition technique (e.g., CVD, ALD, or a combination thereof), and then etching the one or more layers of spacer material using an anisotropic etching process. The anisotropic etching process removes horizontal portions of the one or more layers of spacer material, while leaving vertical portions of the one or more layers of spacer material on the sidewalls of gate structures GS1 and GS2. The remaining spacer material on N-well region 108b can be referred to as gate spacer 120, while the remaining spacer material on p-type body region 112 can be referred to as gate spacer 122. In some embodiments, the anisotropic etching process for forming the gate spacers is an RIE process using a plasma generated by CHF3 gas and / or Cl2 gas. In some embodiments, gate spacers 120 and 122 include silicon nitride (Si3N4), although other materials may be used, such as silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbon oxynitride, silicon oxycarbide, porous dielectric material, hydrogen-doped silicon oxycarbide (SiOC:H), low-k dielectric material, or other suitable dielectric material.

[0104] After forming gate spacers 120 and 122, a resist protection oxide (RPO) layer 124 is formed on gate structures GS1 and GS2, respectively. RPO layer 124 is formed to cover a portion of the top surface of gate electrode 116 of gate structure GS1, while leaving another portion of the top surface of gate electrode 116 exposed. RPO layer 124 is formed to cover a portion of the top surface of gate electrode 116 of gate structure GS2, while leaving another portion of the top surface of gate electrode 116 exposed. RPO layer 124 extends laterally along the top surfaces of N-well regions 108 b and 108 c and terminates before reaching STI region 103. RPO layer 124 can be formed by, for example, depositing an oxide layer (e.g., a SiO2 layer) on gate structures GS1 and GS2 and p-type epitaxial layer 105, and then patterning the oxide layer into RPO layer 124 using a suitable etching technique (e.g., dry etching, wet etching, or a combination thereof). The RPO layer 124 may serve as a silicide blocking layer in a subsequent self-aligned silicidation (also referred to as salicide) process.

[0105] exist Figure 10In the embodiment of the present invention, a patterned mask layer M4 is formed over the p-type epitaxial layer 105 to define the locations of heavily doped p-type regions 118a-118e to be formed in subsequent processing. The patterned mask layer M4 may include an organic material, such as a photoresist material, and may be formed using a spin coating process. The photoresist material is then patterned using a suitable lithography technique to form one or more openings O4 extending through the patterned mask layer M4 to expose target regions within the p-type epitaxial layer 105. For example, the photoresist material is irradiated (exposed) and developed to remove portions of the photoresist material. In more detail, a mask (not shown) may be placed over the photoresist material, which may then be exposed to a radiation beam, which may be an ultraviolet (UV) or excimer laser, such as a krypton fluoride (KrF) excimer laser or an argon fluoride (ArF) excimer laser. Exposure of the photoresist material can be performed, for example, using an immersion lithography tool or an extreme ultraviolet light (EUV) tool to increase resolution and reduce the minimum achievable pitch. A bake or cure operation can be performed to harden the exposed photoresist material, and a developer can be used to remove the exposed or unexposed portions of the photoresist material, depending on whether a positive or negative photoresist is used.

[0106] Next, with the patterned mask layer M4 in place, a p-type ion implantation process IMP4 is performed to dope p-type impurities (e.g., boron, boron fluoride, indium, etc.) into the p-type epitaxial layer 105 to form heavily doped p-type regions 118a, 118b, 118d, and 118e in the p-well regions 106a, 106b, 106d, and 106e, respectively, and a heavily doped p-type region 118c in the p-body region 112. The p-type ion implantation IMP4 is performed using the patterned mask layer M4 as an implantation mask so that the top view pattern or geometry of each heavily doped p-type region 118 inherits the top view pattern or geometry of the corresponding opening O4 of the patterned mask layer M4. In this way, the top view pattern of the opening O4 can be designed to define the desired top view pattern of the heavily doped p-type region 118. In some embodiments, the p-type ion implantation process IMP4 is performed at a density of approximately 1E14 atoms / cm 2 to about 1E15 atoms / cm 2 The p-type impurities are implanted with a dose of about 10 KeV to about 50 KeV and an energy of about 10 KeV. The p-type impurity concentration of the heavily doped p-type regions 118a to 118e is higher than that of the P-well regions 106a to 106e by, for example, at least one order of magnitude.

[0107] exist Figure 11After forming the heavily doped p-type regions 118a-118e, the patterned mask layer M4 is removed, for example, using a plasma ashing process. In some embodiments, the plasma ashing process is performed to increase the temperature of the photoresist mask M4 until the photoresist mask M4 undergoes thermal decomposition and can be removed. However, any other suitable process, such as wet stripping, may be used.

[0108] Next, another patterned mask layer M5 is formed over the p-type epitaxial layer 105 to define the locations of the n-type source / drain regions 114s / 114d to be formed in a subsequent implantation process. The patterned mask layer M5 may comprise an organic material, such as a photoresist material, and may be formed using a spin-coating process. The photoresist material is then patterned using a suitable lithography technique to form one or more openings O5 extending through the patterned mask layer M5, thereby exposing target regions within the p-type epitaxial layer 105. For example, the photoresist material is irradiated (exposed) and developed to remove portions of the photoresist material. More specifically, a mask (not shown) may be placed over the photoresist material, which may then be exposed to a radiation beam, such as ultraviolet (UV) light or an excimer laser, such as a krypton fluoride (KrF) excimer laser or an argon fluoride (ArF) excimer laser. Exposure of the photoresist material can be performed, for example, using an immersion lithography tool or an extreme ultraviolet light (EUV) tool to increase resolution and reduce the minimum achievable pitch. A bake or cure operation can be performed to harden the exposed photoresist material, and a developer can be used to remove the exposed or unexposed portions of the photoresist material, depending on whether a positive or negative photoresist is used.

[0109] Next, with the patterned mask layer M5 in place, an n-type ion implantation process IMP5 is performed to dope n-type impurities (e.g., phosphorus, arsenic, antimony, etc.) into the N-well regions 108b, 108c and the p-type body region 112, thereby forming n-type drain regions 114d in the N-well regions 108b, 108c and n-type source regions 114s in the p-type body region 112. The n-type ion implantation IMP5 is performed using the patterned mask layer M5 as an implantation mask so that the top view pattern or geometry of each source / drain region inherits the top view pattern or geometry of the corresponding opening O5 of the patterned mask layer M5. In this way, the top view pattern of the opening O5 can be designed to define the desired top view pattern of the n-type source / drain regions 114s / 114d. In some embodiments, the n-type ion implantation process IMP5 is performed at a density of approximately 1E14 atoms / cm 2 to about 1E15 atoms / cm 2 The n-type impurities are implanted at a dose of about 10 KeV to about 50 KeV. The n-type source / drain regions 114s / 114d have an n-type impurity concentration higher than that of the N-well regions 108a-108d, for example, by at least one order of magnitude.

[0110] exist Figure 12 In the embodiment of the present invention, a silicide region 126 is formed on the exposed top surfaces of the heavily doped p-type regions 118a-118e, the n-type source / drain regions 114s / 114d, the N-well regions 108a, 108d, and the gate electrode 116. In some embodiments, the silicide region 126 can be formed by, for example, first depositing a metal (not shown) capable of reacting with the single crystal silicon of the underlying p-type epitaxial layer 105 and the polycrystalline silicon of the underlying gate electrode 116, such as cobalt, titanium, nickel, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof, on the exposed portions of the p-type epitaxial layer 105 and the gate electrode 116, and then performing a thermal annealing process to form the silicide region 126. Then, the unreacted portions of the deposited metal are removed, for example, by an etching process. Although the silicide region 126 is referred to as a silicide region, if the p-type epitaxial layer 105 and / or the gate electrode 116 include germanium or silicon germanium, the silicide region 126 may also be a germanide region or a silicon germanide region (eg, a region including silicide and germanide).

[0111] exist Figure 13 In the embodiment of the present invention, an interlayer dielectric (ILD) layer 131 is deposited across the HV transistor. The ILD layer 131 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, before depositing the ILD layer 131, a contact etch stop layer (CESL) (not shown) is deposited over the gate electrode 117 and the p-type epitaxial layer 105. The CESL may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which has a different etch rate than the material of the overlying ILD layer 131.

[0112] Next, metal contacts 128 are formed in the ILD layer 131 to contact the silicide regions 126. These contacts 128 may each include one or more metal layers, such as a barrier layer, a diffusion layer, and a filler material. For example, in some embodiments, each contact 128 includes a barrier layer and a conductive material and is electrically coupled to an underlying conductive feature (e.g., a silicide region). The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. The metal contacts 128 may be formed, for example, by forming contact openings in the ILD layer 131 using appropriate lithography and etching processes, depositing one or more layers of metal material in the contact openings, and then performing a planarization process (such as CMP) to remove excess metal material from the surface of the ILD layer 131.

[0113] exist Figure 14 In the embodiment of the present invention, another interlayer dielectric (ILD) layer 132 is deposited over the ILD layer 131. The ILD layer 132 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) (not shown) is deposited over the ILD layer 131 before depositing the ILD layer 132. The CESL may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, that has a different etch rate than the material of the overlying ILD layer 131.

[0114] Next, a plurality of metal vias 134 are formed in the ILD layer 132 and above each contact 128, and a plurality of metal lines 136 are formed in the ILD layer 132 and above the metal vias 134. The n-type drain region 114d can be electrically connected to the N-well region 108a via the metal vias 134 and the metal lines 136 electrically connected to the metal vias 134. In some embodiments, the metal lines 136 are connected to an input voltage terminal. Each of the metal vias 134 and the metal lines may include a barrier layer and a conductive material. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like.

[0115] The metal vias 134 and the metal lines 136 may be formed using, for example, a dual damascene process, such as forming trenches and contact openings in the ILD layer 132 in a trench-first or via-first manner using appropriate lithography and etching processes, depositing one or more layers of metal material in the trenches and contact openings, and then performing a planarization process (such as CMP) to remove excess metal material from the surface of the ILD layer 132.

[0116] Figure 15A A cross-sectional view of an IC structure according to some embodiments of the present disclosure is shown. Figure 15A The structure shown is Figure 1 The structure shown is similar except that Figure 15A The structure further includes a plurality of p-type doping regions 202 formed in the N-well region 108a and the N-well region 108d. The p-type doping regions 202 are arranged in a matrix arranged in columns and rows, as shown in FIG. Figure 15B , as shown in the top view. This arrangement can increase the reverse breakdown voltage of the Schottky diodes formed in the N-well regions 108a and 108d, thereby reducing unwanted leakage current. In some embodiments, the depth of the p-type doped region 202 is greater than the depth of the STI region 103, so that the lowest point of the p-type doped region 202 is lower than the lowest point of the STI region 103, thereby helping to reduce unwanted leakage current. In some embodiments, the p-type doped region 202 is formed by performing p-type ion implantation to dope p-type impurities (e.g., boron, boron fluoride, indium, etc.) into the N-well regions 108a and 108d.

[0117] Figure 16 A cross-sectional view of an IC structure according to some embodiments of the present disclosure is shown. Figure 16 The structure shown is Figure 1 The structure is similar to Figure 16 The structure further includes heavily doped p-type regions 302 and 304 formed in the N-well regions 108a and 108d, respectively. In this way, the heavily doped p-type region 302 can form a PN diode with the underlying N-well region 108a, and the heavily doped p-type region 304 can form a PN diode with the underlying N-well region 108d, to prevent the parasitic PNP transistor from turning on. Specifically, Figure 17 for Figure 16 The equivalent circuit diagram of the IC structure is shown. The circuit includes a HV transistor T1, a source terminal (ie, source region 114s) of the HV transistor T1 is electrically connected to the inductive load 130, and a drain terminal of the HV transistor T1 is electrically connected to the input voltage terminal VIN.

[0118] When HV transistor T1 is turned off, the magnetic energy stored in inductive load 130 seeks a dissipation path, causing reverse current to flow from inductive load 130 back to input voltage terminal VIN. This reverse current can take two paths, labeled P1 and P2. Path P1 passes through a body diode D1 formed by the PN junction of p-type body region 112 and N-well region 108b. Path P1 then passes through n-type drain region 114d and an overlying contact to input voltage terminal VIN. Path P2 passes through another body diode D2 formed by the PN junction of P-well region 106c and NBL 104. Path P2 then passes through N-well region 108a and an overlying contact to input voltage terminal VIN. When current flows along path P2, it may inadvertently activate parasitic PNP transistor T3 formed by deep P-well region 110b, NBL 104, and p-type substrate 102. The activation of parasitic PNP transistor T3 may result in undesirable leakage current. However, this risk is mitigated by the presence of PN diode D4 formed by N-well region 108a and overlying p-type region 302. When PN diode D4 is connected in series with NBL 104 on path P2, the impedance of path P2 is significantly increased compared to path P1. This increased impedance effectively blocks current from flowing through path P2, thereby preventing activation of parasitic PNP transistor T3. Consequently, potential problems associated with leakage current are reduced.

[0119] Furthermore, when the HV transistor T1 is turned on, the presence of the PN diode D4 does not adversely affect the performance of the circuit because the forward voltage drop of the PN diode D3 connected to the drain terminal of the HV transistor T1 is relatively low.

[0120] Based on the above discussion, it can be seen that the present disclosure provides advantages. However, it should be understood that other embodiments may provide additional advantages, that not all advantages are necessarily disclosed herein, and that no particular advantage is required of all embodiments. One advantage is that the parasitic PNP transistor is prevented from turning on because the conditions leading to activation are mitigated by using a Schottky diode or PN diode connected in series with the NBL. Another advantage is that the risks associated with leakage current and thermal damage caused by the activation of the parasitic PNP transistor are significantly reduced, thereby maintaining the integrity and functionality of the transistor in high-voltage applications.

[0121] In accordance with some embodiments, a device includes an n-type buried layer (e.g., layer 104) in a substrate, a first N-well region (e.g., region 108b) above the n-type buried layer, a p-type body region (e.g., region 112) adjacent to the first N-well region, a first source / drain region (e.g., region 114d) in the first N-well region, a second source / drain region (e.g., region 114s) in the p-type body region, a gate structure (e.g., structure GS1) extending across a boundary between the first N-well region and the p-type body region, a second N-well region (e.g., region 108a) above the n-type buried layer, and a first silicide region (e.g., region 126) forming a Schottky contact with the second N-well region. In some embodiments, the device further includes a second silicide region forming an ohmic contact with the first source / drain region, the lowest position of the second N-well region is lower than the lowest position of the first N-well region, the width of the first silicide region is the same as the width of the top surface of the second N-well region, and the second N-well region has a ring pattern when viewed from a top view, and the ring pattern surrounds the gate structure, the first source / drain region, and the second source / drain region. In some embodiments, the sidewalls of the second N-well region are aligned with the sidewalls of the n-type buried layer, and the second N-well region contacts the n-type buried layer. In some embodiments, the second N-well region and the first source / drain region are electrically connected to the same metal line. In some embodiments, the device further includes a plurality of p-type doped regions located in the second N-well region, and the p-type doped regions are arranged in columns and rows when viewed from a top view.

[0122] According to some embodiments, a device includes an n-type buried layer (e.g., layer 104) in a substrate, a first N-well region (e.g., region 108b) above the n-type buried layer, a p-type body region (e.g., region 112) adjacent to the first N-well region, a first source / drain region (e.g., region 114d) in the first N-well region, a second source / drain region (e.g., region 114s) in the p-type body region, a gate structure (e.g., structure GS1) extending across the boundary between the first N-well region and the p-type body region, a second N-well region (e.g., region 108a) above the n-type buried layer, a p-type region (e.g., 302) above the second N-well region, and a first silicide region (e.g., 126) interfacing with the p-type region. In some embodiments, the device further includes a first STI region located above a first sidewall of the second N-well region and a second STI region located above a second sidewall of the second N-well region, with the p-type region extending continuously from the first STI region to the second STI region. In some embodiments, the second N-well region contacts a top surface of the n-type buried layer.

[0123] According to some embodiments, a method includes the following steps: forming a buried layer (e.g., layer 104) in a substrate. The buried layer has a first conductivity type. forming an epitaxial layer (e.g., layer 105) above the buried layer. forming a first well region (e.g., region 108b) and a second well region (e.g., region 108a) in the epitaxial layer. the first and second well regions have the first conductivity type. forming a body region (e.g., region 112) above the buried layer. the body region forms a PN junction with the first well region. forming a first source / drain region (e.g., region 114d) in the first well region, and forming a second source / drain region (e.g., region 114s) in the body region. forming a gate structure (e.g., structure GS1) laterally between the first source / drain region and the second source / drain region. a first silicide region contacts the second well region. the method further includes the step of forming a second silicide region in contact with the first source / drain region. the method further includes the step of forming a metal line electrically connecting the first silicide region and the second silicide region. In some embodiments, the gate structure extends across a boundary between the body region and the first well region. In some embodiments, the method further includes the following steps: forming a deep well region below the first well region, the deep well region having a second conductivity type different from the first conductivity type, and the deep well region contacting a top surface of the buried layer. In some embodiments, the substrate has a second conductivity type. In some embodiments, a semiconductor device includes a buried layer located in a substrate, the buried layer having a first conductivity type; a first well region located above the buried layer, the first well region having the first conductivity type; an integral region having a second conductivity type and forming a PN junction with the first well region; a first source / drain region located in the first well region; a second source / drain region located in the body region; a gate structure extending across a boundary between the first well region and the body region; a second well region located above the buried layer, the second well region having the first conductivity type; and a first silicide region forming a Schottky contact with the second well region. In some embodiments, the device further includes a plurality of doped regions located in the second well region, the doped regions being arranged in columns and rows when viewed from a top view.

[0124] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made to these equivalent constructions without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: Include: an n-type buried layer located in a substrate; a first N-well region located above the n-type buried layer; a p-type body region adjacent to the first N-well region; a first source / drain region located in the first N-well region; a second source / drain region located in the p-type body region; a gate structure extending across a boundary between the first N-well region and the p-type body region; a second N-well region located above the n-type buried layer; and A first silicide region forms a Schottky contact with the second N-well region.

2. The semiconductor device according to claim 1, wherein Further including: A second silicide region forms an ohmic contact with the first source / drain region.

3. The semiconductor device according to claim 1, wherein A bottommost position of the second N-well region is lower than a bottommost position of the first N-well region.

4. The semiconductor device according to claim 1, wherein From a top view, the second N-well region has a ring pattern.

5. The semiconductor device according to claim 1, wherein Further including: A plurality of p-type doping regions are located in the second N-well region. From a top view, the plurality of p-type doping regions are arranged in columns and rows.

6. A semiconductor device, characterized in that: Include: an n-type buried layer located in a substrate; a first N-well region located above the n-type buried layer; a p-type body region adjacent to the first N-well region; a first source / drain region located in the first N-well region; a second source / drain region located in the p-type body region; a gate structure extending across a boundary between the first N-well region and the p-type body region; a second N-well region located above the n-type buried layer; a p-type region located above the second N-well region; and A first silicide region interfaces with the p-type region.

7. The semiconductor device according to claim 6, wherein Further including: a first shallow trench isolation region located above a first sidewall of the second N-well region; and A second shallow trench isolation region is located above a second sidewall of the second N-well region.

8. The semiconductor device according to claim 6, wherein The second N-well region contacts a top surface of the n-type buried layer.

9. A semiconductor device, characterized in that: Include: a buried layer located in a substrate, the buried layer having a first conductivity type; a first well region located above the buried layer, the first well region having the first conductivity type; An integrated region having a second conductivity type and forming a PN junction with the first well region; a first source / drain region located in the first well region; a second source / drain region located in the body region; a gate structure extending across a boundary between the first well region and the body region; a second well region located above the buried layer, the second well region having the first conductivity type; and A first silicide region forms a Schottky contact with the second well region.

10. The semiconductor device according to claim 9, wherein Also includes: A plurality of doped regions are located in the second well region. From a top view, the plurality of doped regions are arranged in columns and rows.

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