CPCIE board card, case and electronic equipment
Through the innovative design of the backplane and interface board, the functional board interface is directly brought out, solving the problem of complex CPCIE board signal transfer, realizing cable-free connection, and improving the maintainability and versatility of the chassis.
Patent Information
- Application Number
- CN202422783129.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-14
- Publication Date
- 2025-09-12
- Estimated Expiration
- 2034-11-14
AI Technical Summary
Existing CPCIE boards have many signal transfer points, which leads to complex cable design and low versatility, making it difficult to achieve efficient cable-free connection.
The backplane and interface board design is adopted. The function board directly leads to the function interface through the interface board, eliminating the extra connectors and cables on the backplane and realizing cable-free connection.
It improves the maintainability of CPCIE chassis, reduces the difficulty of cable design, and enhances the versatility and configurability of the equipment.
Smart Images
Figure CN223333329U_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of computer technology, and in particular to a CPCIE board, a chassis, and an electronic device. Background Art
[0002] CPCIE (Compact Peripheral Component Interconnect Express) is a high-performance, low-cost computer expansion bus standard with the advantages of hot pluggability, high openness, high scalability, and high reliability. It is currently widely used in communication network computers and other fields, providing users with a flexible and reliable system expansion solution.
[0003] In the prior art, CPCI boards are used as front-exit plug-ins, with each backplane corresponding to a daughterboard plug-in. The functional interfaces of these boards are converted to connectors of other interface types via the CPCI backplane, and then cables are routed to the required panel interfaces. This approach results in an increase in signal transfer points, reduces versatility, and increases the complexity of cable design within the chassis. Utility Model Content
[0004] In order to solve the above technical problems or at least partially solve the above technical problems, the present disclosure provides a distributed computing circuit and a distributed computing server, which do not require additional connectors and cables to be designed on the backplane, and can achieve cable-free connection within the CPCIE architecture chassis, thereby improving the maintainability of the CPCIE architecture chassis, reducing the difficulty of cable design, and improving the versatility and configurability of the equipment.
[0005] In a first aspect, an embodiment of the present disclosure provides a CPCIE board, including:
[0006] Backplane, function board and interface board;
[0007] The function board is plug-connected to the first surface of the backplane, and the interface board is plug-connected to the second surface of the backplane; wherein the first surface of the backplane and the second surface of the backplane are arranged opposite to each other;
[0008] The interface board is used to bring out the functional interface of the functional board.
[0009] Optionally, the backplane includes a first connector and a second connector, the first connector is distributed on the first surface of the backplane, and the second connector is distributed on the second surface of the backplane;
[0010] The backplane is electrically connected to the function board through the first connector, and the backplane is electrically connected to the interface board through the second connector.
[0011] Optionally, the first connector includes a first power connector, and the second connector includes a second power connector;
[0012] The first power connector and the second power connector are staggered.
[0013] Optionally, the first power connector includes a plurality of first connecting pins, and the second power connector includes a plurality of second connecting pins;
[0014] The first connecting pins and the second connecting pins are staggered.
[0015] Optionally, along a direction parallel to the backplane, a distance between adjacent first connecting pins is equal to twice a distance between adjacent first connecting pins and second connecting pins within an error range.
[0016] Optionally, the first connector includes a plurality of first CPCIE connectors, and the second connector includes a plurality of second CPCIE connectors;
[0017] The corresponding plugging direction between the first CPCIE connector and the backplane is opposite to the plugging direction between the second CPCIE connector and the backplane.
[0018] Optionally, each of the first CPCIE connectors includes a plurality of third connection pins, and each of the second CPCIE connectors includes a plurality of fourth connection pins;
[0019] The pin numbers of the corresponding third connecting pins are arranged in opposite directions to the pin numbers of the corresponding fourth connecting pins.
[0020] Optionally, along a direction perpendicular to the back plate, a length of the third connecting pin and the fourth connecting pin ranges from 1.5 mm to 2.8 mm.
[0021] In a second aspect, the present disclosure further provides a chassis comprising the CPCIE board as described in the first aspect.
[0022] In a third aspect, the present disclosure further provides an electronic device, comprising the chassis as described in the second aspect.
[0023] The technical solution provided by the present disclosure has the following advantages compared with the existing technology:
[0024] The present disclosure provides a CPCI board, a chassis, and an electronic device. The CPCI board provided by the present disclosure includes: a backplane, a function board, and an interface board; the function board is pluggably connected to a first side of the backplane, and the interface board is pluggably connected to a second side of the backplane; the first side of the backplane and the second side of the backplane are arranged opposite each other; and the interface board is used to connect the function interface of the function board. Thus, by connecting the function interface of the function board using the interface board, there is no need to design additional connectors and cables on the backplane, thus achieving cable-free connection within the CPCI-based chassis, improving the maintainability of the CPCI-based chassis, reducing the difficulty of cable design, and improving the versatility and configurability of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.
[0026] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0027] Figure 1 A schematic diagram of a top view of a CPCIE board provided in an embodiment of the present disclosure;
[0028] Figure 2 A schematic diagram of the side structure of a CPCIE board provided in an embodiment of the present disclosure;
[0029] Figure 3 A schematic side view of a backplane according to an embodiment of the present disclosure;
[0030] Figure 4 A schematic diagram of the arrangement of slots formed by a first connector provided in an embodiment of the present disclosure;
[0031] Figure 5 A schematic diagram of the arrangement of slots formed by a second connector provided in an embodiment of the present disclosure;
[0032] Figure 6 A schematic diagram of the arrangement of first connecting pins provided in an embodiment of the present disclosure;
[0033] Figure 7 A schematic diagram of the arrangement of second connecting pins provided in an embodiment of the present disclosure;
[0034] Figure 8 A schematic diagram of the arrangement of a third connecting pin provided in an embodiment of the present disclosure;
[0035] Figure 9 A schematic diagram of the arrangement of a fourth connecting pin provided in an embodiment of the present disclosure.
[0036] Among them, 1. backplane; 2. function board; 3. interface board; 11. first connector; 12. second connector; 111. first power connector; 112. second power connector; 1111. first connection pin; 1121. second connection pin; 113. first CPCIE connector; 114. second CPCIE connector; 1131. third connection pin; 1141. fourth connection pin. DETAILED DESCRIPTION
[0037] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features therein can be combined with each other in the absence of conflict.
[0038] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.
[0039] In the prior art, CPCI boards are used as front-mounted plug-ins, with each backplane corresponding to a daughterboard. The functional interfaces of these boards are converted to connectors of other interface types via the CPCI backplane, and then the cables are routed to the required panel interfaces. This approach results in an increase in signal transfer points, reduces versatility, and increases the complexity of cable design within the chassis.
[0040] Figure 1 A schematic diagram of a top view of a CPCIE board provided in an embodiment of the present disclosure is shown. Figure 2 A side view structural diagram of a CPCIE board provided in an embodiment of the present disclosure. Figure 1 and Figure 2 , backplane 1, function board 2 and interface board 3; function board 2 is plug-connected to the first side of backplane 1, and interface board 3 is plug-connected to the second side of backplane 1; wherein, the first side of backplane 1 and the second side of backplane 1 are arranged opposite to each other; interface board 3 is used to lead out the functional interface of function board 2.
[0041] Specifically, combined Figure 1 and Figure 2The first surface of the backplane 1 can be, for example, the front surface of the backplane 1, the second surface of the backplane 1 can be, for example, the back surface of the backplane 1, the functional board 2 can be used as a front plug-in, and the functional board 2 can be, for example, a board with specific functions or data processing capabilities, such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a board with network switching function, or a board with video processing function, etc. can all be used as the functional board 2.
[0042] In existing CPCIE boards, the functional interfaces of functional boards need to be brought out through connectors and cannot be used directly. In this case, some additional connectors for external signal output must be designed on the backplane, and the signals must be brought out to the rear panel of the chassis using plug-in cables, which increases the signal transfer points and complicates the cable design.
[0043] In order to solve the above problems, the embodiment of the present disclosure sets the second side of the backplane 1 to be plugged into the interface board 3, and uses the backplane 1 as a carrier board. The interface board 3 leads out the functional interface of the functional board 2 to form the required interface form, such as USB, network port, HDMI or DB9 serial port, etc., so that there is no need to design additional connectors and cables on the backplane 1, and cable-free connection can be achieved within the CPCIE architecture chassis.
[0044] The CPCI board provided by the embodiment of the present disclosure includes: a backplane 1, a function board 2 and an interface board 3; the function board 2 is plug-connected to the first side of the backplane 1, and the interface board 3 is plug-connected to the second side of the backplane 1; wherein the first side of the backplane 1 and the second side of the backplane 1 are arranged relative to each other; the interface board 3 is used to lead out the functional interface of the function board 2, and there is no need to design additional connectors and cables on the backplane 1, so that cable-free connection can be achieved within the CPCI architecture chassis, thereby improving the maintainability of the CPCI architecture chassis, reducing the difficulty of cable design, and improving the versatility and configurability of the equipment.
[0045] Figure 3 A schematic side view of a backplane according to an embodiment of the present disclosure is shown. Figure 4 A schematic diagram of the arrangement of slots formed by a first connector provided in an embodiment of the present disclosure is provided. Figure 5 A schematic diagram of the arrangement of slots of a second connector provided in an embodiment of the present disclosure. Figures 3 to 5 The backplane 1 includes a first connector 11 and a second connector 12. The first connector 11 is distributed on the first surface of the backplane 1, and the second connector 12 is distributed on the second surface of the backplane 1. The backplane 1 is electrically connected to the functional board 2 through the first connector 11, and the backplane 1 is electrically connected to the interface board 3 through the second connector 12.
[0046] Specifically, Figure 3 FIG. 1 exemplarily shows that a first connector 11 and a second connector 12 are provided on the backplane 1. Figure 4 The figure shows by way of example the slots formed by the first connector 11 on the first surface of the backplane 1. The slots formed by the first connector 11 are the plug-in positions of the function board 2 and the backplane 1. Figure 4 XA0-XP1 to XA0-XJ9 represent the serial numbers of the slots where the first connector 11 is located, which are well known to those skilled in the art and will not be described in detail in the embodiment of the present disclosure. Figure 5 The figure shows by way of example the slots formed by the second connector 12 located on the second surface of the backplane 1. The slots formed by the second connector 12 are the plug-in positions of the interface board 3 and the backplane 1. Figure 5 The numbers R-XA0-XP1 to R-XA0-XJ9 represent the slot numbers for the second connector 12. These details are well known to those skilled in the art and are not detailed here in the present disclosure. The text has been rotated 180° for clarity. Backplane 1 is electrically connected to function board 2 via first connector 11, and to interface board 3 via second connector 12. This ensures that both function board 2 and interface board 3 are electrically connected to backplane 1.
[0047] Figure 4 XA0-XJ4 and XA0-XJ9 are used to represent CPCI connectors located on the first side of the backplane, which are well known to those skilled in the art and will not be described in detail here.
[0048] Alternatively, as Figure 3 As shown, the first connector 11 includes a first power connector 111 , and the second connector 12 includes a second power connector 112 ; the first power connector 111 and the second power connector 112 are staggered.
[0049] Specifically, if Figure 3 As shown, the first connector 11 may, for example, include a first power connector 111, which is located on the first side of the backplane 1; the second connector 12 may, for example, include a second power connector 112, which is located on the second side of the backplane 1; the first power connector 111 and the second power connector 112 are staggered to achieve the connection between the backplane 1 and the functional board 2, as well as the connection between the backplane 1 and the interface board 3.
[0050] Figure 6 A schematic diagram of the arrangement of first connecting pins provided in an embodiment of the present disclosure is provided. Figure 7 A schematic diagram of the arrangement of the second connecting pins provided in an embodiment of the present disclosure. Figure 6 and Figure 7The first power connector 111 includes a plurality of first connection pins 1111 , and the second power connector 112 includes a plurality of second connection pins 1121 ; the corresponding first connection pins 1111 and the second connection pins 1121 are staggered.
[0051] Specifically, for clarity, Figure 6 and Figure 7 The black circle represents the position of the pressing hole of the first connecting pin 1111, and the white circle represents the position of the pressing hole of the second connecting pin 1121. Figure 6 and Figure 7 It can be seen that the plurality of first connecting pins 1111 in the first connector 11 and the plurality of second connecting pins 1121 in the second connector 12 are evenly distributed and staggered.
[0052] Optionally, combined Figure 6 and Figure 7 , along a direction parallel to the back plate 1 , the distance between adjacent first connecting pins 1111 is equal to twice the distance between adjacent first connecting pins 1111 and second connecting pins 1121 within an error range.
[0053] Specifically, combined Figure 6 and Figure 7 The first connecting pins 1111 and the second connecting pins 1121 can be staggered and arranged. Along the direction parallel to the backplane 1, the distance h1 between adjacent first connecting pins 1111 is, for example, 3 mm, and the distance h2 between adjacent first connecting pins 1111 and second connecting pins 1121 is, for example, 1.5 mm. Taking into account the process error, the distance between adjacent first connecting pins 1111 is twice the distance between adjacent first connecting pins 1111 and second connecting pins 1121.
[0054] Optionally, combined Figure 1 and Figure 3 The first connector 11 includes multiple first CPCIE connectors 113, and the second connector 12 includes multiple second CPCIE connectors 114; the corresponding plug-in direction of the first CPCIE connector 113 and the backplane 1 is opposite to the plug-in direction of the second CPCIE connector 114 and the backplane 1.
[0055] Specifically, combined Figure 1 and Figure 3 The first connector 11 includes a plurality of first CPCIE connectors 113, and the second connector 12 includes a plurality of second CPCIE connectors 114. Figure 1 and Figure 3Six first CPCIE connectors 113 and six second CPCIE connectors 114 are exemplarily shown. The present disclosure does not limit the specific number of first CPCIE connectors 113 and second CPCIE connectors 114. The first CPCIE connectors 113 and second CPCIE connectors 114 can be of the same model, with the first CPCIE connectors 113 and second CPCIE connectors 114 positioned opposite to each other, to facilitate connection between the function board 2 and the backplane 1, and between the interface board 3 and the backplane 1.
[0056] Figure 8 A schematic diagram of the arrangement of a third connection pin provided in an embodiment of the present disclosure is provided. Figure 9 A schematic diagram of the arrangement of a fourth connection pin provided in an embodiment of the present disclosure. Figure 8 and Figure 9 Each first CPCIE connector 113 includes a plurality of third connection pins 1131, and each second CPCIE connector 114 includes a plurality of fourth connection pins 1141; the pin numbers of the corresponding third connection pins 1131 and the pin numbers of the fourth connection pins 1141 are arranged in opposite directions.
[0057] Specifically, Figure 8 and Figure 9 Taking the direction in as an example, from left to right, the pin number of the third connection pin 1131 ranges from A(1-10) to F(1-10), and the pin number of the third connection pin 1131 ranges from A(10-1) to F(10-1). The corresponding plug-in direction of the first CPCIE connector 113 and the backplane 1 is opposite to the plug-in direction of the second CPCIE connector 114 and the backplane 1, so that the pin number of the corresponding third connection pin 1131 and the pin number of the fourth connection pin 1141 are arranged in opposite directions, thereby realizing the front and rear plug-in of the backplane 1.
[0058] Optionally, along a direction perpendicular to the back plate 1 , the length of the third connecting pin 1131 and the fourth connecting pin 1141 ranges from 1.5 mm to 2.8 mm.
[0059] Specifically, since the first side of the backplane 1 is plug-connected to the functional board 2, and the second side of the backplane 1 is plug-connected to the interface board 3, in order to reduce the thickness of the backplane 1, the third connecting pin 1131 and the fourth connecting pin 1141 can both adopt a short pin model. Along the direction perpendicular to the backplane 1, the length range of the third connecting pin 1131 and the fourth connecting pin 1141 is 1.5mm-2.8mm. Taking the length of the third connecting pin 1131 and the fourth connecting pin 1141 as an example, both of which are 1.7mm±0.2mm, according to the third connecting pin The longest length of pin 1131 and the fourth connecting pin 1141 is 1.9 mm, and the thickness of the backplane 1 is 2*1.9 mm=3.8 mm. At the same time, taking into account the board processing error of the backplane 1, the thickness of the backplane 1 is designed to be no less than 4.3 mm±10%, which can reduce the thickness of the backplane 1 and effectively avoid the situation where the third connecting pin 1131 and the fourth connecting pin 1141 are pushed when the first CPCIE connector 113 is pressed to the first surface of the backplane 1 and the second CPCIE connector 114 is pressed to the second surface of the backplane 1.
[0060] The CPCIE board provided by the embodiment of the present disclosure includes: a backplane, a function board and an interface board; the function board is plug-connected to the first side of the backplane, and the interface board is plug-connected to the second side of the backplane; wherein the first side of the backplane and the second side of the backplane are arranged relative to each other; the interface board is used to lead out the functional interface of the function board, and there is no need to design additional connectors and cables on the backplane, so that cable-free connection can be achieved within the CPCIE architecture chassis, thereby improving the maintainability of the CPCIE architecture chassis, reducing the difficulty of cable design, and improving the versatility and configurability of the equipment.
[0061] The present disclosure also provides a chassis including the CPCIE board described in the above embodiment. Therefore, the chassis provided by the present disclosure has the advantages described in the above embodiment, which are not further described here. The chassis can be, for example, a reinforced cooling chassis or other type. The present disclosure does not limit the specific structure, shape, or type of the chassis, as long as it meets the user's usage requirements.
[0062] The embodiments of the present disclosure also provide an electronic device, which includes the signs described in the above embodiments. Therefore, the electronic device provided by the embodiments of the present disclosure has the beneficial effects described in the above embodiments.
[0063] In addition, the electronic device described in the embodiments of the present disclosure may be a computer, a mobile phone, etc., and the embodiments of the present disclosure do not make specific limitations on this. The embodiments of the present disclosure do not make specific limitations on this.
[0064] The disclosed embodiments provide a CPCI board, a chassis, and an electronic device. The CPCI board provided by the disclosed embodiments includes: a backplane, a function board, and an interface board; the function board is pluggably connected to the first side of the backplane, and the interface board is pluggably connected to the second side of the backplane; the first side of the backplane and the second side of the backplane are arranged opposite each other; and the interface board is used to connect the function interface of the function board. Thus, by connecting the function interface of the function board using the interface board, there is no need to design additional connectors and cables on the backplane, enabling cable-free connections within the CPCI-based chassis. This improves the maintainability of the CPCI-based chassis, reduces the difficulty of cable design, and enhances the versatility and configurability of the device.
[0065] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device that includes the element.
[0066] The above are merely specific embodiments of the present disclosure, intended to enable those skilled in the art to understand and implement the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is not limited to these embodiments, but is to be construed in the broadest manner consistent with the principles and novel features disclosed herein.
Claims
1. A CPCIE board, characterized in that: include: Backplane, function board and interface board; The function board is plug-connected to the first surface of the backplane, and the interface board is plug-connected to the second surface of the backplane; wherein the first surface of the backplane and the second surface of the backplane are arranged opposite to each other; The interface board is used to bring out the functional interface of the functional board.
2. The CPCIE board according to claim 1, wherein: The backplane includes a first connector and a second connector, wherein the first connector is distributed on a first surface of the backplane, and the second connector is distributed on a second surface of the backplane; The backplane is electrically connected to the function board through the first connector, and the backplane is electrically connected to the interface board through the second connector.
3. The CPCIE board according to claim 2, wherein: The first connector includes a first power connector, and the second connector includes a second power connector; The first power connector and the second power connector are staggered.
4. The CPCIE board according to claim 3, wherein: The first power connector includes a plurality of first connecting pins, and the second power connector includes a plurality of second connecting pins; The corresponding first connecting pins and the second connecting pins are staggered.
5. The CPCIE board according to claim 4, wherein: Along a direction parallel to the back plate, a distance between adjacent first connecting pins is equal to twice a distance between adjacent first connecting pins and second connecting pins within a tolerance range.
6. The CPCIE board according to claim 2, wherein: The first connector includes a plurality of first CPCIE connectors, and the second connector includes a plurality of second CPCIE connectors; The corresponding plugging direction between the first CPCIE connector and the backplane is opposite to the plugging direction between the second CPCIE connector and the backplane.
7. The CPCIE board according to claim 6, wherein: Each of the first CPCIE connectors includes a plurality of third connection pins, and each of the second CPCIE connectors includes a plurality of fourth connection pins; The pin numbers of the corresponding third connecting pins are arranged in opposite directions to the pin numbers of the corresponding fourth connecting pins.
8. The CPCIE board according to claim 7, wherein: Along a direction perpendicular to the back plate, the length of the third connecting pin and the fourth connecting pin ranges from 1.5 mm to 2.8 mm.
9. A chassis, characterized in that: It comprises the CPCIE board card as described in any one of claims 1-8.
10. An electronic device, characterized in that: Comprising the chassis as claimed in claim 9.