Biasing circuit for amplifier and amplifier

Abstract

The utility model provides a biasing circuit and an amplifier. The bias circuit comprises a programmable current source which generates bias current with adjustable magnitude based on a first control signal; the amplification transistor is used for receiving bias voltage; a transistor unit for an input transistor of the first current mirror; the transistor unit comprises a plurality of first transistors, and when the control ends of the first transistors receive bias current, and the first ends and the control ends of the first transistors are short-circuited and connected to an output node, the first transistors provide voltage for the output node; and the first switch units change the quantity of the bias current received by the control end of the first transistor and / or change the quantity of the output nodes connected to the first end of the first transistor based on the second control signal. Therefore, the adjusting range is further widened while the adjusting precision is guaranteed.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, a bias circuit for an amplifier and the amplifier. Background Art

[0002] Currently, bias voltage adjustment and calibration primarily rely on digital-to-analog converters (DACs). However, there's a trade-off between the bias voltage's adjustment range and accuracy. If a change in the DAC's control word results in a significant bias voltage change, while a wider adjustment range can be achieved, adjustment accuracy will be compromised, increasing errors in the chip calibration process. Conversely, if a change in the DAC's control word results in a smaller bias voltage change, while adjustment accuracy can be improved to meet requirements such as amplifier calibration, the overall adjustment range will be limited.

[0003] Therefore, in practical applications, it is necessary to comprehensively consider factors such as adjustment range, adjustment accuracy, and chip area to select the most suitable bias voltage adjustment scheme. Utility Model Content

[0004] In view of this, embodiments of the present disclosure provide a bias circuit for an amplifier and an amplifier, which further expand the adjustment range while ensuring the adjustment accuracy.

[0005] The technical solution of the embodiment of the present disclosure is implemented as follows:

[0006] An embodiment of the present disclosure provides a bias circuit for an amplifier, wherein the bias circuit for the amplifier includes an amplifying transistor, and the bias circuit includes: a programmable current source, which generates a bias current of adjustable size based on a first control signal; the amplifying transistor, which is used to receive a bias voltage; a transistor unit, which is an input transistor of a first current mirror, which outputs a bias voltage, and the output transistor of the first current mirror includes the amplifying transistor; the transistor unit includes: a plurality of first transistors, wherein the first transistor includes a first end and a control end; when the control end of the first transistor receives the bias current, the first end and the control end of the first transistor are short-circuited and connected to the amplifying transistor, the first transistor provides a voltage to the amplifying transistor; a plurality of first switching units, wherein the first switching units change the amount of the bias current received by the control end of the first transistor based on a second control signal, and / or change the number of the amplifying transistors connected to the first end of the first transistor.

[0007] In some embodiments, the bias circuit further includes a second transistor, the second transistor including a first terminal and a control terminal, the control terminal of the second transistor receives the bias current, and the first terminal and the control terminal of the second transistor are short-circuited and connected to the amplifying transistor.

[0008] In some embodiments, the first terminal of the first transistor receives at least one bias current, and / or the control terminal of the first transistor is connected to at least one output node.

[0009] It is understood that the embodiments of the present disclosure can adjust the bias current received by the transistor unit based on the first control signal, thereby adjusting the bias voltage; and can also change the number of first transistors turned on in the transistor unit based on the second control signal, that is, changing the number of first transistors providing voltage to the output node, thereby adjusting the equivalent channel width of the transistor unit. The equivalent channel width is related to the bias voltage, so changing the number of first transistors turned on in the transistor unit can adjust the bias voltage. In this way, both the first control signal and the second control signal can adjust the bias voltage. In this case, if a bit encoding change of the first control signal can bring about a small bias voltage change, and a bit encoding change of the second control signal can bring about a large bias voltage change, that is, the second control signal can provide a larger bias voltage adjustment range and the first control signal can provide a smaller adjustment accuracy, then the embodiments of the present disclosure can use the second control signal to coarsely adjust the bias voltage, and then use the first control signal to fine-tune the bias voltage. Therefore, the embodiments of the present disclosure can not only improve the adjustment accuracy of the bias voltage, but also expand the adjustment range of the bias voltage.

[0010] In addition, the first control signal is used to adjust the size of the bias current, and the second control signal is used to adjust the amount of voltage provided by the first transistor. Assuming that the bit position of the first control signal is X and the bit position of the second control signal is Y, generally X bits require A transistors to implement, and Y bits require B transistors to implement. In this solution, each first control signal can correspond to a second control signal of Y bits, so this solution requires X+Y transistors to implement X×Y bits. In contrast, when the bit position of the first control signal is X×Y bits, X×Y transistors are required. Therefore, when the same X×Y bit adjustment is achieved, this solution uses fewer transistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 Schematic diagram of the bias circuit provided in the embodiment of the present disclosure Figure 1 ;

[0012] Figure 2 Schematic diagram of the structure of the transistor unit provided in the embodiment of the present disclosure Figure 1 ;

[0013] Figure 3 Schematic diagram of the structure of the transistor unit provided in the embodiment of the present disclosure Figure 2 ;

[0014] Figure 4 A schematic diagram of the structure of the first switch unit provided in the embodiment of the present disclosure Figure 1 ;

[0015] Figure 5 A schematic diagram of the structure of the first switch unit provided in the embodiment of the present disclosure Figure 2 ;

[0016] Figure 6 A schematic diagram of the structure of a programmable current source provided in an embodiment of the present disclosure;

[0017] Figure 7 A schematic diagram of the structure of an amplifier provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0019] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0020] If similar descriptions of "first / second" appear in the application documents, the following explanation is added. In the following description, the terms "first / second / third" are merely used to distinguish similar objects and do not represent a specific order for the objects. It is understandable that "first / second / third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0022] Figure 1 is a schematic diagram of the structure of an optional bias circuit 100 provided in an embodiment of the present disclosure, with reference to Figure 1 The bias circuit 100 is connected to the amplifier 200 and is used to provide a bias voltage to the amplifier 200.

[0023] In the embodiments of the present disclosure, reference Figure 1The bias circuit 100 includes a programmable current source 10, which is a current source capable of adjusting the magnitude of an output current according to an external control signal. The programmable current source 10 can generate an adjustable bias current based on a first control signal, where the bias current is the output current of the programmable current source 10. For example, the first control signal can be binary coded to facilitate adjustment of the bias current. The programmable current source 10 can identify changes in each bit code in the first control signal to increase or decrease the bias current, thereby achieving control over the bias current. In other words, the programmable current source 10 can adjust the output bias current in real time according to changes in the first control signal to provide an adjustable bias current.

[0024] Continue to refer Figure 1 Bias circuit 100 further includes a transistor unit 20. Transistor unit 20 can be connected to programmable current source 10 and receive a bias current provided by bias circuit 100. Transistor unit 20 can include at least one transistor, which is connected to amplifying transistor Ma of amplifier 200 to form a first current mirror. The transistors in transistor unit 20 can be used as input transistors of the first current mirror. Amplifying transistor Ma can be used as an output transistor of the first current mirror.

[0025] After the bias current flows into the transistor unit 20, the transistors in the transistor unit 20 generate a bias voltage. The transistor unit 20 and the amplifier transistor Ma form a first current mirror. The gates of the transistors in the transistor unit 20 are connected to the gate of the amplifier transistor Ma, so that the bias voltage biases the amplifier transistor Ma. By adjusting the magnitude of the bias current and / or the equivalent size of the transistors in the transistor unit 20, the magnitude of the bias voltage provided to the amplifier transistor Ma can be adjusted, thereby controlling the operating point of the amplifier transistor Ma and ensuring that the amplifier transistor Ma can efficiently amplify the signal.

[0026] In this embodiment, multiple first transistors and multiple first switch units can be provided in the transistor unit 20. By controlling the second control signal, the switching state of the first switch unit is changed, and the number of effective first transistors in the transistor unit 20 is changed, thereby adjusting the magnitude of the bias voltage. The effective first transistor is a transistor that can provide current to the amplifier transistor Ma. The structure and operating principle of the transistor unit 20 are described below in conjunction with specific embodiments.

[0027] Figure 2 is a schematic structural diagram of an optional transistor unit 20 provided in an embodiment of the present disclosure. It should be noted that: Figure 2The amplifier 200 shown in the example is a cascode structure, and the amplifier 200 can also be a common source structure or a common gate structure, which is not limited here. In addition, the amplifier 200 can be a power amplifier, a gain amplifier, an operational amplifier, a class AB amplifier, etc. Figure 2 Inductor L1 and capacitor C1 form the output matching circuit of amplifier 200, matching the output impedance of amplifier 200. Capacitor C2 isolates the input RF signal from the bias circuit. "RFIN" is the input of amplifier 200; "RFOUT" is the output of amplifier 200. "Vb2" provides a bias voltage to transistor Mb. Transistor Mb and amplifying transistor Ma form a cascode structure to increase the output impedance of amplifier 200, enabling better constant current characteristics.

[0028] It should also be noted that Figure 2 The transistors M0 to Mn shown are all NMOS (N-Metal-Oxide-Semiconductor) transistors for illustration. The first terminals of the transistors M0 to Mn are drains, the second terminals of the transistors M0 to Mn are sources, and the control terminals of the transistors M0 to Mn are gates. Transistors M0 to Mn may also be other types of transistors, such as bipolar junction transistors (BJTs), without limitation herein.

[0029] In the embodiments of the present disclosure, reference Figure 2 , the transistor unit 20 includes a plurality of first transistors ( Figure 2 The first terminals (e.g., drains) and control terminals (e.g., gates) of the first transistors M1 to Mn are short-circuited. Under control of the first switch units 41 a - 41 d, the first terminals (e.g., drains) of some of the first transistors M1 to Mn are connected to the output of the programmable current source 10 to receive a bias current. The first terminals (e.g., drains) of these transistors are connected to the output node A to provide a bias voltage to the output node A.

[0030] In the embodiments of the present disclosure, reference Figure 2 , the transistor unit 20 includes a second transistor M0. The second transistor M0 includes a drain (first end) and a gate (control end). The gate (control end) of the second transistor M0 is connected to the programmable current source 10 to receive the bias current. The drain (first end) and the gate (control end) of the second transistor M0 are short-circuited, and the drain (first end) and the gate (control end) of the second transistor M0 are both connected to the amplifying transistor Ma through the output node A. Thus, the second transistor M0 is in the on state, connected with the amplifying transistor Ma to form a first current mirror to provide a voltage to the output node A of the bias circuit. Figure 2In the illustrated embodiment, the transistor unit 20 includes one second transistor M0 . In other embodiments, the transistor unit 20 may include a plurality of second transistors M0 .

[0031] In the embodiments of the present disclosure, reference Figure 2 , the transistor unit 20 further includes a plurality of first switch units ( Figure 2 41a to 41d in FIG. 41b). A plurality of first switch units ( Figure 2 41a to 41d) can change the number of control terminals of the first transistors receiving the bias current and / or change the number of control terminals of the first transistors connected to the output node based on the second control signal, thereby controlling which first transistors M1 to Mn provide voltage to the output node A, that is, the second control signal can control which first transistors are effective.

[0032] For example, the second control signal may be binary coded to facilitate controlling the switching state of the first switch unit. Each bit of the second control signal may control one first switch unit or one switch in the first switch unit. Figure 2 The first switch unit 41a may include a first switch SW_H1 and a second switch SW_L1, which are used to control a corresponding first transistor M1. In some embodiments, the first switch SW_H1 and the second switch SW_L1 receive the same bit code of the second control signal, and then the first switch SW_H1 and the second switch SW_L1 can be opened or closed at the same time. The first switch SW_H1 is used to disconnect or close the connection between the gate (control terminal) of the first transistor M1 and the programmable current source 10, and the second switch SW_L1 is used to disconnect or close the connection between the drain (first terminal) and the gate (control terminal) of the first transistor M1 and the output node A. When the first switch SW_H1 and the second switch SW_L1 are closed at the same time, the first transistor M1 provides a voltage to the output node A, and the first transistor M1 can be understood as being effective. The first switch units 41b to 41c can all be understood with reference to the first switch unit 41a, and will not be repeated here.

[0033] That is, the plurality of first switch units ( Figure 2 41a to 41d) can increase or decrease the number of the first transistors in the on state in real time according to the change of the second control signal, thereby adjusting the bias voltage of the output node A.

[0034] It is understood that the embodiments of the present disclosure can adjust the bias current received by the transistor unit 20 based on the first control signal, thereby adjusting the bias voltage. Furthermore, the number of first transistors conducting in the transistor unit 20 can be changed based on the second control signal. That is, by changing the number of first transistors providing voltage to the output node A, the equivalent size of the transistor unit can be adjusted. The equivalent size is related to the bias voltage, so changing the number of first transistors conducting in the transistor unit can adjust the bias voltage. In this way, both the first control signal and the second control signal can adjust the bias voltage. In this case, if a per-bit coding change in the first control signal can result in a small bias voltage change, while a per-bit coding change in the second control signal can result in a large bias voltage change, that is, if the second control signal can provide a larger bias voltage adjustment range and the first control signal can provide a smaller adjustment accuracy, then the embodiments of the present disclosure can coarsely adjust the bias voltage using the second control signal, and then fine-tune the bias voltage using the first control signal. Thus, the embodiments of the present disclosure can not only improve the adjustment accuracy of the bias voltage, but also expand the adjustment range of the bias voltage.

[0035] In some embodiments of the present disclosure, reference Figure 2 The bias circuit 100 further includes a first digital-to-analog conversion circuit 31 and a second digital-to-analog conversion circuit 32. The first digital-to-analog conversion circuit 31 is configured to output the first control signal, and the second digital-to-analog conversion circuit 32 is configured to output the second control signal.

[0036] In the embodiments of the present disclosure, reference Figure 2 The first digital-to-analog conversion circuit 31 and the second digital-to-analog conversion circuit 32 may each include a device such as a digital-to-analog converter for converting digital signals into analog signals. The first control signal is used to adjust the magnitude of the bias current, and the second control signal is used to adjust the amount of voltage provided by the first transistor. For example, the first control signal has an X bit position and the second control signal has a Y bit position. Each bit position of the first control signal and the second control signal requires a transistor to implement. Since the first transistor receives the bias current, the first control signal that adjusts the amount of voltage provided by the first transistor and the second control signal that adjusts the bias current can achieve an X×Y bit adjustment. Compared to the related art, which generally adjusts the bias voltage only by adjusting the bias current, achieving an X×Y bit adjustment requires X×Y transistors, while the embodiment of the present disclosure only requires X+Y transistors to achieve an X×Y bit adjustment. In other words, compared to the related art, the embodiment of the present disclosure uses fewer transistors. Therefore, the embodiment of the present disclosure can reduce the area of ​​the bias circuit 10 and improve the integration level.

[0037] It should be noted that one or both of the first digital-to-analog conversion circuit 31 and the second digital-to-analog conversion circuit 32 may be located inside or outside the chip corresponding to the bias circuit, and this is not limited here.

[0038] In the embodiments of the present disclosure, reference Figure 2 , the equivalent size of the first transistor refers to the width-to-length ratio (W / L) of the first transistor. W is the channel width of the first transistor, and L is the channel length of the first transistor. When the number of first transistors providing voltage to the output node A increases, that is, when the equivalent size of the input transistor becomes larger, the current copied by the amplifier transistor Ma (output transistor) will also increase, and the bias voltage will also increase accordingly; conversely, when the number of first transistors providing voltage to the output node A decreases, that is, when the equivalent size of the input transistor becomes smaller, the current copied by the amplifier transistor Ma (output transistor) will decrease, and the bias voltage will also decrease accordingly. In this way, the embodiment of the present disclosure can adjust the equivalent size of the input transistor in the first current mirror by controlling the number of first transistors connected to the programmable current source 10, thereby adjusting the bias voltage.

[0039] The magnitude of the bias voltage V is related to the bias current I and the equivalent channel width W of the transistor unit 20 in the bias circuit. Generally, L is fixed. When L is constant, the relationship among the bias voltage V, the bias current I, and the equivalent channel width W can be expressed as follows:

[0040]

[0041] It should be noted that k in formula (1) is a constant related to the process, V th is the threshold voltage of the first transistor.

[0042] Continue to refer Figure 2 The programmable current source 10 can adjust the magnitude of the bias current I based on the first control signal, thereby changing the magnitude of the bias voltage V, thereby adjusting the accuracy of the bias voltage V output by the bias circuit 100. The transistor unit 20 can change the first switch unit ( Figure 2 41a to 41d) in the switching state, thereby controlling the first transistor ( Figure 2 M1 to 4Mn) provide the number of voltages, so that when the first transistor ( Figure 2 The more voltages provided by M1 to Mn in the embodiment, the larger the equivalent channel width W is, and thus the magnitude of the bias voltage V can be changed. Thus, the voltage range of the bias voltage V is expanded while ensuring the accuracy of the bias voltage V.

[0043] In the embodiments of the present disclosure, reference Figure 2, the equivalent sizes of the plurality of first transistors increase proportionally in sequence. For example, the equivalent sizes of the plurality of first transistors M1 to Mn gradually increase in multiples of 2, and the ratio of the equivalent sizes of the first transistors M1, M2...Mn is 1:2:...:2 n In this way, the embodiment of the present disclosure can further increase the adjustment range of the equivalent size of the input transistor, thereby further increasing the adjustment range of the bias voltage.

[0044] It should be noted that the equivalent sizes of the multiple first transistors are not limited to a multiple of 2. The equivalent sizes of the multiple first transistors can be adjusted according to actual needs and are not limited here.

[0045] In some embodiments of the present disclosure, reference Figure 2 The bias circuit 100 further includes a third switch SW_off connected between the programmable current source 10 and the ground.

[0046] In the embodiments of the present disclosure, reference Figure 2 When the bias switch SW_off is on, the programmable current source 10 is grounded, the gate voltages of transistors M0 to Mn are at ground, and transistors M0 to Mn are all in the off state, thereby turning off amplifier 200. Conversely, when the bias switch SW_off is off, the drains of one or more transistors M0 to Mn receive the bias current, the gate voltages of transistors M0 to Mn are in the on state, and thereby turning on amplifier 200. Thus, the bias switch SW_off can control whether to turn off the bias of amplifier 200.

[0047] Figure 3 2 is a schematic structural diagram of another optional transistor unit 20 provided in an embodiment of the present disclosure. It should be noted that the third switch SW_off can be a transistor. Figure 3 The programmable current source 10 and amplifier 200 shown can be referred to Figure 2 The embodiments are provided for understanding and will not be described in detail here.

[0048] In the embodiments of the present disclosure, reference Figure 3 , the embodiment of this disclosure does not set Figure 2 The second transistor M0 in the embodiment of the present disclosure is configured such that the first switching unit 41a-41d changes the number of the first terminals of the first transistors receiving the bias current based on the second control signal, and the number of the first terminals of the first transistors receiving the bias current is at least one; and / or the first switching unit changes the number of the control terminals of the first transistors connected to the output node based on the second control signal, and the number of the control terminals of the first transistors connected to the output node is at least one. In other words, because the embodiment of the present disclosure does not set Figure 2To ensure that the second transistor M0 in the circuit can form a first current mirror, at least one first transistor must be active and provide a voltage to the output node A. Therefore, the gate (control terminal) of at least one first transistor must receive a bias current to turn on the first transistor. Furthermore, the drain (first terminal) and gate (control terminal) of the first transistor must be connected to the output node A, forming a first current mirror with the amplifier transistor Ma to ensure that the output node A can provide an effective bias voltage.

[0049] Figure 4 This is an optional structural diagram provided by an embodiment of the present disclosure. Figure 4 The programmable current source 10, the first transistors (M1 to Mn), the second transistor M0 and the amplifier 200 shown can all be referred to as Figure 2 The embodiments are provided for understanding and will not be described in detail here.

[0050] In some embodiments of the present disclosure, reference Figure 4 Each first switch unit includes a first switch and a second switch. The first and second switches are opened or closed simultaneously based on a second control signal. For example, the first and second switches may be transistors, and the first switch unit 41a includes a first switch M11 and a second switch M21. The first and second switches M11 and M21 may receive the same bit code of the second control signal, thereby enabling the first and second switches M11 and M21 to be turned on or off simultaneously.

[0051] In the embodiments of the present disclosure, reference Figure 4 After the first terminals (drains) and control terminals (gates) of the first transistors M1 to Mn are short-circuited, they are connected to the programmable current source 10 via corresponding first switches M11 to M14 to receive bias current. Furthermore, after the first terminals (drains) and control terminals (gates) of the first transistors M1 to Mn are short-circuited, they are connected to the output node A via corresponding second switches M21 to M24 to provide voltage to the output node A. The second terminals (sources) of the first transistors M1 to Mn are grounded. For example, after the first terminal (drain) and control terminal (gate) of the first transistor M1 are short-circuited, they are connected to the programmable current source 10 via transistor M11 (first switch) to receive bias current. After the first terminal (drain) and control terminal (gate) of the first transistor M1 are short-circuited, they are connected to the output node A via transistor M21 (second switch). The same applies to the first transistors M2 to Mn. Thus, the bias circuit 100 can adjust the number of first transistors in the input portion of the first current mirror by simultaneously opening or closing the first and second switches.

[0052] In some embodiments of the present disclosure, reference Figure 4, the first switch and the second switch are both transistors. The equivalent on-resistance of the first switch and the second switch is less than or equal to 10 ohms, for example, 2 ohms, 4 ohms, 6 ohms, 8 ohms, etc. In this way, under the same bias current, the first switch (M11 to M14) and the second switch (M21 to M24) have a relatively small obstruction effect on the bias current. Thus, the power consumption of the first switch and the second switch is avoided, and interference with the adjustment process of the bias voltage is avoided. Specifically, the equivalent on-resistance is the resistance when the transistor is turned on. The equivalent on-resistance can be adjusted by setting the equivalent size of the transistor. The larger the equivalent size, the smaller the equivalent on-resistance.

[0053] Figure 5 is a structural diagram of another optional first switch unit provided in an embodiment of the present disclosure. It should be noted that: Figure 5 The first terminals of the second transistor M0 and the plurality of first transistors ( M1 to Mn) are all connected to the programmable current source 10 and the output node A.

[0054] In other embodiments of the present disclosure, Figure 5 The first switch unit includes single-pole double-throw switches SW_1 to SW_n. The single-pole double-throw switches connect the first terminals (drains) and control terminals (gates) of the corresponding first transistors M1 to Mn based on a second control signal, or connect the second terminals (sources) and control terminals (gates) of the corresponding first transistors M1 to Mn. The single-pole double-throw switches SW_1 to SW_n include a common terminal, a first throw terminal, and a second throw terminal. The common terminal is connected to the control terminals (gates) of the corresponding first transistors M1 to Mn, the first throw terminal is connected to the first terminals (drains) of the corresponding first transistors M1 to Mn, and the second throw terminal is connected to the second terminals (sources) of the corresponding first transistors M1 to Mn. When the common terminal is connected to the first throw terminal, the first terminals (drains) of the corresponding first transistors M1 to Mn are connected to the control terminals (gates). When the common terminal is connected to the second throw terminal, the second terminals (sources) of the corresponding first transistors M1 to Mn are connected to the control terminals (gates). For example, the first switch unit 41a includes a single-pole double-throw switch SW_1. For example, the single-pole double-throw switch SW_1 can turn on the gate and drain of the first transistor M1 based on the second control signal, thereby connecting the gate of the first transistor M1 to the programmable current source 10, receiving the bias current, turning on the first transistor M1, and then the first transistor M1 is active, outputting a voltage to the output node A. The single-pole double-throw switch SW_1 can turn on the gate and drain of the first transistor M1 based on the second control signal, thereby connecting the gate of the first transistor M1 to the ground terminal, and turning off the first transistor M1, then the first transistor M1 is inactive, and does not output a voltage to the output node A. Thus, the bias circuit 100 can adjust the number of first transistors in the input portion of the first current mirror through the single-pole double-throw switch.

[0055] Figure 6 1 is a schematic diagram of the structure of an optional programmable current source 10 provided in an embodiment of the present disclosure. Figure 6 The programmable current source 10 may include a current source 110, a second current mirror 120, a third current mirror 130, and a second switch unit 42. The current source 110 is used to provide an initial current IB. The second current mirror 120 includes a transistor M310 and a transistor M311 for proportionally replicating the initial current IB.

[0056] In the embodiments of the present disclosure, reference Figure 6 , the programmable current source 10 further includes a third current mirror 130. The third current mirror 130 includes a third transistor M39 and a plurality of fourth transistors ( Figure 6 M31 to M34 in the figure). The third transistor M39 and the plurality of fourth transistors ( Figure 6 Each of M31 to M34 in the embodiment includes a control terminal and a first terminal. The control terminal and the first terminal of the third transistor M39 are short-circuited, and the first terminal of the third transistor M39 receives the copied initial current. Figure 6 The gates (control terminals) of the M31 to M34 in the embodiment are connected to the gate (control terminal) of the third transistor M39. Figure 6 The drains (first ends) of the fourth transistors M31 to M34 (in the embodiment of FIG. 1 ) are connected together after passing through the second switch unit 42 to output the bias current IB_AMP. In other words, the fourth transistors M31 to M34 and the third transistor M39 form a third current mirror 130. The fourth transistors M31 to M34 replicate the initial current IB in the same proportion to generate I0 to I3, respectively.

[0057] In the embodiments of the present disclosure, reference Figure 4 , multiple second switch units ( Figure 4 M35 to M38 in the circuit), changes the switch state based on the first control signal, and controls the fourth transistor ( Figure 4 The effective number of M31 to M34 in the fourth transistor is that the current output by the fourth transistor can flow out of the second switch unit to form a part of the bias current IB_AMP. For example, the first digital-to-analog conversion circuit 31 can be a 2-bit digital-to-analog converter, and the first digital-to-analog conversion circuit 31 can control Figure 4 The conduction state of the transistors M35 to M38 in the circuit selects whether to output the corresponding I0 to I3, thereby changing the bias current IB_AMP output to the amplifier. For example, if multiple fourth transistors ( Figure 4 If the equivalent size of M31 to M34 in the circuit is the same, the bias current IB_AMP can achieve an output range of 1 to 4 times I0.

[0058] It should be noted that the plurality of fourth transistors ( Figure 4The equivalent dimensions of M31 to M34 in FIG can also be scaled proportionally to achieve different bias current ranges.

[0059] It should be noted that in Figure 6 In the illustrated embodiment, transistor M310 and transistor M311 form a second current mirror 120, and current source 110 is connected to second current mirror 120. In other embodiments, programmable current source 10 may not include second current mirror 120, and third current mirror 130 may be directly connected to current source 110 to replicate the initial current IB of current source 110.

[0060] Figure 7 is a schematic diagram of the structure of an optional amplifier 200 provided in an embodiment of the present disclosure, with reference to Figure 7 The amplifier 200 includes an amplifying transistor Ma and the bias circuit 100 in the above embodiment. The control terminal of the amplifying transistor Ma is connected to the output node of the circuit and receives the bias voltage output by the bias circuit 100.

[0061] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0062] The serial numbers of the embodiments of the present disclosure are for descriptive purposes only and do not represent the merits of the embodiments. The methods disclosed in the several method embodiments provided in the present disclosure can be arbitrarily combined to obtain new method embodiments when there is no conflict. The features disclosed in the several product embodiments provided in the present disclosure can be arbitrarily combined to obtain new product embodiments when there is no conflict. The features disclosed in the several method or device embodiments provided in the present disclosure can be arbitrarily combined to obtain new method embodiments or device embodiments when there is no conflict.

[0063] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present disclosure, and they should all be covered by the protection scope of the present disclosure.

Claims

1. A bias circuit for an amplifier, characterized in that The amplifier includes an amplifying transistor; The bias circuit comprises: A programmable current source generates a bias current with an adjustable magnitude based on a first control signal; The amplifying transistor is configured to receive a bias voltage; A transistor unit, used as an input transistor of a first current mirror, outputting a bias voltage; the output transistor of the first current mirror includes the amplifying transistor; The transistor unit includes: a plurality of first transistors, each comprising a first terminal and a control terminal; when the first terminal of any one of the first transistors receives the bias current, and the first terminal and the control terminal of the first transistor are short-circuited and connected to the amplifying transistor, the first transistor provides a voltage to the amplifying transistor; a plurality of first switch units, wherein the first switch units change the number of control terminals of the first transistors receiving the bias current and / or change the number of first terminals of the first transistors connected to the amplifying transistor based on a second control signal; A second transistor includes a first terminal and a control terminal, the control terminal of the second transistor receives the bias current, and the first terminal and the control terminal of the second transistor are short-circuited and connected to the amplifying transistor.

2. A bias circuit for an amplifier, characterized in that The amplifier includes an amplifying transistor; The bias circuit comprises: A programmable current source generates a bias current with an adjustable magnitude based on a first control signal; A transistor unit, used as an input transistor of a first current mirror; the output transistor of the first current mirror includes the amplifying transistor; the transistor unit includes: a plurality of first transistors, each of the first transistors including a first terminal and a control terminal; when the first terminal of any one of the first transistors receives the bias current, and the first terminal and the control terminal of the first transistor are short-circuited and connected to the amplifying transistor, the first transistor provides a voltage to the amplifying transistor; a plurality of first switching units, wherein the first switching units change the number of control terminals of the first transistors receiving the bias current based on a second control signal, and the number of control terminals of the first transistors receiving the bias current is at least one; and / or the first switching units change the number of first terminals of the first transistors connected to the amplifying transistor based on the second control signal, and the number of first terminals of the first transistors connected to the amplifying transistor is at least one.

3. The bias circuit according to claim 1 or 2, wherein: The programmable current source comprises: A current source, used to provide an initial current; a second current mirror, connected to the current source and configured to replicate the initial current; a third current mirror, comprising a third transistor and a plurality of fourth transistors, wherein the third transistor and the fourth transistor each include a control terminal and a first terminal, the control terminal and the first terminal of the third transistor being short-circuited, and the first terminal of the third transistor receiving the copied initial current; the control terminals of the plurality of fourth transistors being connected to the control terminal of the third transistor; and the first terminals of the plurality of fourth transistors being connected together for outputting the bias current; The second switch unit changes a switch state based on the first control signal to control the effective number of the fourth transistor.

4. The bias circuit according to claim 1 or 2, wherein: The first switch unit includes: a first switch and a second switch; wherein, After the first terminal and the control terminal of the first transistor are short-circuited, the first terminal is connected to the programmable current source through the corresponding first switch to receive the bias current, and the first terminal is connected to the amplifying transistor through the corresponding second switch; The first switch and the second switch are opened or closed simultaneously based on the second control signal.

5. The bias circuit according to claim 4, wherein: The first switch and the second switch are both transistors; wherein, The equivalent on-resistance of the first switch and the second switch is less than or equal to 10 ohms.

6. The bias circuit according to claim 1 or 2, wherein: The first switch unit includes a single-pole double-throw switch; wherein, The first transistors each further include a second terminal; the first terminals of the first transistors are each connected to the programmable current source and the amplifying transistor; The single-pole double-throw switch switches on the first terminal and the control terminal of the first transistor, or switches on the second terminal and the control terminal of the first transistor based on the second control signal.

7. The bias circuit according to claim 1 or 2, wherein: Also includes: a first digital-to-analog conversion circuit, configured to output the first control signal; and / or, The second digital-to-analog conversion circuit is configured to output the second control signal.

8. The bias circuit according to claim 1 or 2, wherein: The equivalent sizes of the plurality of first transistors increase proportionally in sequence.

9. The bias circuit according to claim 2, wherein: Also includes: A third switch is connected between the programmable current source and ground.

10. An amplifier, characterized in that: include: The bias circuit according to any one of claims 1 to 9; The amplifying transistor includes a control terminal, and the control terminal of the amplifying transistor receives the bias voltage output by the bias circuit.

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