Control circuit of domain controller

Abstract

The utility model discloses a control circuit of a domain controller, and relates to the technical field of circuits. Comprising a voltage monitoring circuit located between the storage battery and the primary power supply. The voltage monitoring circuit comprises a first processor, a first voltage division circuit and a first switch. When the voltage of the first input end is detected to be greater than or equal to an overvoltage threshold value, or the voltage of the second input end is detected to be smaller than an undervoltage threshold value; and controlling a first output end of the first processor to output a signal for controlling the first switch to be in an off state, and controlling a third output end of the first processor to output a signal for representing that the voltage of the storage battery is in an under-voltage or over-voltage state to a system-on-chip. Under-voltage or over-voltage detection of the storage battery is achieved, and when it is detected that the storage battery is in an under-voltage or over-voltage state, the first switch is controlled to be turned off, that is, under-voltage turn-off of the power supply can reduce static power consumption of a product during under-voltage; the overvoltage turn-off power supply prevents each stage of power supply from being damaged, and the reliability of the domain controller and the product is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of circuits, in particular to a control circuit of a domain controller. Background Art

[0002] Due to the complexity of current traffic and road conditions, automotive OEMs are placing increasingly stringent demands on component reliability design. Intelligent driving domain controllers, as controllers crucial to vehicle safety, are subject to extremely high reliability requirements, including ensuring the stability of the domain controller's power supply voltage and current, and ensuring that the power supply timing meets timing control requirements. However, failure to ensure domain controller reliability can negatively impact product reliability.

[0003] It can be seen that how to ensure the reliability of domain controllers is a technical problem that people in this field urgently need to solve. Utility Model Content

[0004] The purpose of the utility model is to provide a control circuit of a domain controller to solve the technical problem of low reliability of the domain controller.

[0005] In order to solve the above technical problems, the present utility model provides a control circuit of a domain controller, comprising: a voltage monitoring circuit located between a battery and a primary power supply;

[0006] The voltage monitoring circuit includes a first processor, a first voltage dividing circuit and a first switch;

[0007] The first end of the first voltage divider circuit and the first end of the first switch are both connected to the positive electrode of the battery;

[0008] The second end of the first voltage divider circuit is connected to the first input end of the first processor, and the third end of the first voltage divider circuit is connected to the second input end of the first processor;

[0009] The second end of the first switch is connected to the input end of the primary power supply and the second output end of the first processor respectively;

[0010] The first output end of the first processor is connected to the third end of the first switch, and is used to control the first output end of the first processor to output a first signal and control the third output end of the first processor to output a second signal to the system-level chip when it is detected that the voltage of the first input end is greater than or equal to an overvoltage threshold, or when it is detected that the voltage of the second input end is less than an undervoltage threshold; wherein, when the overvoltage threshold is greater than the undervoltage threshold, the first signal is used to control the first switch to be in a closed state, and the second signal is used to indicate that the voltage of the battery is in an undervoltage or overvoltage state.

[0011] Exemplarily, it further includes a first filtering circuit and a first diode;

[0012] The input end of the first filter circuit and the input end of the first diode are both connected to the positive electrode of the battery;

[0013] The output end of the first filtering circuit is grounded;

[0014] A first end of the first voltage divider circuit and a first end of the first switch are both connected to the output end of the first diode.

[0015] Exemplarily, the first filtering circuit includes a suppressor diode and a capacitor connected in parallel with the suppressor diode;

[0016] The first end of the capacitor connected in parallel with the suppression diode and the first end of the suppression diode are both connected to the positive electrode of the battery;

[0017] A second end of the capacitor connected in parallel with the suppression diode and a second end of the suppression diode are both grounded.

[0018] Exemplarily, the device further includes a second filtering circuit;

[0019] The input end of the second filter circuit is connected to the second end of the first switch;

[0020] The output end of the second filtering circuit is connected to the input end of the primary power supply.

[0021] Exemplarily, the first switch includes a first MOS transistor and a second MOS transistor;

[0022] The drain of the first MOS transistor is the first end of the first switch, the source of the first MOS transistor is connected to the source of the second MOS transistor, and the gate of the first MOS transistor and the gate of the second MOS transistor are the third end of the first switch;

[0023] The drain of the second MOS transistor serves as the second end of the first switch.

[0024] Exemplarily, a protection circuit is also included;

[0025] The protection circuit includes a first resistor, a second resistor, a third resistor and a first capacitor;

[0026] A first end of the first capacitor is connected to a first end of the first resistor, a second end of the first capacitor is grounded, a second end of the first resistor is respectively connected to a first output end of the first processor, a first end of the second resistor, and a first end of the third resistor, a second end of the second resistor is connected to a gate of the first MOS transistor, and a second end of the third resistor is connected to a gate of the second MOS transistor.

[0027] Exemplarily, the device further includes a shunt resistor and a current monitoring circuit connected in parallel with the shunt resistor;

[0028] The current monitoring circuit includes a second processor;

[0029] The first end of the shunt resistor is connected to the output end of the second filter circuit and the first input end of the second processor respectively;

[0030] The second end of the shunt resistor is connected to the input end of the primary power supply and the second input end of the second processor respectively;

[0031] The third input terminal and the fourth input terminal of the second processor are respectively connected to the pull-down resistor, and are used to configure the I2C address of the device; the fifth input terminal of the second processor is used to receive a clock signal, and the sixth input terminal of the second processor is used to receive data;

[0032] The system-level chip is connected to the first output terminal of the second processor, and is used to output a signal indicating an overcurrent when detecting that the current value is less than the current threshold;

[0033] The second output terminal of the second processor is connected to the output terminal of the secondary power supply.

[0034] Exemplarily, a third filtering circuit is further included;

[0035] The third filtering circuit includes a fourth resistor, a fifth resistor and a second capacitor;

[0036] The first end of the second capacitor is connected to the first end of the fourth resistor and the first input end of the second processor respectively;

[0037] The second end of the second capacitor is connected to the first end of the fifth resistor and the second input end of the second processor respectively;

[0038] The second end of the fourth resistor is connected to the second end of the shunt resistor; the second end of the fifth resistor is connected to the first end of the shunt resistor.

[0039] Exemplarily, the control circuit includes a multi-stage power supply, and the control circuit further includes a third processor and a second switch;

[0040] The first input terminal of the second switch is used to receive a wake-up signal, the second input terminal of the second switch is connected to the input terminal of the primary power supply, and the output terminal of the second switch is connected to the first input terminal of the third processor; wherein the wake-up signal is used to control the conduction or shutdown of the second switch;

[0041] The second input terminal of the third processor is connected to the first terminal of at least one pull-up resistor;

[0042] The second end of each pull-up resistor is connected to an output end of the third processor, and outputs an enable signal corresponding to each level of power supply according to the timing signal corresponding to each level of power supply.

[0043] Exemplarily, the first input terminal of the power supply of the third processor is connected to the input terminal of the primary power supply, and the output terminal of the power supply of the third processor is connected to the second input terminal of the second switch.

[0044] The control circuit of a domain controller provided by the present invention includes: a voltage monitoring circuit located between a battery and a primary power supply; the voltage monitoring circuit includes a first processor, a first voltage divider circuit, and a first switch; the first end of the first voltage divider circuit and the first end of the first switch are both connected to the positive terminal of the battery; the second end of the first voltage divider circuit is connected to the first input end of the first processor, and the third end of the first voltage divider circuit is connected to the second input end of the first processor; the second end of the first switch is respectively connected to the input end of the primary power supply and the second output end of the first processor. The first output end of the first processor is connected to the third end of the first switch, and is configured to control the first output end of the first processor to output a first signal and the third output end of the first processor to output a second signal to a system-on-chip when the voltage at the first input end is detected to be greater than or equal to an overvoltage threshold, or when the voltage at the second input end is detected to be less than an undervoltage threshold; wherein the first signal is used to control the first switch to be in a closed state, and the second signal is used to indicate whether the battery voltage is in an undervoltage or overvoltage state. It can be seen that the control circuit of the domain controller realizes the detection of undervoltage or overvoltage of the battery. When the battery is detected to be in an undervoltage or overvoltage state, the first processor sends a first signal to control the closure of the first switch, that is, undervoltage shuts off the power supply, which can reduce the static power consumption of the product during undervoltage; overvoltage shuts off the power supply, so that the power supplies of various levels of the product are not damaged, thereby improving the reliability of the domain controller and thus improving the reliability of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the embodiments of the present invention, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0046] Figure 1 A schematic diagram of a control circuit of a domain controller provided by an embodiment of the present utility model;

[0047] Figure 2A specific voltage monitoring circuit diagram provided by an embodiment of the utility model;

[0048] Figure 3 A reference diagram for selecting a MOS tube provided in an embodiment of the utility model;

[0049] Figure 4 A schematic diagram of a current monitoring circuit provided by an embodiment of the present utility model;

[0050] Figure 5 A schematic diagram of a monitoring circuit of a domain controller provided by an embodiment of the present utility model;

[0051] Figure 6 A specific current monitoring circuit diagram provided by an embodiment of the utility model;

[0052] Figure 7 A schematic diagram of a control circuit of another domain controller provided by an embodiment of the present utility model;

[0053] Figure 8 A schematic diagram of a power-on and power-off timing sequence provided by an embodiment of the present utility model;

[0054] Figure 9 A schematic diagram of a specific wake-up and sleep circuit for implementing power-on and power-off timing provided by an embodiment of the present utility model;

[0055] Figure 10 The embodiment of the present utility model provides Figure 9 A schematic diagram of the power-on sequence of the circuit diagram shown;

[0056] Figure 11 The embodiment of the present utility model provides Figure 9 The circuit diagram shown is a schematic diagram of the power-down timing. DETAILED DESCRIPTION

[0057] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0058] The core of the utility model is to provide a control circuit of a domain controller to solve the technical problem of low reliability of the domain controller.

[0059] Due to the complexity of current traffic and road conditions, automotive OEMs are placing increasingly stringent demands on component safety designs. Intelligent driving domain controllers, as controllers crucial to vehicle safety, are subject to extremely high safety requirements. However, few products on the market offer undervoltage or overvoltage protection for the KL30 battery power supply. This new device monitors the KL30 in the domain controller through hardware, implementing overvoltage and undervoltage protection to ensure product safety and reliability.

[0060] In order to enable those skilled in the art to better understand the present invention, the present invention will be described in further detail below with reference to the accompanying drawings and specific implementation methods. Figure 1 A schematic diagram of a control circuit of a domain controller provided by an embodiment of the present utility model is shown as follows: Figure 1 As shown, it includes: a voltage monitoring circuit located between the battery and the primary power supply;

[0061] The voltage monitoring circuit includes a first processor, a first voltage dividing circuit and a first switch;

[0062] The first end of the first voltage divider circuit and the first end of the first switch are both connected to the positive electrode of the battery;

[0063] The second end of the first voltage divider circuit is connected to the first input end of the first processor, and the third end of the first voltage divider circuit is connected to the second input end of the first processor;

[0064] The second end of the first switch is connected to the input end of the primary power supply and the second output end of the first processor respectively;

[0065] The first output terminal of the first processor is connected to the third terminal of the first switch, and is used to control the first output terminal of the first processor to output a first signal and control the third output terminal of the first processor to output a second signal to a system on chip (SOC) when it is detected that the voltage of the first input terminal is greater than or equal to an overvoltage threshold, or when it is detected that the voltage of the second input terminal is less than an undervoltage threshold. Wherein, when the overvoltage threshold is greater than the undervoltage threshold, the first signal is used to control the first switch to be in a closed state, and the second signal is used to indicate that the battery voltage is in an undervoltage or overvoltage state.

[0066] A KL30 is used as the positive terminal of the car battery, with a normal operating voltage between 9 and 16V. The primary power supply used is a buck step-down power supply. To improve the stability of the domain controller, the present invention incorporates a voltage monitoring circuit within the domain controller's control circuitry, comprising a first processor, a first voltage divider circuit, and a first switch. The first voltage divider circuit and the first switch are not specified and are determined based on practical circumstances. In implementation, a metal-oxide-semiconductor field-effect transistor (MOSFET) can be selected as the first switch. Figure 2 A specific voltage monitoring circuit diagram provided by the embodiment of the present utility model is as follows: Figure 2 As shown, the first switch used includes a first MOS transistor Q1 and a second MOS transistor Q2. The drain of the first MOS transistor Q1 is the first end of the first switch, the source of the first MOS transistor Q1 is connected to the source of the second MOS transistor Q2, the gate of the first MOS transistor Q1 and the gate of the second MOS transistor Q2 are the third end of the first switch; the drain of the second MOS transistor Q2 is the second end of the first switch. The first voltage divider circuit used is as follows Figure 2 As shown, including the first voltage divider resistor R 分压1 (ie PR01), the second voltage divider resistor R 分压2 (ie PR02) and the third voltage divider resistor R 分压3 (i.e. PR03).

[0067] The first processor detects the relationship between the voltage at the first input terminal and the overvoltage threshold. The overvoltage threshold is not limited and is determined according to the actual circuit. The first processor detects the relationship between the voltage at the second input terminal and the undervoltage threshold. The undervoltage threshold is not limited and is determined according to the actual circuit. Figure 2 For example, the first voltage divider resistor R 分压1 , the second voltage divider resistor R 分压2 and the third voltage divider resistor R 分压3 Configurable overvoltage (OV) and undervoltage (UV) thresholds.

[0068] Figure 2 The selection of each resistor in the first voltage divider circuit and the setting of the overvoltage threshold and undervoltage threshold specifically include the following process:

[0069] 1) Select the maximum tolerable offset error voltage VOS(UV) of the UV pin as 3mv, divided by the worst-case UV pin leakage current ILEAK (10nA), which is the sum of PR02+PR03:

[0070] PR02+PR03=VOS(UV) / ILEAK;

[0071] 2) Select the desired UV turn-off threshold UVTH and obtain the value of PR01:

[0072] PR01=[VOS(UV) / ILEAK]*[(UVTH-0.5V) / 0.5V];

[0073] 3) Select the desired OV turn-off threshold OVTH and derive PR02 and PR03:

[0074] PR03=[VOS(UV) / ILEAK +PR01] / OVTH*0.5V;

[0075] PR02=VOS(UV) / ILEAK –PR03;

[0076] According to OEM customer requirements, the Controller Area Network (CAN) communication voltage range is 6-26V, while the maximum supply voltage VIN of the first-level BUCK chip is 36V. If UVTH = 5V and OVTH = 30V, then:

[0077] 1) PR02+PR03=VOS(UV) / ILEAK=3mV / 10nA=300k;

[0078] 2) PR01=300k*[(5V-0.5V) / 0.5V]=2.7M;

[0079] 3) PR03 = (300K + 2.7M) / 30 * 0.5 = 50K, taking the nearest resistance value of 47k; then PR2 = 300K - 47K = 253K, taking the nearest resistance value of 240k. Based on the above formula, we can infer the actual OV = 31.77V and UV = 5.2V.

[0080] In addition, when selecting the MOS tube in the first switch, Figure 3 Make selection. Figure 3 A reference diagram for selecting a MOS tube provided by the embodiment of the present utility model. Figure 2 In the example, OV = 31.77V, UV = 5.2V. Within the range of UV = 5.2V and OV = 31.77V, the ΔVGATE range is 8V to 13V. This means that the MOS transistor's VGS(th) is less than 8V and its VGS(Max) is greater than 13V. Furthermore, VDS(Max) must be greater than 31.77V and ID(Max) must be greater than the product's operating current of 2A. Select a MOS transistor that meets these requirements.

[0081] When the input voltage KL30 is within the OV and UV set points, the level signal of the first output pin of the first processor is high, the first MOS transistor and the second MOS transistor are in the on state, and KL30 can supply power to the product; when the input voltage KL30 is outside the OV and UV set points, the level signal of the first output pin of the first processor is pulled low, the first MOS transistor and the second MOS transistor are in the off state, realizing overvoltage and undervoltage protection for the product, and at the same time pulling low the pin of the third output end of the first processor (such as the FAULT_L pin), and an error indication is output to the SOC.

[0082] Specifically, when it is detected that the voltage of the first input terminal is greater than or equal to the overvoltage threshold, it is determined that the KL30 voltage is in an overvoltage state, and the first output terminal of the first processor is controlled to output a first signal for controlling the first switch to be in a closed state, thereby turning off the first switch. This operation ensures that the power supply of each level of the product is not damaged and improves the reliability of the domain controller. At the same time, the first processor can send a signal to the SOC through the third output terminal (corresponding to the FAULT_L pin) to indicate that the KL30 voltage is in an overvoltage state, that is, to issue an overvoltage alarm.

[0083] When it is detected that the voltage of the second input terminal is less than the undervoltage threshold, it is determined that the KL30 voltage is in an undervoltage state, and the second output terminal of the first processor is controlled to output a first signal for controlling the first switch to be in a closed state, thereby closing the first switch. This operation can reduce the static power consumption of the product during undervoltage. At the same time, the first processor can send a signal to the SOC to indicate that the KL30 voltage is in an undervoltage state, that is, to issue an undervoltage alarm.

[0084] This embodiment uses the control circuit of the domain controller to detect undervoltage or overvoltage of the battery. When the battery is detected to be in an undervoltage or overvoltage state, the first processor sends a first signal to control the closure of the first switch. In other words, undervoltage shuts off the power supply, which can reduce the static power consumption of the product during undervoltage; overvoltage shuts off the power supply, which prevents damage to the power supplies at all levels of the product, thereby improving the reliability of the domain controller and thus the reliability of the product.

[0085] In order to improve the stability of the control circuit of the domain controller, the control circuit of the domain controller further includes a first filter circuit and a first diode;

[0086] The input end of the first filter circuit and the input end of the first diode are both connected to the positive electrode of the battery;

[0087] An output terminal of the first filter circuit is grounded;

[0088] The first end of the first voltage divider circuit and the first end of the first switch are both connected to the output end of the first diode.

[0089] Specifically, the first filtering circuit includes a suppressor diode and a capacitor connected in parallel with the suppressor diode. A first end of the capacitor connected in parallel with the suppressor diode and a first end of the suppressor diode are both connected to the positive electrode of the battery; a second end of the capacitor connected in parallel with the suppressor diode and a second end of the suppressor diode are both grounded.

[0090] Figure 2 The first diode D1 is a dual-path diode (i.e., anti-reverse diode), and the first filter circuit is as follows Figure 2 As shown, it includes a transient voltage suppressor (TVS) diode and two parallel capacitors. The TVS diode provides electrostatic discharge (ESD) protection, suppressing transient voltages, while the two parallel capacitors provide high-frequency filtering. Using multiple capacitors in series in each circuit not only allows for higher voltage drops but also prevents the KL30 from shorting out due to single capacitor failure. It's worth noting that the power input of the first processor can be directly connected to the KL30 power supply.

[0091] In addition to the above-mentioned high-frequency filtering, in order to further improve the signal quality, the control circuit of the domain controller also includes a second filtering circuit;

[0092] An input end of the second filter circuit is connected to the second end of the first switch;

[0093] The output end of the second filter circuit is connected to the input end of the primary power supply.

[0094] Figure 2 The second filtering circuit used is a π filter composed of an inductor and multiple capacitors, which is used for low-frequency filtering.

[0095] To protect the first switch, a protection circuit is also provided in the control circuit of the domain controller; the protection circuit includes a first resistor R1, a second resistor R2, a third resistor R3, and a first capacitor C1. The first end of the first capacitor C1 is connected to the first end of the first resistor R1, the second end of the first capacitor C1 is grounded, the second end of the first resistor R1 is connected to the first output end of the first processor, the first end of the second resistor R2, and the first end of the third resistor R3, respectively. The second end of the second resistor R2 is connected to the gate of the first MOS transistor Q1, and the second end of the third resistor R3 is connected to the gate of the second MOS transistor Q2.

[0096] The second resistor R2 and the third resistor R3 can suppress high-frequency oscillation of the first MOS transistor Q1 and the second MOS transistor Q2. The RC network composed of the first capacitor C1 and the first resistor R1 can limit the inrush current when the first MOS transistor Q1 and the second MOS transistor Q2 are turned on.

[0097] In the above, the voltage of KL30 is monitored by the voltage monitoring circuit. In order to further improve the stability of the domain controller, a current monitoring circuit is set in the control circuit of the domain controller. Figure 4 A schematic diagram of a current monitoring circuit provided by an embodiment of the present utility model is shown as follows: Figure 4 As shown, the control circuit of the domain controller also includes a shunt resistor and a current monitoring circuit connected in parallel with the shunt resistor.

[0098] The current monitoring circuit includes a second processor;

[0099] The first end of the shunt resistor is connected to the output end of the second filter circuit and the first input end of the second processor respectively;

[0100] The second end of the shunt resistor is connected to the input end of the primary power supply and the second input end of the second processor respectively;

[0101] The third input terminal and the fourth input terminal of the second processor are respectively connected to the pull-down resistors for configuring the I2C address of the device; the fifth input terminal (e.g., the SCL port) of the second processor is used to receive a clock signal (e.g., SOC_SCL), and the sixth input terminal (e.g., the SDA port) of the second processor is used to receive data (e.g., SOC_SDA);

[0102] The system-level chip is connected to the first output end (corresponding to the ALERT port) of the second processor, and is used to output a signal indicating overcurrent when a current value is detected to be less than a current threshold; the second output end (such as the VS port) of the second processor is connected to the output end of the secondary power supply (such as PMIC_OUT1 corresponding to the PMIC).

[0103] In addition, in order to ensure the stability of the signal, the control circuit of the domain controller also includes a third filtering circuit;

[0104] The third filtering circuit includes a fourth resistor, a fifth resistor and a second capacitor;

[0105] The first end of the second capacitor is respectively connected to the first end of the fourth resistor and the first input end of the second processor;

[0106] The second end of the second capacitor is respectively connected to the first end of the fifth resistor and the second input end of the second processor;

[0107] The second end of the fourth resistor is connected to the second end of the shunt resistor; the second end of the fifth resistor is connected to the first end of the shunt resistor.

[0108] After the voltage monitoring circuit and the current monitoring circuit are set in the control circuit of the domain controller, the schematic diagram of the monitoring circuit of the domain controller is as follows: Figure 5 As shown, Figure 5A schematic diagram of a monitoring circuit for a domain controller provided by an embodiment of the present invention. The monitoring circuit includes an ESD protection and high-frequency filtering circuit, followed by an anti-reverse diode, a voltage monitoring circuit, a π filter circuit, a shunt resistor, a first-level buck power supply, and a power management circuit (PMIC). The voltage monitoring circuit's FAULT port is connected to a GPIO pin on the SOC. The current monitoring circuit is connected in parallel across the shunt resistor, with the BAT_IN and BAT_IN+ power supplies on either side of the shunt resistor. The PMIC's PMIC_OUT1 is connected to the second output port (VS port) of the second processor in the current monitoring circuit, providing power to the second processor via PMIC_OUT1. The second processor's first output port (ALERT port) in the current monitoring circuit is connected to another GPIO port on the SOC. Furthermore, the current monitoring circuit's I2C port is connected to the SOC's I2C port.

[0109] The KL30 passes through the ESD protection and high-frequency filtering circuits, then through the anti-reverse diode to the voltage monitoring circuit. The voltage monitoring circuit monitors the KL30 voltage in real time to ensure that the product's KL30 voltage operates within the set range. If the voltage exceeds the range, an error signal is output to the SOC through the FAULT pin. The power supply after the voltage monitoring circuit passes through the π filter circuit to obtain a relatively clean BAT_IN power supply.

[0110] According to the power path, the BAT_IN power supply is converted to the BAT_IN+ power supply after passing through a shunt resistor. The BAT_IN+ power supply serves as the input of the first-stage buck power supply. The output of the first-stage buck power supply serves as the input of the PMIC. One of the PMIC outputs serves as the power input of the current monitoring circuit. According to the signal path, the current monitoring circuit periodically monitors the voltage drop across the shunt resistor. If the monitored voltage drop exceeds the set limit, the ALERT pin alerts the SoC, triggering product functional degradation and reporting an overcurrent fault.

[0111] In order to enable those skilled in the art to better understand the current monitoring circuit provided by the present invention, a specific current monitoring circuit diagram is provided below for explanation. Figure 6 A specific current monitoring circuit diagram provided by the embodiment of the present utility model. Figure 6 As shown, the shunt resistor R 分流 The two ends of the second processor are connected to the first input terminal and the second input terminal respectively, and the third input terminal of the second processor is connected to the first pull-down resistor R 下拉1 Connect the fourth input terminal of the second processor to the second pull-down resistor R 下拉2 The other end of the first pull-down resistor R pull-down 1 and the other end of the second pull-down resistor R pull-down 2 are both grounded. 下拉1 and the second pull-down resistor R 下拉2Used to configure the I2C address of the device. In addition, the third filter circuit is as follows Figure 6 The circuit consists of the fourth resistor R4, the fifth resistor R5, and the second capacitor C2. The second capacitor C2 is used to filter out high-frequency noise during sampling. The fourth resistor R4 and the fifth resistor R5, together with the second capacitor, eliminate high-frequency noise and excessive dV / dt. The first output terminal (ALERT port) of the second processor is connected to PMIC_OUT1, which serves as the reference power source for the resistor signal POWER_ALERT (alarm). The ALERT port is an open-drain output, and a pull-up resistor can be set on the line output by the ALERT port. The second processor also has a seventh input terminal (VBUS) port connected to BAT_IN+ to monitor BAT_IN+.

[0112] The specific implementation method of the current monitoring circuit is:

[0113] The first input terminal and the second output terminal of the second processor are respectively connected to the shunt resistor R 分流 The BAT_IN and BAT_IN+ power supplies on both sides are used to monitor the shunt resistor R 分流 The voltage at both ends. The normal operating current of the product is Imax=2A, set the KL30 overcurrent limit value Ilimit=3A, and select the shunt resistor R 分流 =0.005Ω, then the shunt resistance R 分流 The shunt voltage Vlimit=Ilimit*R2=15mV. The SOC configures the SOL bit of the Mask / Enable register to 1 through I2C communication, enables the shunt voltage overlimit (SOL) function, and sets the overcurrent limit value to 3A and the shunt resistor R 分流 The calculated shunt voltage limit for 0.005Ω is 15mV. The value of the configured Alert Limit register is 6000, that is, the shunt voltage limit Vlimit = 6000*2.5uV = 15mV.

[0114] The SOC monitors the ALERT port of the second processor every 100ms. When the KL30 current is less than 3A, the ALERT port outputs a high level. When the KL30 current is greater than 3A, the ALERT port outputs a low level to the SOC, triggering product functional degradation and reporting an overcurrent fault.

[0115] The domain controller described above includes a voltage monitoring circuit, which implements undervoltage shutdown and overvoltage shutdown of the KL30 power supply to achieve undervoltage and overvoltage protection. Specifically, undervoltage shutdown of the KL30 power supply can reduce the static power consumption of the product during undervoltage; overvoltage shutdown of the KL30 power supply prevents damage to the product's BUCK power supply; and current monitoring of the KL30 power supply is implemented through the current monitoring circuit, achieving overcurrent protection, and enhancing the product's safety redundancy design through overcurrent monitoring.

[0116] In addition to the aforementioned voltage and current monitoring to ensure domain controller stability, current automotive OEMs have basic wake-up and sleep functionality requirements for components. These requirements also place specific demands on the power-on sequence of power chips after wake-up and power-off sequence after sleep. Most current solutions on the market focus on achieving wake-up and sleep without rigorous consideration of the timing of primary and secondary power supplies, resulting in reduced domain controller stability. To improve domain controller stability, the domain control circuitry of the present invention also includes wake-up and sleep circuitry for achieving power-on and power-off sequencing. Figure 7 A schematic diagram of a control circuit of another domain controller provided by an embodiment of the present utility model is shown as follows: Figure 7 As shown in the figure, BAT_IN+ serves as the power input for the first-level BUCK power supply and the wake-up and sleep circuits used to implement power-up and power-down sequencing. The output of the first-level BUCK power supply, BUCK_OUT, serves as the input for the second-level PMIC power supply.

[0117] Power-on process: KL30 is always powered. After the wake-up source is triggered, the control circuit pulls up the BUCK_EN and PMIC_EN signals in sequence to wake up the first device to be awakened (the first-level BUCK power supply) and the second device to be awakened (the second-level PMIC power supply). The PMIC power output supplies power to the SOC, which in turn powers on all parts of the domain controller to complete the wake-up.

[0118] Power-off process: After the wake-up source is removed, the control circuit pulls down the PMIC_EN and BUCK_EN signals in sequence. That is, after the secondary PMIC power supply fully powers down the chip output power supplies, the primary BUCK power supply is powered down, completing hibernation.

[0119] Figure 8 This is a schematic diagram of a power-on and power-off timing sequence provided by an embodiment of the present utility model. Figure 8 As shown in the figure, during the power-on process, the time from the enable signal BUCK_EN of the primary power supply to the enable signal PMIC_EN of the secondary PMIC power supply is T2+T3, and T2+T3 depends on the power supply characteristics of the primary power supply. The time t1 set by the timing chip of the control circuit needs to be greater than T2+T3 to retain sufficient margin.

[0120] Power-off process: The timing chip of the control circuit preferentially pulls down PMIC_EN. The PMIC itself has its own power-off logic. If the PMIC power-off time is less than 10ms, the timing chip requires that the time T5 from when the enable signal PMIC_EN of the secondary PMIC power supply is pulled down to when the enable signal BUCK_EN of the primary power supply is pulled down is greater than 10ms to ensure normal power-off of the product.

[0121] In summary, whether powering on or off, the time interval between the two enabling states of the timing chip must be precisely controlled to ensure normal power on and off. Failure to do so will result in power on and off failures, resulting in the product not being able to operate normally or being unable to sleep.

[0122] In order to meet the power-on and power-off timing requirements of each level of power supply, the control circuit provided by the present invention includes multiple levels of power supply, and the control circuit also includes a third processor and a second switch;

[0123] The first input terminal of the second switch is used to receive a wake-up signal, the second input terminal of the second switch is connected to the input terminal of the primary power supply, and the output terminal of the second switch is connected to the first input terminal of the third processor; wherein the wake-up signal is used to control the conduction or closing of the second switch;

[0124] A second input terminal of the third processor is connected to a first terminal of at least one pull-up resistor;

[0125] The second end of each pull-up resistor is connected to an output end of the third processor, and the second end of each pull-up resistor outputs an enable signal corresponding to each power supply according to the timing signal corresponding to each power supply.

[0126] There is no limitation on the second switch. Figure 9 The second switch used in the embodiment is a switch composed of two transistors. Figure 9 A schematic diagram of a specific wake-up and sleep circuit for implementing power-up and power-down sequence according to an embodiment of the present invention is provided. The second switch Q2 includes a first transistor O1 and a second transistor O2. The first transistor O1 is an NPN transistor; the second transistor O2 is a PNP transistor.

[0127] The base of the first transistor O1 is the first input end of the second switch Q2, the emitter of the first transistor O1 is grounded, the collector of the first transistor O1 is connected to the base of the second transistor O2, the emitter of the second transistor O2 is the second input end of the second switch Q2, and the collector of the second transistor Q2 is the output end of the second switch Q2. Figure 9 The second switch Q2 is a combination circuit of NPN and PNP, which can realize that when pin 2 is high, pin 3 and pin 4 are turned on, and when pin 2 is low, pin 3 and pin 4 are not turned on.

[0128] In the control circuit of the domain controller provided by the present invention, the first input end of the power supply of the third processor is connected to the input end of the primary power supply, and the output end of the power supply of the third processor is connected to the second input end of the second switch.

[0129] Since the third processor's power input voltage range is 2.7-5.5V, a power supply is required. A low-cost, large-dropout linear regulator (LDO) with a 3.5-36V input voltage range is recommended. The BAT_IN+ power supply can be supplied by a KL30 anti-reverse filter. Figure 9 There are two wake-up sources in the system. The LDO power supply is used to power the third processor. Pin 3 of the second switch is connected to the first input terminal of the third processor through a resistor. The second input terminal of the third processor is connected to the first terminals of two pull-up resistors respectively, and the second terminals of each pull-up resistor are connected to an output terminal of the third processor respectively, outputting enable signals BUCK_EN and PMIC_EN.

[0130] In order to improve the signal quality, the control circuit of the domain controller further includes an anti-reverse circuit, a fourth filtering circuit and a fifth filtering circuit;

[0131] The input end of the anti-backflow circuit is connected to the input end of the primary power supply, the output end of the anti-backflow circuit is connected to the first input end of the power supply of the third processor and the input end of the fourth filter circuit respectively, the first output end of the fourth filter circuit is connected to the second input end of the power supply of the third processor, and the second output end of the fourth filter circuit is grounded;

[0132] A first end of the fifth filtering circuit is connected to the output end of the power supply of the third processor; a second end of the fifth filtering circuit is grounded.

[0133] Figure 9 In the embodiment, the anti-reverse circuit includes a second diode D2 (anti-reverse diode); the fourth filter circuit includes a sixth resistor R6 and a third capacitor C3; and the fifth filter circuit includes a fourth capacitor C4 and a fifth capacitor C5.

[0134] When there are multiple wake-up sources, in order to avoid interference between different signal sources, the control circuit of the domain controller also includes a signal isolation circuit;

[0135] The input end of the signal isolation circuit is connected to each wake-up signal respectively, and the output end of the second isolation circuit is connected to the first input end of the second switch.

[0136] like Figure 9 The signal isolation circuit used in the embodiment includes a third diode D3 and a fourth diode D4.

[0137] To protect the second switch, the control circuit of the domain controller further includes a second voltage dividing circuit and a third voltage dividing circuit;

[0138] A first end of the second voltage divider circuit is connected to the emitter of the second transistor; a second end of the second voltage divider circuit is connected to the base of the second transistor; and a third end of the second voltage divider circuit is connected to the collector of the first transistor;

[0139] A first end of the third voltage divider circuit is connected to the emitter of the first transistor, a second end of the third voltage divider circuit is connected to the base of the first transistor, and a third end of the third voltage divider circuit is used to receive the wake-up signal.

[0140] Figure 9 In the embodiment, the second voltage divider circuit includes two resistors between pin 4 and pin 5 of the second switch Q2, and the third voltage divider circuit includes two resistors between pin 1 and pin 2 of the second switch Q2.

[0141] In order to further improve the signal quality, the control circuit of the domain controller further includes a sixth filtering circuit and a seventh filtering circuit;

[0142] A first end of the sixth filter circuit is connected to the third end of the third voltage divider circuit, a second end of the sixth filter circuit is connected to the emitter of the first diode, and is grounded;

[0143] A first end of the seventh filtering circuit is connected to the first input end of the third processor, and a second end of the seventh filtering circuit is grounded.

[0144] Figure 9 The sixth filtering circuit includes a sixth capacitor C6, and the seventh filtering circuit includes a seventh capacitor C7 and a seventh resistor R7.

[0145] Below Figure 9 The power-on and power-off processes of the wake-up and sleep circuits used to implement the power-on and power-off sequences are described.

[0146] 1) Power-on process: By pulling high any wake-up source signal KL15, CAN_INH, or SOC_GPIO, pins 3 and 4 of the second switch are turned on through the third or fourth diode, thereby pulling high the signal 3 at the first input terminal of the third processor. The BUCK_EN signal at the first output terminal of the third processor is first pulled high, and then the PMIC_EN signal at the second output terminal is pulled high, thereby achieving wake-up.

[0147] 2) Power-off process: The wake-up source is pulled low, pins 3 and 4 of the second switch are not conducting, and then the signal at the first input terminal of the third processor is pulled low through the seventh resistor. The PMIC_EN signal at the second output terminal of the third processor is first pulled low, and then the BUCK_EN signal at the first output terminal is pulled low, thereby achieving sleep.

[0148] Figure 10 The embodiment of the present utility model provides Figure 9 The circuit diagram shown is a schematic diagram of the power-on timing. Figure 11 The embodiment of the present utility model provides Figure 9 The schematic diagram of the power-off sequence of the circuit diagram shown is shown. Assuming that the third processor is used, Figure 10 and Figure 11 The time td1~td6 in the above table is 30ms. Figure 8 T2+T3 can also meet the power-off process Figure 8 The T5, power on and power off time is not too long, select different primary power supply and secondary PMIC, 30ms time interval can also meet the requirements. Figure 9 The third control chip supports 2 enable outputs. In practice, it can also support multiple enable outputs, which is scalable.

[0149] The control circuit provided in this embodiment includes a third processor and a second switch, supporting multiple wake-up source inputs. The third processor can also precisely control the output signal intervals, ensuring power-up and power-down timing for different voltage rails. This precise control of the timing chip's output signal intervals satisfies power-up and power-down requirements and improves product reliability.

[0150] The above is a detailed introduction to the control circuit of a domain controller provided by the present invention. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, the present invention can also be improved and modified in several ways, and these improvements and modifications also fall within the scope of protection of the present invention.

[0151] It should also be noted that, in this specification, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

Claims

1. A control circuit of a domain controller, characterized in that: include: A voltage monitoring circuit located between the battery and the primary power supply; The voltage monitoring circuit includes a first processor, a first voltage dividing circuit and a first switch; The first end of the first voltage divider circuit and the first end of the first switch are both connected to the positive electrode of the battery; The second end of the first voltage divider circuit is connected to the first input end of the first processor, and the third end of the first voltage divider circuit is connected to the second input end of the first processor; The second end of the first switch is connected to the input end of the primary power supply and the second output end of the first processor respectively; The first output end of the first processor is connected to the third end of the first switch, and is used to control the first output end of the first processor to output a first signal and control the third output end of the first processor to output a second signal to the system-level chip when it is detected that the voltage of the first input end is greater than or equal to an overvoltage threshold, or when it is detected that the voltage of the second input end is less than an undervoltage threshold; wherein, when the overvoltage threshold is greater than the undervoltage threshold, the first signal is used to control the first switch to be in a closed state, and the second signal is used to indicate that the voltage of the battery is in an undervoltage or overvoltage state.

2. The control circuit of the domain controller according to claim 1, characterized in that: Also includes a first filtering circuit and a first diode; The input end of the first filter circuit and the input end of the first diode are both connected to the positive electrode of the battery; The output end of the first filtering circuit is grounded; A first end of the first voltage divider circuit and a first end of the first switch are both connected to the output end of the first diode.

3. The control circuit of the domain controller according to claim 2, characterized in that: The first filtering circuit includes a suppressor diode and a capacitor connected in parallel with the suppressor diode; The first end of the capacitor connected in parallel with the suppression diode and the first end of the suppression diode are both connected to the positive electrode of the battery; A second end of the capacitor connected in parallel with the suppression diode and a second end of the suppression diode are both grounded.

4. The control circuit of the domain controller according to claim 1, characterized in that: Also comprising a second filtering circuit; The input end of the second filter circuit is connected to the second end of the first switch; The output end of the second filtering circuit is connected to the input end of the primary power supply.

5. The control circuit of the domain controller according to any one of claims 1 to 4, characterized in that: The first switch includes a first MOS transistor and a second MOS transistor; The drain of the first MOS transistor is the first end of the first switch, the source of the first MOS transistor is connected to the source of the second MOS transistor, and the gate of the first MOS transistor and the gate of the second MOS transistor are the third end of the first switch; The drain of the second MOS transistor serves as the second end of the first switch.

6. The control circuit of the domain controller according to claim 5, characterized in that: Also includes protection circuits; The protection circuit includes a first resistor, a second resistor, a third resistor and a first capacitor; A first end of the first capacitor is connected to a first end of the first resistor, a second end of the first capacitor is grounded, a second end of the first resistor is respectively connected to a first output end of the first processor, a first end of the second resistor, and a first end of the third resistor, a second end of the second resistor is connected to a gate of the first MOS transistor, and a second end of the third resistor is connected to a gate of the second MOS transistor.

7. The control circuit of the domain controller according to claim 4, characterized in that: Also includes a shunt resistor and a current monitoring circuit connected in parallel with the shunt resistor; The current monitoring circuit includes a second processor; The first end of the shunt resistor is connected to the output end of the second filter circuit and the first input end of the second processor respectively; The second end of the shunt resistor is connected to the input end of the primary power supply and the second input end of the second processor respectively; The third input terminal and the fourth input terminal of the second processor are respectively connected to the pull-down resistor, and are used to configure the I2C address of the device; the fifth input terminal of the second processor is used to receive a clock signal, and the sixth input terminal of the second processor is used to receive data; The system-level chip is connected to the first output terminal of the second processor, and is used to output a signal indicating an overcurrent when detecting that the current value is less than the current threshold; The second output terminal of the second processor is connected to the output terminal of the secondary power supply.

8. The control circuit of the domain controller according to claim 7, characterized in that: Also comprising a third filtering circuit; The third filtering circuit includes a fourth resistor, a fifth resistor and a second capacitor; The first end of the second capacitor is connected to the first end of the fourth resistor and the first input end of the second processor respectively; The second end of the second capacitor is connected to the first end of the fifth resistor and the second input end of the second processor respectively; The second end of the fourth resistor is connected to the second end of the shunt resistor; the second end of the fifth resistor is connected to the first end of the shunt resistor.

9. The control circuit of the domain controller according to claim 1, characterized in that: The control circuit includes a multi-stage power supply, and the control circuit also includes a third processor and a second switch; The first input terminal of the second switch is used to receive a wake-up signal, the second input terminal of the second switch is connected to the input terminal of the primary power supply, and the output terminal of the second switch is connected to the first input terminal of the third processor; wherein the wake-up signal is used to control the conduction or shutdown of the second switch; The second input terminal of the third processor is connected to the first terminal of at least one pull-up resistor; The second end of each pull-up resistor is connected to an output end of the third processor, and outputs an enable signal corresponding to each level of power supply according to the timing signal corresponding to each level of power supply.

10. The control circuit of the domain controller according to claim 9, characterized in that: The first input end of the power supply of the third processor is connected to the input end of the primary power supply, and the output end of the power supply of the third processor is connected to the second input end of the second switch.

Images