Photoelectric conversion device and electronic equipment

Abstract

The utility model relates to the technical field of photoelectric sensors, and discloses a photoelectric conversion device and electronic equipment, and the photoelectric conversion device comprises an SPAD device, a quenching module, a counting module, a time analog conversion module and a data processing module. When the count value is not greater than the preset value, the data processing module uses the count value to represent the ambient light intensity; and when the count value is greater than the preset value, calculating the average voltage corresponding to the average value of the pulse widths of the electric signals in the whole exposure period according to the accumulated value of the analog voltage, and representing the ambient light intensity by using the average voltage. According to the utility model, the counting module is firstly used for counting the number of photons received by the SPAD device, and when the counting value reaches a set value, the time analog conversion module is switched to represent the ambient light intensity, so that the dynamic range of photon detection is expanded without increasing the power consumption, the photons can be detected when the light intensity is relatively low or relatively high, and the detection efficiency is improved. And the condition of inaccurate counting caused by saturation of the counter due to increase of the light intensity is avoided.

Description

Technical Field

[0001] The utility model relates to the technical field of photoelectric imaging sensors, in particular to a photoelectric conversion device and an electronic device. Background Art

[0002] The SPAD device (Single Photon Avalanche Diode) in the photoelectric imaging sensor usually adopts a passive quenching method, such as Figure 1 As shown, when the SPAD device 201 detects a photon, avalanche multiplication occurs. Since the resistance of the quenching device 202 is much greater than the resistance of the SPAD device 201 during avalanche, the VC point begins to discharge, causing the VC voltage to drop. When the VC voltage is lower than the judgment threshold, the VO voltage begins to rise.

[0003] like Figure 2 and Figure 3 As shown, from time t0 to time t1, a voltage difference "VH-VL" is applied to Figure 1 The SPAD device 201 in the circuit. At time t1, when a photon is incident on the SPAD device 201, avalanche multiplication occurs in the SPAD device 201, so that the avalanche multiplication current flows in the quenching element 202, causing the voltage of VC to drop. If the voltage drop amount increases further, and the voltage difference applied to the SPAD device 201 becomes smaller, the avalanche multiplication of the SPAD device 201 stops at time t2, and the voltage level at the VC point does not drop more than the predetermined value. Then, between time t2 and time t3, current flows from the voltage VL to VC to form a voltage drop, and at time t3, the potential level at the VC point statically stabilizes to the original potential level. At this time, in the case where the output waveform at the VC point exceeds the threshold, the output waveform is shaped by the waveform shaping unit 210 and output to VO as a signal, at which point the VO point is finally output in the form of a pulse voltage (such as Figure 3 If the VO point is connected to a counter, photon counting can be performed, that is, the number of pulse voltages can be recorded.

[0004] like Figure 5 As shown in FIG, under low light intensity, there are only 3 photons. When the SPAD device 201 receives 3 photons, the counter counts three pulses accordingly. Figure 6 As shown in the figure, under high light intensity, although about 20 photons are incident, only 3 pulses are counted, and the count value is small. Although there are continuous photon irradiation, the VC point voltage is continuously lower than the threshold voltage, and VO does not generate a pulse signal. It can be seen that during the high level period of each clock cycle of the clock signal, only the first triggered photon can be responded to, so the count value is less than the actual number of photons. Therefore, Figure 4As shown in the figure, after the light intensity reaches a certain value, the value represented by the count value will decrease instead, and the count value and the light intensity value cannot correspond one to one. In this case, the SPAD device cannot obtain the correct count value, and the count value of the counter is easily saturated, making it impossible to count subsequent photons.

[0005] Currently, in strong light environments, the dynamic range of SPAD is usually increased by increasing the number of bits and clock frequency of the counter. However, this method will significantly increase the power consumption of the photosensor chip, which is not conducive to the development of SPAD image sensors. Utility Model Content

[0006] In view of the above-mentioned deficiencies in the prior art, the purpose of the present invention is to provide a photoelectric conversion device and an electronic device to solve the problem of inaccurate counting values ​​of the existing photoelectric sensors in a strong light environment.

[0007] In order to solve the above technical problems, the present invention adopts the following technical solutions:

[0008] A photoelectric conversion device, comprising a SPAD device, a quenching module, a counting module, a time-to-analog conversion module, and a data processing module;

[0009] The quenching module is used to switch the working state according to the clock signal. When the quenching module is in the conducting state, the SPAD device is charged to the power supply voltage. When the quenching module is in the non-conducting state, the SPAD device waits for receiving photon triggering;

[0010] The SPAD device is used to generate an electrical signal pulse according to the first photon signal received in each clock cycle during the exposure period;

[0011] The counting module is used to count the number of the electrical signal pulses output by the SPAD device to obtain a count value;

[0012] The time analog conversion module is used to convert the pulse width values ​​of the electrical signal pulses in all clock cycles into the cumulative value of the analog voltage;

[0013] The data processing module is used to use the count value to characterize the ambient light intensity when the count value is not greater than the preset value; and is used to calculate the average voltage corresponding to the average value of the pulse width of the electrical signal pulse during the entire exposure period based on the accumulated value of the analog voltage when the count value is greater than the preset value, and use the average voltage to characterize the ambient light intensity.

[0014] In the photoelectric conversion device, the preset value is smaller than the maximum value of the counting module.

[0015] In the photoelectric conversion device, during the high level period of the clock signal, when the SPAD device receives a photon signal, the electrical signal pulse is at a high level;

[0016] The pulse width of the electrical signal pulse is the time length between the first time point when the SPAD device is first triggered by a photon in each clock cycle and the second time point when the clock signal falls.

[0017] In the photoelectric conversion device, the high level of the clock signal accounts for at least 80% of the clock period.

[0018] In the photoelectric conversion device, the time analog conversion module includes a first PMOS transistor, a first NMOS transistor, a second NMOS transistor and a first capacitor, the gate of the first PMOS transistor is connected to an external bias power supply, the source of the first PMOS transistor is connected to a power supply terminal, the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, the gate of the first NMOS transistor is connected to the output terminal of the SPAD device, the source of the first NMOS transistor is connected to one end of the first capacitor, the input terminal of the data processing module and the drain of the second NMOS transistor, the source of the second NMOS transistor and the other end of the first capacitor are grounded, and the gate of the second NMOS transistor is connected to the first external control terminal;

[0019] The external bias power supply controls the first PMOS tube to be continuously turned on, providing charging current for the first capacitor; when exposure starts, when the SPAD device receives a photon, the output of the SPAD device controls the first NMOS tube to be turned on to charge the first capacitor, and the second NMOS tube is disconnected at this time; when exposure ends, the output of the SPAD device controls the first NMOS tube to be turned off, and the second NMOS tube is turned on to release the charge of the first capacitor, waiting for the next exposure.

[0020] In the photoelectric conversion device, calculating the average value of the pulse width of the electrical signal during the entire exposure period based on the accumulated value of the analog voltage specifically includes:

[0021] The change in the voltage of the first capacitor before and after exposure is divided by the number of electrical signal pulses to obtain an average voltage of the analog voltage corresponding to the pulse width of the electrical signal pulses.

[0022] In the photoelectric conversion device, the time analog conversion module includes: a D flip-flop, an inverter, a buffer, a second PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a second capacitor, and a third capacitor. The input end of the D flip-flop is connected to the output end of the SPAD device, the clock pulse input end of the D flip-flop is connected to the trigger clock, the output end of the D flip-flop is connected to the gate of the third NMOS transistor, the input end of the inverter, and the input end of the buffer, the output end of the inverter is connected to the reset end of the D flip-flop, the output end of the buffer is connected to the gate of the fifth NMOS transistor, the gate of the second PMOS transistor is connected to the second external control end, the source of the second PMOS transistor is connected to the power supply end, the drain of the second PMOS transistor is connected to the drain of the third NMOS transistor and one end of the second capacitor, the source of the third NMOS transistor is connected to the drain of the fourth NMOS transistor, the gate of the fourth NMOS transistor is connected to the third external control end, the source of the fourth NMOS transistor is connected to the drain of the fifth NMOS transistor and one end of the third capacitor, and the source of the fifth NMOS transistor, the other end of the second capacitor, and the other end of the third capacitor are all grounded.

[0023] The clock frequency of the trigger clock is n times that of the clock signal. Before exposure begins, the second external control terminal controls the second PMOS transistor to be turned on, and the power supply of the power supply terminal charges the second capacitor.

[0024] After exposure starts, the fourth NMOS tube is turned on, and the second external control terminal controls the second PMOS tube to be turned off. When the electrical signal pulse is at a high level, each time the rising edge of the trigger clock occurs, the D trigger outputs a high-level signal to turn on the third NMOS tube. At this time, the charge of the second capacitor is discharged to the third capacitor through the third NMOS tube and the fourth NMOS tube, and the fifth NMOS tube is turned off. The high-level signal output by the D trigger passes through the inverter as the reset signal of the D trigger. The output of the D trigger is reset to a low-level signal to turn off the third NMOS tube. At this time, the fifth NMOS tube is turned on, and the charge of the third capacitor is discharged to the ground. During exposure, the charge on the second capacitor will be continuously discharged according to the high level of the electrical signal pulse.

[0025] In the photoelectric conversion device, the clock frequency of the trigger clock is 5 times that of the clock signal. When the electrical signal pulse is at a high level, the trigger clock has 1-4 rising edges, causing the third NMOS tube to be turned on 1-4 times.

[0026] In the photoelectric conversion device, the capacitance of the second capacitor is M times that of the third capacitor, and M is greater than the number of the electrical signal pulses during the exposure period.

[0027] In the photoelectric conversion device, calculating the average value of the pulse width of the electrical signal during the entire exposure period based on the accumulated value of the analog voltage specifically includes:

[0028] The change value of the second capacitor voltage before and after exposure is divided by a coefficient to obtain the average value of the pulse width of the electrical signal pulse; the coefficient is related to the number of the electrical signal pulses and the clock frequency of the trigger clock is a multiple of the clock signal.

[0029] The utility model also provides an electronic device, characterized in that it comprises the photoelectric conversion device as described above.

[0030] Compared with the existing technology, the photoelectric conversion device and electronic device provided by the utility model first use a counting module to count the number of photons received by the SPAD device. When the count value reaches the set value, it switches to a time analog conversion module to characterize the ambient light intensity. This achieves the expansion of the dynamic range of photon detection without increasing power consumption, so that photons can be detected when the light intensity is low or high, avoiding the situation where the counter is saturated due to the increase in light intensity, resulting in inaccurate counting. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 This is a circuit diagram of a photoelectric sensor in the prior art.

[0032] Figure 2 Schematic diagram of the voltage waveform at the VC point when the SPAD device in the photoelectric sensor of the prior art avalanches.

[0033] Figure 3 Schematic diagram of the voltage waveform at the VO point when the SPAD device in the photoelectric sensor of the prior art avalanches.

[0034] Figure 4 Schematic diagram of light intensity.

[0035] Figure 5 Schematic diagram of counting photons received by a SPAD device of a conventional photosensor under low light intensity.

[0036] Figure 6 This is a schematic diagram of counting photons received by a SPAD device of a conventional photoelectric sensor under strong light intensity.

[0037] Figure 7 This is a structural block diagram of the photoelectric conversion device provided by the utility model.

[0038] Figure 8 This is a schematic diagram of the waveform correspondence between the clock signal, electrical signal pulse, count value, and pulse width value output by the time analog conversion module in the photoelectric conversion device provided by the present invention.

[0039] Figure 9The photoelectric conversion device provided by the utility model respectively uses a counting module and a time analog conversion module to represent a waveform diagram of light intensity.

[0040] Figure 10 This is a circuit diagram of an embodiment of a time-to-analog conversion module in the photoelectric conversion device provided by the present utility model.

[0041] Figure 11 for Figure 10 Schematic diagram of the voltage waveforms of VO and VC1.

[0042] Figure 12 This is a circuit diagram of another embodiment of the time-to-analog conversion module in the photoelectric conversion device provided by the present invention.

[0043] Figure 13 for Figure 12 Medium VO, V TRG 、V Dis Schematic diagram of the voltage waveform of VC2.

[0044] Description of Reference Numerals

[0045] SPAD device 11, quenching module 12, counting module 13, time-to-analog conversion module 14, data processing module 15, first PMOS transistor Q1, first NMOS transistor Q2, second NMOS transistor Q3, first capacitor C1, D flip-flop U1, inverter INVT, buffer A1, second PMOS transistor Q4, third NMOS transistor Q5, fourth NMOS transistor Q6, fifth NMOS transistor Q7, second capacitor C2, third capacitor C3 DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0047] See also Figure 7The photoelectric conversion device provided by the present invention mainly includes a SPAD device 11, a quenching module 12, a counting module 13, a time analog conversion module 14 and a data processing module 15. The cathode of the SPAD device 11 is connected to the power supply end (such as VDD power supply) through the quenching module 12 and is also connected to an input end of the logic module. The anode of the SPAD device 11 is grounded; the external clock source is connected to the other input end of the logic module and connected to the clock pulse input end STOP of the time analog conversion module 14. The output end of the logic module is connected to the input end of the counting module 13 and the control input end START of the time analog conversion module 14. The output end of the counting module 13 and the output end of the time analog conversion module 14 are connected to the input end of the data processing module 15.

[0048] The quenching module 12 is configured to switch operating states based on a clock signal. When the quenching module 12 is in the conducting state, the SPAD device 11 is charged to the power supply voltage (i.e., the voltage VDD at the power supply terminal). When the quenching module 12 is in the non-conducting state, the SPAD device 11 waits for photon triggering. In one embodiment, the quenching module is a PMOS transistor.

[0049] The SPAD device 11 is used to generate an electrical signal pulse VO according to the photon signal received for the first time in each clock cycle during the exposure period.

[0050] In one embodiment, the logic module is as follows Figure 7 The figure shows an AND gate with inverted inputs. The cathode voltage of the SPAD is denoted as VC, and the clock signal clk_R and VC are input to the AND gate. When a photon strikes the SPAD, the value of VC transitions from high to low. In this case, when the clock signal clk_R is high, the output VO of the logic module goes high. Then, when the clock signal clk_R transitions from high to low, the output VO of the logic module transitions to low, thereby generating the output signal, namely, the electrical signal pulse VO.

[0051] The counting module 13 is used to count the number of the electrical signal pulses VO output by the SPAD device 11 to obtain a count value. The counting module 13 is a counter used in existing SPAD image sensors. It is a prior art and will not be described in detail here.

[0052] The time analog conversion module 14 is used to convert the pulse width Ti (such as Figure 8 and converts the accumulated value Vn of analog voltage into the accumulated value Vn. Figure 8In the photoelectric conversion device of the present invention, the pulse width of the electrical signal pulse VO is represented as a time signal, that is, the duration of the high level of the electrical signal pulse VO in one cycle.

[0053] The data processing module 15 is used to use the count value to represent the ambient light intensity when the count value is not greater than the preset value; and is used to calculate the average value of the pulse width of the electrical signal pulse VO during the entire exposure period based on the accumulated value Vn of the analog voltage when the count value is greater than the preset value, convert the average value of the pulse width into an average voltage Vi, and use the average voltage Vi to represent the ambient light intensity.

[0054] The present invention uses a counting module 13 to first count the number of photons received by the SPAD device 11. When the count value reaches a set value, the method switches to the time analog conversion module 14 to characterize the ambient light intensity. This achieves the expansion of the dynamic range of ambient light intensity detection without increasing power consumption. That is, the photoelectric conversion device can characterize the light intensity value under both weak and strong light conditions. In other words, when the count value is not greater than the preset value (i.e., at low light intensity), the counting module 13 counts. When the count value is greater than the preset value, the time analog conversion module 14 uses the average value of the electrical signal pulses during the entire exposure period to characterize the ambient light intensity. Combining these two methods can achieve a larger dynamic range and low power consumption.

[0055] like Figure 9 As shown, in Figure 9 The medium dynamic range DR1 is represented by the count value (counter) provided by the counting module 13. However, when the light intensity reaches a certain value, the counting module 13 is saturated, i.e., the count is full. The present invention switches to the time analog conversion module 14 before the counting module is saturated. Figure 9 The dynamic range DR2 in the time analog conversion module 14 is characterized by the analog voltage value output. Figure 9 It can be seen that the dynamic range of SPAD detection of photons can be increased by combining the counting module 13 and the time analog conversion module 14. In weak light, the counting value of the counting module is used to represent the light intensity to ensure accuracy, while in strong light, the analog voltage output by the time analog conversion module is used to represent the light intensity to expand the detection range.

[0056] In an optional embodiment, the preset value is less than the maximum value of the counter. For example, the maximum count value of the counting module 13 may be 1024, and the preset value may be 1000. When the count value of the counter reaches 1000, the data processing module calculates the voltage value Vi corresponding to the average value of the pulse width of the electrical signal pulse VO during the entire exposure period based on the accumulated value Vn of the analog voltage of the time-to-analog conversion module 14, and outputs Vi to represent the ambient light intensity. This achieves the expansion of the dynamic range of photon detection without increasing power consumption, that is, the ambient light intensity can be detected when the light intensity is large or small.

[0057] like Figure 8 As shown, in the time analog conversion module 14, within one cycle of the clock signal, when the clock signal is at a high level, when the SPAD device 11 receives the first photon signal, the electrical signal pulse VO output by the time analog conversion module 14 changes from a low level to a high level; the pulse width value Ti of the electrical signal pulse VO is the time length between the first time point when the SPAD device 11 is first triggered by a photon in each clock cycle and the second time point of the falling edge of the clock signal.

[0058] However, using only the electrical signal pulse VO within a single clock cycle to represent light intensity is inaccurate. When an exposure is complete, the pulse widths T1-Tn corresponding to the high-level periods of the electrical signal pulses VO_1-VO_n over the entire clock cycle must be obtained. By averaging these values, we can obtain the average pulse width during the high-level periods of the electrical signal pulses VO. The stronger the light, the larger the average pulse width. The average pulse width reflects the light intensity, so the voltage corresponding to the average pulse width is linearly related to the light intensity. By calculating the voltage corresponding to the average pulse width, we can determine the light intensity.

[0059] In an optional embodiment, the high level of the clock signal provided by the clock source accounts for at least 80% of the clock cycle. For example, within a clock cycle, the high level accounts for 90% and the low level accounts for only 10%. The high level time is made as long as possible to receive more photons and improve the counting accuracy.

[0060] See also Figure 10 and Figure 11 In an optional embodiment of the photoelectric conversion device of the present invention, the time analog conversion module 14 includes a first PMOS transistor Q1, a first NMOS transistor Q2, a second NMOS transistor Q3, and a first capacitor C1. When the gate of the first PMOS transistor Q1 is at a low level, the MOS transistor is turned on. When the gates of the first NMOS transistor Q2 and the second NMOS transistor Q3 are at a high level, the MOS transistors are turned on.

[0061] The gate of the first PMOS transistor Q1 is connected to an external bias power supply Vbias, the source of the first PMOS transistor Q1 is connected to a power supply terminal VDD, the drain of the first PMOS transistor Q1 is connected to the drain of the first NMOS transistor Q2, the gate of the first NMOS transistor Q2 is connected to the output terminal of the SPAD device 11, the source of the first NMOS transistor Q2 is connected to one end of the first capacitor C1, the input terminal of the data processing module 15, and the drain of the second NMOS transistor Q3, the source of the second NMOS transistor Q3 and the other end of the first capacitor C1 are grounded, and the gate of the second NMOS transistor Q3 is connected to a first external control terminal VR. The external bias power supply Vbias and the first external control terminal VR can be provided by a chip or a switch. The provision method is not a protection point of the present invention and is not described in detail here.

[0062] If a photon reaches the SPAD device 11 during the high level period of clk_R, when the SPAD device 11 receives the photon, the first NMOS tube Q2 is turned on and the second NMOS tube Q3 is turned off to charge the first capacitor C1. When the exposure is completed, the second NMOS tube Q3 is turned on and the first NMOS tube Q2 is turned off to release the charge of the first capacitor C1, waiting for the next exposure.

[0063] In this embodiment, the first PMOS transistor Q1 is used to provide a charging current for the first capacitor C1. During the exposure cycle, the first PMOS transistor Q1 is continuously turned on to provide the charging current for the first capacitor C1. The external bias power supply Vbias controls the continuous conduction of the first PMOS transistor and controls the magnitude of the charging current, which is recorded as I. The first NMOS transistor Q2 and the second NMOS transistor Q3 both function as switches. Whether the first NMOS transistor Q2 is turned on is controlled by the high and low level states of the electrical signal pulse VO. When the electrical signal pulse VO is high, the first NMOS transistor Q2 is turned on, and the current I during each turn-on period charges the first capacitor C1. The second NMOS transistor Q3 is turned off during normal SPAD exposure. After the exposure is completed, the second NMOS transistor Q3 is turned on, releasing the charge on the first capacitor C1 and waiting for the next exposure. By charging and discharging the first capacitor C1 multiple times, more photons can be counted.

[0064] Exposure starts. When the SPAD device receives a photon, the output of the SPAD device controls the first NMOS tube Q2 to turn on, thereby charging the first capacitor C1. At this time, the second NMOS tube Q3 is disconnected. When the SPAD device does not receive a photon, the output of the SPAD device controls the first NMOS tube Q2 to turn off. At this time, the second NMOS tube Q3 is turned on to release the charge of the first capacitor C1, waiting for the next exposure.

[0065] In this embodiment, the average value of the pulse width of the electrical signal pulse VO during the entire exposure period is calculated based on the accumulated value Vn of the analog voltage, specifically including: dividing the change in the voltage of the first capacitor C1 before and after exposure by the number of electrical signal pulses VO to obtain the average voltage of the analog voltage corresponding to the pulse width of the electrical signal pulse VO, and using it to characterize the ambient light intensity, wherein the pulse width is linearly related to the analog voltage, and the analog voltage is linearly related to the light intensity.

[0066] However, in this embodiment, the capacitance of the first capacitor C1 needs to be very large, and the charging current needs to be very small to ensure that the amount of charge charged each time is smaller, that is, Q1=C1V=It. In this way, during the entire exposure period, when the electrical signal pulse VO outputs a pulse, the first capacitor C1 can be charged and will not be fully charged too quickly, otherwise the stability of the ambient light intensity measurement will be affected. However, the larger the capacitance of the capacitor, the larger the volume of the capacitor, which makes the capacitor occupy a large space, does not meet the requirements of the miniaturization development of the photoelectric conversion device, and increases the cost.

[0067] from Figure 11 It can be seen that as the number of photons received per clock increases, the voltage of VC1 gradually increases, but the maximum increase of VC1 is VDD. If VDD is 1.1v / 3.3v / 2.5v, in order to prevent VC1 from increasing too quickly, the capacitance value of the first capacitor C1 must be increased. The increase in capacitance value will increase the chip area and increase the cost of the photosensor.

[0068] In another optional embodiment of the photoelectric conversion device of the present invention, please refer to Figure 12 and Figure 13 The time-to-analog conversion module 14 includes: a D flip-flop U1, an inverter INVT, a buffer A1, a second PMOS transistor Q4, a third NMOS transistor Q5, a fourth NMOS transistor Q6, a fifth NMOS transistor Q7, a second capacitor C2, and a third capacitor C3. When the gate of the second PMOS transistor Q4 is at a low level, the transistors are turned on. When the gates of the third NMOS transistor Q5, the fourth NMOS transistor Q6, and the fifth NMOS transistor Q7 are at a high level, the MOS transistors are turned on.

[0069] The input end of the D flip-flop U1 is connected to the output end of the SPAD device 11, the clock pulse input end of the D flip-flop U1 (the clock pulse input end STOP of the time analog conversion module 14) is connected to the trigger clock, the output end of the D flip-flop U1 is connected to the gate of the third NMOS transistor Q5, the input end of the inverter INVT and the input end of the buffer A1, the output end of the inverter INVT is connected to the reset end of the D flip-flop U1, the output end of the buffer A1 is connected to the gate of the fifth NMOS transistor Q7, and the gate of the second PMOS transistor Q4 is connected to the second external control Terminal RSTB1, the source of the second PMOS transistor Q4 is connected to the power supply terminal VDD, the drain of the second PMOS transistor Q4 is connected to the drain of the third NMOS transistor Q5 and one end of the second capacitor C2, the source of the third NMOS transistor Q5 is connected to the drain of the fourth NMOS transistor Q6, the gate of the fourth NMOS transistor Q6 is connected to the third external control terminal Vb, the source of the fourth NMOS transistor Q6 is connected to the drain of the fifth NMOS transistor Q7 and one end of the third capacitor C3, the source of the fifth NMOS transistor Q7, the other end of the second capacitor C2, and the other end of the third capacitor C3 are all grounded. Among them, the second external control terminal RSTB1 and the third external control terminal Vb can be provided by a chip or a switch. The provision method is not a protection point of the present invention and is not described in detail here.

[0070] The trigger clock has a frequency of n times the clock signal. Before exposure begins, the second external control terminal RSTB1 turns on the second PMOS transistor Q4, allowing the power supply terminal VDD to charge the second capacitor C2 in preparation for exposure. After exposure begins, the fourth NMOS transistor Q6 turns on, and the second external control terminal RSTB1 turns off the second PMOS transistor Q4. When the electrical signal pulse is at a high level, each time the trigger clock rises, the trigger outputs a high-level signal, turning on the third NMOS transistor Q5. At this point, the charge on the second capacitor C2 is discharged to the third capacitor C3 via the third and fourth NMOS transistors Q5 and Q6, while the fifth NMOS transistor Q7 turns off. The high-level signal output by the D flip-flop passes through the inverter INVT and serves as the reset signal for the D flip-flop U1, resetting the output of the D flip-flop to a low-level signal and turning off the third MOS transistor Q5. Due to the delay, the fifth NMOS transistor Q7 turns on, discharging the charge on the third capacitor C3 to ground. During exposure, the charge on the second capacitor C2 is continuously discharged according to the high level of the electrical signal pulse.

[0071] In this embodiment, the average value of the pulse width of the electrical signal pulse VO during the entire exposure period is calculated based on the accumulated value Vn of the analog voltage, specifically including: dividing the change value of the voltage of the second capacitor C2 before and after exposure by a coefficient to obtain the average value of the pulse width of the electrical signal pulse VO; the coefficient is related to the number of the electrical signal pulses and the clock frequency of the trigger clock is a multiple of the clock signal.

[0072] In specific implementations, the trigger clock ck2 has a frequency that is n times the clock signal. Using the same clock source, a frequency multiplier, phase-locked loop, or resonator can be used to multiply the clock frequency by n times, thereby serving as the trigger clock ck2. In this embodiment, ck2 serves as the clock for the D-type flip-flop U1. The electrical signal pulse VO serves as the input signal for the D-type flip-flop U1. The output VTRG of the D-type flip-flop U1 serves as the control signal for turning on the third NMOS transistor Q5. Before exposure begins, signal RSTB1 turns on the second PMOS transistor Q4, allowing the VDD power supply to charge the second capacitor C2, and waiting for exposure to begin.

[0073] After the exposure starts, RSTB1 is at a low level to control the second PMOS tube Q4 to be disconnected and stop charging the second capacitor C2. When the electric signal pulse VO is at a high level and each time ck2 rises, the V output by the D trigger U1 is TRG The signal becomes high level to turn on the third NMOS tube Q5, and after passing through the inverter INVT, it serves as the reset signal of the D flip-flop U1. TRG The signal is reset to a low level to disconnect the third NMOS tube Q5; therefore, at V TRG When the signal is at a high level, the third NMOS transistor Q5 is turned on, and when the signal is at a low level, the third NMOS transistor Q5 is turned off.

[0074] During the exposure period, the fourth NMOS transistor Q6 is always in the on state. When the third NMOS transistor Q5 is on, the fifth NMOS transistor Q7 is off, and the charge on the second capacitor C2 is discharged to the third capacitor C3 through the third NMOS transistor Q5 and the fourth NMOS transistor Q6. When the third NMOS transistor Q5 is off, the fifth NMOS transistor Q7 is on, so that the charge on the third capacitor C3 is discharged to the ground through the fifth NMOS transistor Q7.

[0075] During the exposure period, the charge on the second capacitor C2 is continuously discharged according to the pulse of the electrical signal pulse VO, so that the second capacitor C2 and the third capacitor C3 do not need to have a very large capacitance.

[0076] In an optional embodiment, the clock frequency of the trigger clock is 5 times that of the clock signal, that is, n is 5. Within one cycle of the clock signal, when the electrical signal pulse is at a high level, the trigger clock has 1-4 rising edges, causing the third NMOS transistor Q5 to be turned on 1-4 times. Figure 13As shown, in one clock cycle, when the clock signal is at a high level, the trigger clock has four clock rising edges, so that the third NMOS transistor Q5 and the fifth NMOS transistor Q7 can be turned on three times.

[0077] Furthermore, the capacitance of the second capacitor C2 is M times that of the third capacitor C3, where M is greater than the number of the electrical signal pulses VO during the exposure period.

[0078] In another optional embodiment of the present invention, Figure 12 , the voltage VC2 on the second capacitor C2 indirectly reflects the cumulative value of the pulse width of the electrical signal pulse VO; within one cycle of the clock signal, the electrical signal pulse VO is at a high level, ck2 has 1-4 rising edges, so the third NMOS tube Q5 is turned on 1-4 times, and the second capacitor C2 will discharge 1-4 times of charge, but the time of each discharge is very short, so during the exposure period, the second capacitor C2 can always discharge the charge according to the high pulse of the electrical signal pulse VO, but it will not be discharged quickly. The charge discharged each time is determined by the third capacitor C3 and the voltage on the third capacitor C3, achieving a more precise control of the voltage VC2 drop, and the voltage VC2 gradually decreases. During the exposure period, there is always voltage on the second capacitor C2 and it does not drop to 0 quickly, so that a more accurate ambient light intensity can be obtained during the exposure period.

[0079] according to Figure 12 and Figure 13 The charge Q2 on the second capacitor C2 is equal to C2*VDD, and the voltage V3 on the third capacitor C3 is equal to Vb-Vgs(Q6). Therefore, the charge Q3 charged each time by the third capacitor C3 is equal to C3*V3. Therefore, each time the third NMOS transistor Q5 is turned on, the charge discharged from the third NMOS transistor Q5 is determined by the third capacitor C3, that is, Q2 / Q3=K*C2 / C3=the number of Vtrg pulses=M. The value of M indicates how many times the VTRG pulse signal can be discharged from the second capacitor C2. Therefore, this embodiment focuses on the value of M and no longer pays attention to the absolute value of the second capacitor C2, thereby reducing the area of ​​the second capacitor C2.

[0080] The present invention further provides an electronic device, which includes the above-mentioned photoelectric conversion device. The electronic device may be a scanner. Since the photoelectric conversion device has been described in detail above, it will not be described again here.

[0081] To sum up, the utility model adopts a method of first using a counting module to count the number of photons received by the SPAD device, and when the count value reaches the set value, switching to a time analog conversion module to characterize the ambient light intensity, thereby expanding the dynamic range of photon detection without increasing power consumption, so that photons can be detected when the light intensity is low or high, avoiding the situation where the counter is saturated due to the increase in light intensity and thus inaccurate counting.

[0082] At the same time, the utility model does not need to increase the number of bits and clock frequency of the counter, which can make the photoelectric conversion device small in size, low in power consumption, and low in product cost. When the light intensity is low, a counting module is used for counting. When the counting module is close to saturation, a time analog conversion module is used to characterize the ambient light intensity, thereby ensuring the working efficiency of the photoelectric conversion device and enabling it to maintain good performance under different lighting conditions.

[0083] It is understandable that those skilled in the art can make equivalent substitutions or changes based on the technical solution and utility model concept of the present invention, and all these changes or substitutions should fall within the scope of protection of the claims attached to the present invention.

Claims

1. A photoelectric conversion device, characterized in that: It includes SPAD device, quenching module, counting module, time analog conversion module and data processing module; The quenching module is used to switch the working state according to the clock signal. When the quenching module is in the conducting state, the SPAD device is charged to the power supply voltage. When the quenching module is in the non-conducting state, the SPAD device waits for receiving photon triggering; The SPAD device is used to generate an electrical signal pulse according to the first photon signal received in each clock cycle during the exposure period; The counting module is used to count the number of the electrical signal pulses output by the SPAD device to obtain a count value; The time analog conversion module is used to convert the pulse width values ​​of the electrical signal pulses in all clock cycles into the cumulative value of the analog voltage; The data processing module is configured to use the count value to represent the ambient light intensity when the count value is not greater than a preset value; And when the count value is greater than a preset value, the average voltage corresponding to the average value of the pulse width of the electrical signal pulse during the entire exposure period is calculated according to the accumulated value of the analog voltage, and the average voltage is used to represent the ambient light intensity.

2. The photoelectric conversion device according to claim 1, wherein: The preset value is smaller than the maximum value of the counting module.

3. The photoelectric conversion device according to claim 1, wherein: During the high level period of the clock signal, when the SPAD device receives a photon signal, the electrical signal pulse is at a high level; The pulse width of the electrical signal pulse is the time length between the first time point when the SPAD device is first triggered by a photon in each clock cycle and the second time point of the falling edge of the clock signal.

4. The photoelectric conversion device according to claim 1, wherein: The high level of the clock signal accounts for at least 80% of the clock period.

5. The photoelectric conversion device according to claim 1, wherein: The time analog conversion module includes a first PMOS transistor, a first NMOS transistor, a second NMOS transistor and a first capacitor, the gate of the first PMOS transistor is connected to an external bias power supply, the source of the first PMOS transistor is connected to a power supply terminal, the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, the gate of the first NMOS transistor is connected to the output terminal of the SPAD device, the source of the first NMOS transistor is connected to one end of the first capacitor, the input terminal of the data processing module and the drain of the second NMOS transistor, the source of the second NMOS transistor and the other end of the first capacitor are grounded, and the gate of the second NMOS transistor is connected to the first external control terminal; The external bias power supply controls the first PMOS tube to be continuously turned on, providing charging current for the first capacitor; when exposure starts, when the SPAD device receives a photon, the output of the SPAD device controls the first NMOS tube to be turned on to charge the first capacitor, and the second NMOS tube is disconnected at this time; when exposure ends, the output of the SPAD device controls the first NMOS tube to be turned off, and the second NMOS tube is turned on to release the charge of the first capacitor, waiting for the next exposure.

6. The photoelectric conversion device according to claim 5, wherein: Calculating an average voltage corresponding to an average value of the pulse width of the electrical signal pulses during the entire exposure period according to the accumulated value of the analog voltage, specifically comprising: The change in the voltage of the first capacitor before and after exposure is divided by the number of electrical signal pulses to obtain an average voltage corresponding to the average value of the pulse width of the electrical signal pulses.

7. The photoelectric conversion device according to claim 1, wherein: The time-to-analog conversion module includes: a D flip-flop, an inverter, a buffer, a second PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a second capacitor, and a third capacitor. The input end of the D flip-flop is connected to the output end of the SPAD device, the clock pulse input end of the D flip-flop is connected to the trigger clock, the output end of the D flip-flop is connected to the gate of the third NMOS transistor, the input end of the inverter, and the input end of the buffer, the output end of the inverter is connected to the reset end of the D flip-flop, the output end of the buffer is connected to the gate of the fifth NMOS transistor, the gate of the second PMOS transistor is connected to the second external control end, the source of the second PMOS transistor is connected to the power supply end, the drain of the second PMOS transistor is connected to the drain of the third NMOS transistor and one end of the second capacitor, the source of the third NMOS transistor is connected to the drain of the fourth NMOS transistor, the gate of the fourth NMOS transistor is connected to the third external control end, the source of the fourth NMOS transistor is connected to the drain of the fifth NMOS transistor and one end of the third capacitor, and the source of the fifth NMOS transistor, the other end of the second capacitor, and the other end of the third capacitor are all grounded. The clock frequency of the trigger clock is n times that of the clock signal. Before exposure begins, the second external control terminal controls the second PMOS transistor to be turned on, and the power supply of the power supply terminal charges the second capacitor. After exposure starts, the fourth NMOS tube is turned on, and the second external control terminal controls the second PMOS tube to be turned off. When the electrical signal pulse is at a high level, each time the rising edge of the trigger clock occurs, the D trigger outputs a high-level signal to turn on the third NMOS tube. At this time, the charge of the second capacitor is discharged to the third capacitor through the third NMOS tube and the fourth NMOS tube, and the fifth NMOS tube is turned off. The high-level signal output by the D trigger passes through the inverter as the reset signal of the D trigger. The output of the D trigger is reset to a low-level signal to turn off the third NMOS tube. At this time, the fifth NMOS tube is turned on, and the charge of the third capacitor is discharged to the ground. During exposure, the charge on the second capacitor will be continuously discharged according to the high level of the electrical signal pulse.

8. The photoelectric conversion device according to claim 7, wherein: The clock frequency of the trigger clock is 5 times that of the clock signal. Within one cycle of the clock signal, when the electrical signal pulse is at a high level, the trigger clock has 1-4 rising edges, causing the third NMOS tube to be turned on 1-4 times.

9. The photoelectric conversion device according to claim 7, wherein: The capacitance of the second capacitor is M times that of the third capacitor, and M is greater than the number of the electrical signal pulses during the exposure period.

10. The photoelectric conversion device according to claim 7, wherein: Calculating the average value of the pulse width of the electrical signal during the entire exposure period according to the accumulated value of the analog voltage, specifically including: The change in the second capacitor voltage before and after exposure is divided by a coefficient to obtain an average value of the pulse width of the electrical signal pulse; the coefficient is related to the number of the electrical signal pulses and whether the clock frequency of the trigger clock is a multiple of the clock signal.

11. An electronic device, characterized in that: The device comprises the photoelectric conversion device according to any one of claims 1 to 10.

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