Dual-output pulse width modulation shifter circuit

Abstract

The utility model discloses a dual-output pulse width modulation shifter circuit, which comprises a metal shell and a circuit board, and is characterized in that the circuit board is mounted in the metal shell and comprises a power supply module, a Hall module, an output protection module, a shielding network module and an output interface module, the Hall module, the output protection module and the output interface module are all connected with the power supply module, and the metal shell is connected with the shielding network module. According to the utility model, the two completely independent induction circuits are arranged in the Hall module, namely the Hall chip, and respectively output two paths of independent output signals, so that the two paths of signals do not interfere with each other, and the output PWM signals are more stable.

Description

Technical Field

[0001] The utility model relates to a dual-output pulse width modulation shifter circuit. Background Art

[0002] Currently available joysticks on the market serve as sensors for controlling the operation of mechanical mechanisms. They primarily consist of a handle and a measuring device for detecting the handle's state. The handle can perform single-axis or multi-axis motion. The measuring device detects the handle's position and sends a position signal to the outside through an electrical interface. As part of the joystick, the shifter plays a very important role. Existing joystick shifters output signals in various forms, including analog, digital, and switch signals. Some joystick shifters only have a single output signal, which may not meet the needs of certain specific systems. In demanding applications, certain functions may be limited and unavailable. Furthermore, the joystick shifter uses PWM signal output. Traditional analog signal output has a short transmission distance and is easily affected by noise. Digital signals may not be as complex and confidential as analog signals. Switch signals may result in information loss and low accuracy in situations requiring precise measurement and control. Utility Model Content

[0003] The purpose of the present invention is to solve the problems raised in the above background technology and to provide a circuit for outputting dual-path PWM waves. The present invention is not easily affected by noise, thereby achieving precise control of the output signal.

[0004] In order to achieve the above object, the present invention is implemented through the following technical solutions:

[0005] A dual-output pulse width modulation shifter circuit includes a metal housing and a circuit board. The circuit board is installed in the metal housing and includes a power module, a Hall module, an output protection module, a shielded network module, and an output interface module. The Hall module, the output protection module, and the output interface module are all connected to the power module, and the metal housing is connected to the shielded network module.

[0006] Preferably, the power module includes a first power circuit, a second power circuit, and an input power supply, wherein the first power circuit and the second power circuit are both connected to the input power supply, which can be a 9-40V DC power supply.

[0007] Preferably, the first power supply circuit includes a transient voltage suppressor diode T1, a diode D1, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C7, a resistor R1, a resistor R2, a magnetic bead FB1, a magnetic bead FB2, and a linear regulator U1. The input power supply is connected to the first ground signal GND-0 through the transient voltage suppressor diode T1, the capacitor C1 is connected in parallel with the transient voltage suppressor diode T1, the input power supply is connected to the positive electrode of the diode D1, and the negative electrode of the diode D1 is connected to the input terminal IN of the linear regulator U1 through the magnetic bead FB1. The input terminal I of the linear regulator U1 N is connected to the first analog ground AGND1 through capacitor C2, the first ground signal GND-0 is connected to the first analog ground AGND1 through magnetic bead FB2, the capacitors C3, C4, and C5 are all connected in parallel with capacitor C2, the output voltage adjustable terminal ADJ of the linear regulator U1 is connected to the first analog ground AGND1 through resistor R2, the output terminal OUT of the linear regulator U1 is connected to the output voltage adjustable terminal ADJ of the linear regulator U1 through resistor R1, the TAB terminal TAB of the linear regulator U1 is connected to the output terminal OUT of the linear regulator U1, and the output terminal OUT of the linear regulator U1 outputs VCC.

[0008] Preferably, the second power supply circuit includes a transient voltage suppressor diode T2, a diode D2, a capacitor C8, a capacitor C9, a capacitor C10, a capacitor C11, a capacitor C12, a capacitor C13, a capacitor C14, a resistor R3, a resistor R4, a magnetic bead FB3, a magnetic bead FB4, and a linear regulator U2. The input power supply is connected to the second ground signal GND-2 through the transient voltage suppressor diode T2, the capacitor C8 is connected in parallel with the transient voltage suppressor diode T2, the input power supply is connected to the positive electrode of the diode D2, and the negative electrode of the diode D2 is connected to the input terminal IN of the linear regulator U2 through the magnetic bead FB3. The input terminal IN of the linear regulator U2 is connected to the second analog ground AGND2 through the capacitor C9, the second ground signal GND-2 is connected to the second analog ground AGND2 through the magnetic bead FB4, the capacitors C10, C11, and C12 are all connected in parallel with the capacitor C9, the output voltage adjustable terminal ADJ of the linear regulator U2 is connected to the second analog ground AGND2 through the resistor R4, the output terminal OUT of the linear regulator U2 is connected to the output voltage adjustable terminal ADJ of the linear regulator U2 through the resistor R3, and the TAB terminal TAB of the linear regulator U2 is connected to the output terminal OUT of the linear regulator U2.

[0009] The output terminal OUT of the linear regulator U2 outputs VDD.

[0010] Preferably, the Hall module includes a Hall chip U3, a capacitor C15, a capacitor C16, a capacitor C17, a capacitor C18, a capacitor C19, a capacitor C20, a capacitor C21, and a capacitor C22. The first power input terminal VSUP1 of the Hall chip U3 is connected to VCC, the second power input terminal VSUP2 of the Hall chip U3 is connected to VDD, the first power input terminal VSUP1 of the Hall chip U3 is connected to the first analog ground AGND1 through the capacitor C15, the second power input terminal VSUP2 of the Hall chip U3 is connected to the second analog ground AGND2 through the capacitor C16, the first ground terminal GND1 of the Hall chip U3 is connected to the first analog ground AGND1, and the second ground terminal GND 2 is connected to the second analog ground AGND2, the first ground terminal GND1 of the Hall chip U3 is connected to the fourth test terminal TEST4 of the Hall chip U3, the second ground terminal GND2 of the Hall chip U3 is connected to the eighth test terminal TEST8 of the Hall chip U3, the first output terminal OUT1 of the Hall chip U3 is connected to the first analog ground AGND1 through the capacitor C19, the capacitor C17 and the capacitor C18 are both connected in parallel with the capacitor C19, the third output terminal OUT3 of the Hall chip U3 is connected to the second analog ground AGND2 through the capacitor C20, the capacitor C21 and the capacitor C22 are both connected in parallel with the capacitor C20, and the first output terminal OUT1 and the third output terminal OUT3 of the Hall chip U3 are both connected to the output protection module.

[0011] Preferably, the output protection module includes a first output protection circuit and a second output protection circuit. The first output terminal OUT1 of the Hall chip U3 is connected to the first output protection circuit, and the third output terminal OUT3 of the Hall chip U3 is connected to the second output protection circuit.

[0012] Preferably, the first output protection circuit includes a resistor R5, a resistor R6, a diode D31, and a diode D32, one end of the resistor R5 is connected to the first output terminal OUT1 of the Hall chip U3, the other end of the resistor R5 is connected to one end of the resistor R6, the other end of the resistor R6 outputs the first PWM wave, the other end of the resistor R5 is connected to VCC through the diode D31, and the VCC is connected to the cathode of the diode D1 through the diode D32.

[0013] Preferably, the second output protection circuit includes a resistor R7, a resistor R8, a diode D41, and a diode D42, one end of the resistor R7 is connected to the third output terminal OUT3 of the Hall chip U3, the other end of the resistor R7 is connected to one end of the resistor R8, and the other end of the resistor R8 outputs a second PWM wave. The other end of the resistor R7 is connected to VDD through the diode D41, and the VDD is connected to the cathode of the diode D2 through the diode D42.

[0014] Preferably, the output interface module includes a first output interface circuit and a second output interface circuit. The first output interface circuit includes an output connector J1, a resistor R11, and a transient voltage suppressor diode T3. The input power supply, the first ground signal GND-0, and the first PWM wave are all connected to the output connector J1. The output connector J1 is connected to VCC through the resistor R11.

[0015] The second output interface circuit includes an output connector J2, a resistor R12, and a transient voltage suppressor diode T4. The input power supply, the second ground signal GND-2, and the second PWM wave are all connected to the output connector J2. The output connector J2 is connected to VDD through the resistor R12.

[0016] Preferably, the shielded network module includes a first shielding circuit and a second shielding circuit. The first shielding circuit includes a resistor R9 and a capacitor C23. One end of the resistor R9 is connected to the metal casing, one end of the resistor R9 is connected to the first power ground PGND1, and the other end of the resistor R9 is connected to the first analog ground AGND1. The capacitor C23 is connected in parallel with the resistor R9. The second shielding circuit includes a resistor R10 and a capacitor C24. One end of the resistor R10 is connected to the metal casing, one end of the resistor R10 is connected to the second power ground PGND2, and the other end of the resistor R10 is connected to the second analog ground AGND2. The capacitor C24 is connected in parallel with the resistor R10.

[0017] The beneficial effects of the utility model are as follows:

[0018] 1. Both power input interfaces are protected with TVS tubes and reverse polarity protection diodes. The main function of the TVS tube is to suppress surges and prevent surge damage to the circuit. The main function of the reverse polarity protection diode is to protect the circuit from damage by reverse current and prevent reverse polarity of the power supply.

[0019] 2. The redundant design of the power module ensures that the power supplies of the two signals are independent and do not interfere with each other, thus improving the power supply stability and circuit anti-interference ability;

[0020] 3. The Hall module, i.e. the Hall chip, has two completely independent sensing circuits built in, which output two independent output signals respectively, so that the two signals do not interfere with each other;

[0021] 4. The input power at the input interface in the power circuit adopts a wide voltage range input, which can better meet the power input requirements in different application scenarios;

[0022] 5. Output protection circuits are installed for both Hall output signals. The main function is to absorb spike pulses caused by unstable power supply circuit voltage, thereby making the output PWM signal more stable.

[0023] 6. In the shielded network circuit part, an RC resistor-capacitor circuit is added between the metal shell and the circuit board ground, which can effectively prevent ESD static discharge from damaging the circuit board and effectively reduce the impact of electromagnetic interference on the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is a schematic diagram of the circuit structure of a dual-output pulse width modulation shifter circuit according to an embodiment of the present invention;

[0025] Figure 2 This is a connection diagram of a shielded network module and a metal housing according to an embodiment of the present invention;

[0026] Figure 3 This is a circuit diagram of a first power supply circuit according to an embodiment of the present invention;

[0027] Figure 4 This is a circuit diagram of a second power supply circuit according to an embodiment of the present invention;

[0028] Figure 5 This is a circuit diagram of a Hall module according to an embodiment of the present invention;

[0029] Figure 6 This is a circuit schematic diagram of a first output protection circuit according to an embodiment of the present invention;

[0030] Figure 7 This is a circuit schematic diagram of a second output protection circuit according to an embodiment of the present invention;

[0031] Figure 8 This is a circuit schematic diagram of a first output interface circuit according to an embodiment of the present invention;

[0032] Figure 9 This is a circuit schematic diagram of a second output interface circuit according to an embodiment of the present invention;

[0033] Figure 10 This is a circuit schematic diagram of a first shielding circuit according to an embodiment of the present invention;

[0034] Figure 11 This is a circuit schematic diagram of a second shielding circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0035] The technical solution of the present invention will be further described below in conjunction with the accompanying drawings:

[0036] like Figure 1 、 Figure 2As shown, a dual-output pulse width modulation shifter circuit includes a metal shell 6 and a circuit board. The circuit board is installed in the metal shell 6. The circuit board includes a power module 1, a Hall module 2, an output protection module 3, a shielded network module 4, and an output interface module 5. The Hall module 2, the output protection module 3, and the output interface module 5 are all connected to the power module 1, and the metal shell 6 is connected to the shielded network module 4.

[0037] like Figure 1 As shown, the power module 1 includes a first power circuit 11, a second power circuit 12, and an input power supply 14. The first power circuit 11 and the second power circuit 12 are both connected to the input power supply 14. The input power supply is labeled VSUP in the circuit diagram. The input power supply can input a 9-40V DC power supply.

[0038] like Figure 3 As shown, the first power supply circuit 11 includes a transient voltage suppressor diode T1, a diode D1, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C7, a resistor R1, a resistor R2, a magnetic bead FB1, a magnetic bead FB2, and a linear regulator U1. The input power supply 14 is connected to the first ground signal GND-0 through the transient voltage suppressor diode T1. The capacitor C1 is connected in parallel with the transient voltage suppressor diode T1. The input power supply 14 is connected to the anode of the diode D1. The cathode of the diode D1 is connected to the input terminal IN of the linear regulator U1 through the magnetic bead FB1. The input terminal of the linear regulator U1 IN is connected to the first analog ground AGND1 via capacitor C2. The first ground signal GND-0 is connected to the first analog ground AGND1 via ferrite bead FB2. Capacitors C3, C4, and C5 are all connected in parallel with capacitor C2. The adjustable output voltage terminal ADJ of the linear regulator U1 is connected to the first analog ground AGND1 via resistor R2. The output terminal OUT of the linear regulator U1 is connected to the adjustable output voltage terminal ADJ of the linear regulator U1 via resistor R1. The TAB terminal TAB of the linear regulator U1 is connected to the output terminal OUT of the linear regulator U1. The output terminal OUT of the linear regulator U1 outputs VCC. VCC is a 5V DC power supply.

[0039] like Figure 4As shown, the second power supply circuit 12 includes a transient voltage suppressor diode T2, a diode D2, a capacitor C8, a capacitor C9, a capacitor C10, a capacitor C11, a capacitor C12, a capacitor C13, a capacitor C14, a resistor R3, a resistor R4, a magnetic bead FB3, a magnetic bead FB4, and a linear regulator U2. The input power supply 14 is connected to the second ground signal GND-2 through the transient voltage suppressor diode T2. The capacitor C8 is connected in parallel with the transient voltage suppressor diode T2. The input power supply 14 is connected to the anode of the diode D2. The cathode of the diode D2 is connected to the input terminal IN of the linear regulator U2 through the magnetic bead FB3. The input of the linear regulator U2 Terminal IN is connected to the second analog ground AGND2 via capacitor C9. The second ground signal GND-2 is connected to the second analog ground AGND2 via ferrite bead FB4. Capacitors C10, C11, and C12 are all connected in parallel with capacitor C9. The adjustable output voltage terminal ADJ of the linear regulator U2 is connected to the second analog ground AGND2 via resistor R4. The output terminal OUT of the linear regulator U2 is connected to the adjustable output voltage terminal ADJ of the linear regulator U2 via resistor R3. The TAB terminal TAB of the linear regulator U2 is connected to the output terminal OUT of the linear regulator U2. The output terminal OUT of the linear regulator U2 outputs VDD. VDD is a 5V DC power supply.

[0040] like Figure 5 As shown, the Hall module 2 includes a Hall chip U3, a capacitor C15, a capacitor C16, a capacitor C17, a capacitor C18, a capacitor C19, a capacitor C20, a capacitor C21, and a capacitor C22. The first power input terminal VSUP1 of the Hall chip U3 is connected to VCC, the second power input terminal VSUP2 of the Hall chip U3 is connected to VDD, the first power input terminal VSUP1 of the Hall chip U3 is connected to the first analog ground AGND1 through the capacitor C15, the second power input terminal VSUP2 of the Hall chip U3 is connected to the second analog ground AGND2 through the capacitor C16, the first ground terminal GND1 of the Hall chip U3 is connected to the first analog ground AGND1, and the second ground terminal GND2 of the Hall chip U3 is connected to the first analog ground AGND1. Connected to the second analog ground AGND2, the first ground terminal GND1 of the Hall chip U3 is connected to the fourth test terminal TEST4 of the Hall chip U3, the second ground terminal GND2 of the Hall chip U3 is connected to the eighth test terminal TEST8 of the Hall chip U3, the first output terminal OUT1 of the Hall chip U3 is connected to the first analog ground AGND1 through the capacitor C19, the capacitor C17 and the capacitor C18 are both connected in parallel with the capacitor C19, the third output terminal OUT3 of the Hall chip U3 is connected to the second analog ground AGND2 through the capacitor C20, the capacitor C21 and the capacitor C22 are both connected in parallel with the capacitor C20, and the first output terminal OUT1 and the third output terminal OUT3 of the Hall chip U3 are both connected to the output protection module 3.

[0041] like Figure 1 、 Figure 5 As shown, the output protection module 3 includes a first output protection circuit 131 and a second output protection circuit 132 . The first output terminal OUT1 of the Hall chip U3 is connected to the first output protection circuit 131 , and the third output terminal OUT3 of the Hall chip U3 is connected to the second output protection circuit 132 .

[0042] like Figure 6 As shown, the first output protection circuit 131 includes a resistor R5, a resistor R6, a diode D31, and a diode D32. One end of the resistor R5 is connected to the first output end OUT1 of the Hall chip U3, and the other end of the resistor R5 is connected to one end of the resistor R6. The other end of the resistor R6 outputs the first PWM wave. The other end of the resistor R5 is connected to VCC through the diode D31, and the VCC is connected to the cathode of the diode D1 through the diode D32.

[0043] like Figure 7 As shown, the second output protection circuit 132 includes a resistor R7, a resistor R8, a diode D41, and a diode D42. One end of the resistor R7 is connected to the third output terminal OUT3 of the Hall chip U3, and the other end of the resistor R7 is connected to one end of the resistor R8. The other end of the resistor R8 outputs a second PWM wave. The other end of the resistor R7 is connected to VDD through the diode D41, and the VDD is connected to the cathode of the diode D2 through the diode D42.

[0044] like Figure 8 、 Figure 9 As shown, the output interface module 5 includes a first output interface circuit 51 and a second output interface circuit. The first output interface circuit 51 includes an output connector J1, a resistor R11, and a transient voltage suppressor diode T3. The input power supply 14, the first ground signal GND-0, and the first PWM wave are all connected to the output connector J1. The output connector J1 is connected to VCC through the resistor R11.

[0045] The second output interface circuit 52 includes an output connector J2, a resistor R12, and a transient voltage suppressor diode T4. The input power supply 14, the second ground signal GND-2, and the second PWM wave are all connected to the output connector J2, and the output connector J2 is connected to VDD through the resistor R12.

[0046] like Figure 10 、 Figure 11As shown, the shielded network module 4 includes a first shielding circuit and a second shielding circuit. The first shielding circuit includes a resistor R9 and a capacitor C23. One end of the resistor R9 is connected to the metal shell 6, one end of the resistor R9 is connected to the first power ground PGND1, and the other end of the resistor R9 is connected to the first analog ground AGND1. The capacitor C23 is connected in parallel with the resistor R9. The second shielding circuit includes a resistor R10 and a capacitor C24. One end of the resistor R10 is connected to the metal shell 6, one end of the resistor R10 is connected to the second power ground PGND2, and the other end of the resistor R10 is connected to the second analog ground AGND2. The capacitor C24 is connected in parallel with the resistor R10.

[0047] This patent proposes a dual-output pulse width modulation shifter circuit, which outputs two PWM signals respectively. The shifter can be positioned in three directions: front, middle and rear. Since the magnet moves when shifting, a Hall chip sensor is installed at the relative position of the circuit board to sense the changes of the magnets in different positions, thereby outputting different duty cycle signals to reflect the three directions of the shifter: front, middle and rear.

[0048] The main working principle of the dual-output pulse width modulation shifter circuit is: when the shifter moves forward or backward, the magnet moves with it. A Hall chip sensor is installed at the relative position of the circuit board. The Hall chip senses the changes in the magnets at different positions. The sensed signal is a PWM signal. The output signal is protected by the output protection circuit, and the spike pulses caused by the unstable voltage of the absorption power supply circuit are filtered out, making the output PWM signal more stable. Finally, it is transmitted to the external device through the output interface module.

[0049] Depend on Figure 3 、 Figure 4 As shown in the figure, the power supply circuit, wherein T1 at the power input interface is a TVS tube, which prevents electrostatic surge from damaging the subsequent circuit. D1 is an anti-reverse polarity diode, which prevents reverse polarity of the power supply and protects the circuit from damage by reverse current. C1 and C8 are input filter capacitors. FB1, FB2, FB3, and FB4 are ferrite beads, which are mainly used to suppress high-frequency noise and spike interference on the power line. C2, C3, C4, C9, C10, and C11 are filter capacitors, which make the input power supply voltage more stable. U1 and U2 are linear regulators LDO, wherein C5 and C12 are U1 and U2 input power filter capacitors respectively. C6 and C7 are U1 output filter capacitors. C13 and C14 are U2 output filter capacitors, which make the output voltage of U1 and U2 more stable. The output voltage of U1 and U2 is adjusted by the resistor divider R1, R2, R3, and R4.

[0050] Depend on Figure 5As shown in the figure, in the Hall module, U3 is the Hall chip, C15 and C16 are the filter capacitors of the two input power supply voltages of the Hall chip, which make the chip input voltage more stable, C17, C18, and C19 are the filter capacitors at the output end of HALL-OUT1, which make the output signal more stable, and C20, C21, and C22 are the filter capacitors at the output end of HALL-OUT2, which make the output signal more stable.

[0051] Depend on Figure 6 、 Figure 7 As shown in FIG. 1 , the output protection circuit, wherein D31, D32, D41, and D42 are switching diodes respectively, is mainly used to absorb spike pulses generated by the output signal caused by unstable power supply circuit voltage, thereby making the output PWM signal more stable.

[0052] Depend on Figure 10 、 Figure 11 As shown, the shielded network circuit isolates the metal housing from the circuit board ground through the RC resistor-capacitor circuit, which can effectively prevent ESD (electrostatic discharge) from damaging the circuit board and effectively reduce the impact of electromagnetic interference on the circuit.

[0053] Depend on Figure 8 、 Figure 9 As shown in the figure, the output interface circuit has protection circuits on both output interfaces. T3 and T4 are TVS tubes, which effectively protect the precision components in the circuit from damage by surge pulses and reduce the instability of the output signal.

[0054] It should be noted that the above is only one specific embodiment of the present invention. Obviously, the present invention is not limited to the above embodiment and may be subject to many variations. In short, all variations that can be directly derived or associated with the content of the present invention by a person skilled in the art should be considered to be within the scope of protection of the present invention.

Claims

1. A dual-output pulse width modulation shifter circuit, comprising a metal housing (6), characterized in that: The invention also includes a circuit board, which is installed in a metal shell (6). The circuit board includes a power module (1), a Hall module (2), an output protection module (3), a shielded network module (4), and an output interface module (5). The Hall module (2), the output protection module (3), and the output interface module (5) are all connected to the power module (1), and the metal shell (6) is connected to the shielded network module (4).

2. A dual-output pulse width modulation shifter circuit according to claim 1, characterized in that: The power module (1) comprises a first power circuit (11), a second power circuit (12) and an input power supply (14); the first power circuit (11) and the second power circuit (12) are both connected to the input power supply (14).

3. The dual-output pulse width modulation shifter circuit according to claim 2, characterized in that: The first power supply circuit (11) includes a transient voltage suppression diode T1, a diode D1, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C7, a resistor R1, a resistor R2, a magnetic bead FB1, a magnetic bead FB2, and a linear regulator U1. The input power supply (14) is connected to a first ground signal GND-0 through the transient voltage suppression diode T1. The capacitor C1 is connected in parallel with the transient voltage suppression diode T1. The input power supply (14) is connected to the positive electrode of the diode D1. The negative electrode of the diode D1 is connected to the input terminal IN of the linear regulator U1 through the magnetic bead FB1. The linear regulator U1 The input terminal IN is connected to the first analog ground AGND1 through the capacitor C2, the first ground signal GND-0 is connected to the first analog ground AGND1 through the magnetic bead FB2, the capacitor C3, the capacitor C4, and the capacitor C5 are all connected in parallel with the capacitor C2, the output voltage adjustable terminal ADJ of the linear regulator U1 is connected to the first analog ground AGND1 through the resistor R2, the output terminal OUT of the linear regulator U1 is connected to the output voltage adjustable terminal ADJ of the linear regulator U1 through the resistor R1, the TAB terminal TAB of the linear regulator U1 is connected to the output terminal OUT of the linear regulator U1, and the output terminal OUT of the linear regulator U1 outputs VCC.

4. A dual-output pulse width modulation shifter circuit according to claim 3, characterized in that: The second power supply circuit (12) includes a transient voltage suppression diode T2, a diode D2, a capacitor C8, a capacitor C9, a capacitor C10, a capacitor C11, a capacitor C12, a capacitor C13, a capacitor C14, a resistor R3, a resistor R4, a magnetic bead FB3, a magnetic bead FB4, and a linear regulator U2. The input power supply (14) is connected to the second ground signal GND-2 through the transient voltage suppression diode T2. The capacitor C8 is connected in parallel with the transient voltage suppression diode T2. The input power supply (14) is connected to the positive electrode of the diode D2. The negative electrode of the diode D2 is connected to the input terminal IN of the linear regulator U2 through the magnetic bead FB3. The linear regulator U2 The input terminal IN is connected to the second analog ground AGND2 through the capacitor C9, the second ground signal GND-2 is connected to the second analog ground AGND2 through the magnetic bead FB4, the capacitor C10, the capacitor C11, and the capacitor C12 are all connected in parallel with the capacitor C9, the output voltage adjustable terminal ADJ of the linear regulator U2 is connected to the second analog ground AGND2 through the resistor R4, the output terminal OUT of the linear regulator U2 is connected to the output voltage adjustable terminal ADJ of the linear regulator U2 through the resistor R3, the TAB terminal TAB of the linear regulator U2 is connected to the output terminal OUT of the linear regulator U2, and the output terminal OUT of the linear regulator U2 outputs VDD.

5. The dual-output pulse width modulation shifter circuit according to claim 4, characterized in that: The Hall module (2) comprises a Hall chip U3, a capacitor C15, a capacitor C16, a capacitor C17, a capacitor C18, a capacitor C19, a capacitor C20, a capacitor C21, and a capacitor C22; a first power input terminal VSUP1 of the Hall chip U3 is connected to VCC; a second power input terminal VSUP2 of the Hall chip U3 is connected to VDD; the first power input terminal VSUP1 of the Hall chip U3 is connected to a first analog ground AGND1 via the capacitor C15; the second power input terminal VSUP2 of the Hall chip U3 is connected to a second analog ground AGND2 via the capacitor C16; a first ground terminal GND1 of the Hall chip U3 is connected to the first analog ground AGND1; a second ground terminal GND2 of the Hall chip U3 is connected to the first analog ground AGND1; The second analog ground AGND2 is connected, the first ground terminal GND1 of the Hall chip U3 is connected to the fourth test terminal TEST4 of the Hall chip U3, the second ground terminal GND2 of the Hall chip U3 is connected to the eighth test terminal TEST8 of the Hall chip U3, the first output terminal OUT1 of the Hall chip U3 is connected to the first analog ground AGND1 through the capacitor C19, the capacitor C17 and the capacitor C18 are both connected in parallel with the capacitor C19, the third output terminal OUT3 of the Hall chip U3 is connected to the second analog ground AGND2 through the capacitor C20, the capacitor C21 and the capacitor C22 are both connected in parallel with the capacitor C20, and the first output terminal OUT1 and the third output terminal OUT3 of the Hall chip U3 are both connected to the output protection module (3).

6. The dual-output pulse width modulation shifter circuit according to claim 5, characterized in that: The output protection module (3) comprises a first output protection circuit (131) and a second output protection circuit (132); the first output terminal OUT1 of the Hall chip U3 is connected to the first output protection circuit (131); and the third output terminal OUT3 of the Hall chip U3 is connected to the second output protection circuit (132).

7. The dual-output pulse width modulation shifter circuit according to claim 6, characterized in that: The first output protection circuit (131) comprises a resistor R5, a resistor R6, a diode D31, and a diode D32, one end of the resistor R5 is connected to the first output terminal OUT1 of the Hall chip U3, the other end of the resistor R5 is connected to one end of the resistor R6, the other end of the resistor R6 outputs a first PWM wave, the other end of the resistor R5 is connected to VCC via the diode D31, and the VCC is connected to the cathode of the diode D1 via the diode D32.

8. The dual-output pulse width modulation shifter circuit according to claim 7, characterized in that: The second output protection circuit (132) includes a resistor R7, a resistor R8, a diode D41, and a diode D42. One end of the resistor R7 is connected to the third output terminal OUT3 of the Hall chip U3, the other end of the resistor R7 is connected to one end of the resistor R8, the other end of the resistor R8 outputs a second PWM wave, the other end of the resistor R7 is connected to VDD through the diode D41, and the VDD is connected to the cathode of the diode D2 through the diode D42.

9. The dual-output pulse width modulation shifter circuit according to claim 8, characterized in that: The output interface module (5) comprises a first output interface circuit (51) and a second output interface circuit, the first output interface circuit (51) comprising an output connector J1, a resistor R11, and a transient voltage suppressor diode T3, the input power supply (14), the first ground signal GND-0, and the first PWM wave are all connected to the output connector J1, and the output connector J1 is connected to VCC via the resistor R11; The second output interface circuit (52) includes an output connector J2, a resistor 12, and a transient voltage suppressor diode T4. The input power supply (14), the second ground signal GND-2, and the second PWM wave are all connected to the output connector J2. The output connector J2 is connected to VDD through a resistor R12.

10. A dual-output pulse width modulation shifter circuit according to any one of claims 1 to 9, characterized in that: The shielded network module (4) includes a first shielding circuit and a second shielding circuit. The first shielding circuit includes a resistor R9 and a capacitor C23. One end of the resistor R9 is connected to the metal housing (6), one end of the resistor R9 is connected to the first power ground PGND1, the other end of the resistor R9 is connected to the first analog ground AGND1, and the capacitor C23 is connected in parallel with the resistor R9. The second shielding circuit includes a resistor R10 and a capacitor C24. One end of the resistor R10 is connected to the metal housing (6), one end of the resistor R10 is connected to the second power ground PGND2, the other end of the resistor R10 is connected to the second analog ground AGND2, and the capacitor C24 is connected in parallel with the resistor R10.

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