IO-Link slave station circuit supporting cascade connection

Abstract

The utility model relates to the technical field of IO-Link, in particular to an IO-Link slave station circuit supporting cascading, which comprises a master control module, a power supply module, a cascading circuit, an IO-Link communication circuit and a digital quantity interface circuit, wherein the master control module is in data communication with IO-Link master station equipment through the IO-Link communication circuit; according to the cascading IO-Link slave station circuit provided by the utility model, an expansion port of a slave station can be cascaded with a slave station by using an IO-Link communication interface, communication between a first-stage slave station and a second-stage slave station can be carried out at a distance of 20m, and the distance between the second-stage slave station and a master station can reach 40m. And thus, higher flexibility is brought to on-site signal acquisition and control.

Description

Technical Field

[0001] The utility model relates to the technical field of IO-Link, in particular to an IO-Link slave circuit supporting cascade. Background Art

[0002] The length of IO-Link master-slave communication cables can affect communication efficiency. Because IO-Link is a high-speed digital communication technology, its transmission rate depends on cable length. Longer cables reduce transmission rates, which in turn affects communication efficiency. Furthermore, cable length affects signal strength. As cables become longer, signal strength weakens, further impacting communication efficiency. Therefore, when using IO-Link master-slave communication, cable length should be minimized to ensure efficient communication. Consequently, the maximum transmission distance for IO-Link is limited to 20 meters.

[0003] This has created a bottleneck problem in the application of IO-Link technology. To address the shortcomings of the existing technology, a Chinese patent document discloses an "IO-Link repeater long-line transceiver supporting SIO function" (Announcement No. CN213693739U), which discloses an IO-Link repeater long-line transceiver supporting SIO function. Although this patent document mentions extending the transmission distance of IO-Link, it mainly solves the transmission distance problem by adding a repeater between the master station and the slave station. Not only does it require an external power supply, but it also requires two repeaters, which increases the cost of the transmission line equipment. Utility Model Content

[0004] The utility model provides an IO-Link slave circuit supporting cascade, which increases the IO-Link communication distance through the cascade circuit.

[0005] In order to achieve the purpose of the present invention, the technical solution adopted is: a cascade-supported IO-Link slave circuit, including a master control module, a power module, a cascade circuit, an IO-Link communication circuit and a digital interface circuit, wherein the master control module communicates data with the IO-Link master device through the IO-Link communication circuit;

[0006] The power supply module is used to convert the input power supply voltage into the internal required voltage;

[0007] The IO-Link communication circuit is used to connect to the IO-Link master station communication cable, convert the IO-Link communication level signal into a serial port signal, and provide power supply voltage to the power module;

[0008] The cascade circuit is used to connect the communication cable of the next-level IO-Link slave station, transmit the communication level signal of the next-level IO-Link system to the circuit of this level, and provide the power supply voltage to the next level;

[0009] The digital quantity interface circuit is used to connect the main control module with an external input or output digital quantity device.

[0010] As an optimized solution of the present invention, the main control module includes a microcontroller U1, and the microcontroller U1 is GD32F103VCT6.

[0011] As an optimization solution of the present utility model, the IO-Link communication circuit includes an IO-Link communication transceiver chip U2, a current limiting resistor R1, a resistor R2, a resistor R3, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6 and a capacitor C7. The first pin of the IO-Link communication transceiver chip U2 is connected to the capacitor C1 and the 3.3V power supply, and the other end of the capacitor C1 is grounded. The second pin of the IO-Link communication transceiver chip U2 is connected to the 3.3V power supply and the parallel capacitor C6 and resistor R3, and the other ends of the capacitor C6 and the resistor R3 are grounded. The third pin of the IO-Link communication transceiver chip U2 is the data receiving port of the chip, which is connected to the parallel capacitor C7 and the resistor R2. The other ends of the capacitor C7 and the resistor R2 are grounded. The fourth pin of the IO-Link communication transceiver chip U2 is a fault diagnosis pin, connected to the current limiting resistor R1 for the chip The output is enabled, the fifth pin of the IO-Link communication transceiver chip U2 is the data sending port, the sixth pin of the IO-Link communication transceiver chip U2 is the overload diagnosis port of the chip, the seventh, eighth and thirteenth pins of the IO-Link communication transceiver chip U2 are connected to GND, the ninth pin of the IO-Link communication transceiver chip U2 is connected to capacitor C5, and the other end of capacitor C5 is grounded, the tenth pin of the IO-Link communication transceiver chip U2 is connected to capacitor C4, and the other end of capacitor C4 is grounded, the eleventh pin of the IO-Link communication transceiver chip U2 is connected to capacitor C3, and the other end of capacitor C3 is grounded, the ninth pin, tenth pin and eleventh pin of the IO-Link communication transceiver chip U2 are connected as the I / O receiving pin of the chip, the twelfth pin of the IO-Link communication transceiver chip U2 is connected to capacitor C2 and a 24V power supply, and the other end of capacitor C2 is grounded.

[0012] As an optimized solution of the present utility model, the cascade circuit includes an RS485 transceiver U3, a capacitor C10 and a resistor R11. Pin 1 of the RS485 transceiver U3 is connected to pin 87 of the microcontroller U1, pins 2 and 3 of the RS485 transceiver U3 are connected to pin 88 of the microcontroller U1, and pin 4 of the RS485 transceiver U3 is connected to pin 86 of the microcontroller U1.

[0013] As an optimized solution of the present utility model, the digital interface circuit includes an optocoupler output circuit and an optocoupler input circuit.

[0014] As an optimized solution of the present invention, the power module includes a DCDC power conversion chip U4, a capacitor C11, a capacitor C12, a capacitor C13, a resistor R21, a resistor R22, a capacitor C15, a capacitor C14, a voltage regulator D1, an inductor L1, a capacitor C16, a capacitor C17, a resistor R23, a resistor R24, a resistor R25 and a resistor R26. The capacitor C11, the capacitor C12 and the capacitor C13 are connected in parallel between the second pin of the DCDC power conversion chip U4 and the ground. The second pin of the DCDC power conversion chip U4 is grounded through the series-connected resistors R21 and R22. The fourth pin of the DCDC power conversion chip U4 is grounded through the capacitor C15. Capacitor C14 is connected between pin 1 and pin 8 of the DCDC power conversion chip U4, regulator D1 is connected between pin 8 and pin 7 of the DCDC power conversion chip U4, inductor L1 and parallel capacitor C18 and capacitor C19 are connected in series between pin 8 and pin 7 of the DCDC power conversion chip U4, capacitor C16 and resistor R23 are connected in series and then connected in parallel with capacitor C17 between pin 6 of the DCDC power conversion chip U4 and ground, resistors R24, R25 and R26 are connected in series between the output pin of the power module and ground, and pin 5 of the DCDC power conversion chip U4 is grounded through resistor R26.

[0015] This utility model has the following positive effects: 1) It provides a cascadeable IO-Link slave circuit. The slave's expansion port uses the IO-Link communication interface to cascade another slave. A primary slave and a secondary slave can communicate over a distance of 20 meters, and a secondary slave can be up to 40 meters from the master. This provides greater flexibility for on-site signal acquisition and control. Furthermore, the primary and secondary slaves can be swapped through parameter configuration, eliminating the need for mismatching.

[0016] 2) The utility model expands the number of slave ports to 15 and the number of IO channels to 30, while only occupying one IO-Link master port, which better shares the cost of the master and reduces the cost of port use. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The present invention will be further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0018] Figure 1 This is a principle block diagram of the utility model;

[0019] Figure 2 This is the circuit schematic diagram of the main control module of the utility model;

[0020] Figure 3 This is a circuit schematic diagram of the IO-Link communication circuit of the utility model;

[0021] Figure 4 It is a circuit principle diagram of the utility model cascade circuit;

[0022] Figure 5 This is a circuit schematic diagram of the optocoupler output circuit of the utility model;

[0023] Figure 6 This is a circuit schematic diagram of the optocoupler input circuit of the utility model;

[0024] Figure 7 This is a circuit diagram of the power module of the utility model;

[0025] Figure 8 It is a schematic diagram of an application scenario of the present utility model. DETAILED DESCRIPTION

[0026] like Figure 1 As shown, the utility model discloses an IO-Link slave circuit supporting cascade, including a master control module, a power module, a cascade circuit, an IO-Link communication circuit and a digital interface circuit. The master control module communicates data with the IO-Link master device through the IO-Link communication circuit;

[0027] The power module is used to convert the input power voltage into the required internal voltage;

[0028] An IO-Link communication circuit, used to connect to an IO-Link master communication cable, convert IO-Link communication level signals into serial port signals, and provide power supply voltage to the power module;

[0029] The cascade circuit is used to connect the communication cable of the next-level IO-Link slave station, transmit the communication level signal of the next-level IO-Link system to the circuit of this level, and provide power supply voltage to the next level;

[0030] The digital interface circuit is used to connect the main control module with an external input or output digital device.

[0031] like Figure 2 As shown, the main control module includes a microcontroller U1, which is a GD32F103VCT6. The GD32F103VCT6 is a 32-bit microcontroller based on the ARM Cortex-M3 core. It has a frequency of up to 72MHz and supports multiple serial communication protocols such as USART, I2C, and SPI.

[0032] like Figure 3 As shown, the IO-Link communication circuit includes an IO-Link communication transceiver chip U2, a current limiting resistor R1, a resistor R2, a resistor R3, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6 and a capacitor C7. The first pin of the IO-Link communication transceiver chip U2 is connected to the capacitor C1 and a 3.3V power supply, and the other end of the capacitor C1 is grounded. The second pin of the IO-Link communication transceiver chip U2 is connected to the 3.3V power supply and the parallel capacitor C6 and resistor R3. The other ends of the capacitor C6 and the resistor R3 are grounded. The third pin of the IO-Link communication transceiver chip U2 is the data receiving port of the chip and is connected to the parallel capacitor C7 and resistor R2. The other ends of the capacitor C7 and the resistor R2 are grounded. The fourth pin of the IO-Link communication transceiver chip U2 is a fault diagnosis pin, which is connected to the current limiting resistor R1 to enable the output of the chip. Pin 5 of IO-Link communication transceiver chip U2 is the data transmission port. Pin 6 of IO-Link communication transceiver chip U2 is the chip's overload diagnostic port. Pins 7, 8, and 13 of IO-Link communication transceiver chip U2 are connected to GND. Pin 9 of IO-Link communication transceiver chip U2 is connected to capacitor C5, the other end of which is grounded. Pin 10 of IO-Link communication transceiver chip U2 is connected to capacitor C4, the other end of which is grounded. Pin 11 of IO-Link communication transceiver chip U2 is connected to capacitor C3, the other end of which is grounded. Pins 9, 10, and 11 of IO-Link communication transceiver chip U2 are connected as the chip's I / O receiving pins. Pin 12 of IO-Link communication transceiver chip U2 is connected to capacitor C2 and a 24V power supply, the other end of which is grounded. C1 is a filter coupling capacitor, and C2 is a filter coupling capacitor.

[0033] The IO-Link communication transceiver chip is the L6362A. The L6362A is an IO-Link and SIO mode transceiver compatible with PHY2 (3-wire connection) and supports COM1 (4.8k baud), COM2 (38.4kbaud), and COM3 (230.4kbaud) modes. The output stage can be configured as high-side, low-side, or push-pull, and can drive resistive, capacitive, and inductive loads. It can be connected to sensor chips in industrial 24V environments. The L6362A features reverse polarity protection between the VCC, GND, OUTH, OUTL, and I / Q pins. It also provides protection against output short-circuit, overvoltage, and surge voltage (±1kV pulse amplitude, 1.2 / 50μs pulse duration, 500Ω source impedance).

[0034] like Figure 4As shown, the cascade circuit includes an RS485 transceiver U3, capacitor C10, and resistor R11. Pin 1 of the RS485 transceiver U3 is connected to pin 87 of the microcontroller U1, pins 2 and 3 of the RS485 transceiver U3 are connected to pin 88 of the microcontroller U1, and pin 4 of the RS485 transceiver U3 is connected to pin 86 of the microcontroller U1. The cascade circuit uses the RS485 serial bus standard to transmit the collected data from the next-level slave circuit to the internal storage space of the master control module. The master control module then transmits the received data to the IO-Link master device via the IO-Link communication circuit. The 485 transceiver U3 is a SP3485EN-L / TR chip.

[0035] The digital interface circuit includes an optocoupler output circuit and an optocoupler input circuit. Figure 5 As shown in the figure, the optocoupler output circuit uses the PC817C chip. Figure 6 As shown, the optocoupler input circuit uses the CYTLP521-1 (GB-TP2) chip

[0036] like Figure 7 As shown, the power supply module includes a DCDC power conversion chip U4, a capacitor C11, a capacitor C12, a capacitor C13, a resistor R21, a resistor R22, a capacitor C15, a capacitor C14, a voltage regulator D1, an inductor L1, a capacitor C16, a capacitor C17, a resistor R23, a resistor R24, a resistor R25 and a resistor R26. The capacitor C11, the capacitor C12 and the capacitor C13 are connected in parallel between the second pin of the DCDC power conversion chip U4 and the ground. The second pin of the DCDC power conversion chip U4 is grounded through the series resistor R21 and the resistor R22. The fourth pin of the DCDC power conversion chip U4 is grounded through the capacitor C15. The capacitor C14 is connected to the ground. Connected between pin 1 and pin 8 of the DCDC power conversion chip U4, the voltage regulator D1 is connected between pin 8 and pin 7 of the DCDC power conversion chip U4, the inductor L1 and the parallel capacitors C18 and C19 are connected in series between pin 8 and pin 7 of the DCDC power conversion chip U4, the series capacitor C16 and resistor R23 are connected in series and then connected in parallel with capacitor C17 between pin 6 of the DCDC power conversion chip U4 and ground, the resistors R24, R25 and R26 are connected in series between the output pin of the power module and ground, and the pin 5 of the DCDC power conversion chip U4 is grounded through resistor R26.

[0037] The power module converts the input 24V power supply voltage and outputs a 3.3V internal voltage. The power module uses a DC-DC power conversion chip to convert the input 24V power supply voltage to a 3.3V internal voltage. The DC-DC power conversion chip uses the TI TPS54331D chip.

[0038] like Figure 8 As shown, microcontroller U1 connects to IO-Link transceiver U2 via its serial interface. IO-Link transceiver U2 then connects to the IO-Link master via a dedicated cable. IO-Link transceiver U2 is responsible for bidirectional data transmission and level adaptation. If multiple slaves are present, RS485 transceiver U3 can be used for cascading expansion to support additional devices.

[0039] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. An IO-Link slave circuit supporting cascading, characterized by: It includes a main control module, a power module, a cascade circuit, an IO-Link communication circuit and a digital interface circuit. The main control module communicates data with the IO-Link master device through the IO-Link communication circuit. The power supply module is used to convert the input power supply voltage into the internal required voltage; The IO-Link communication circuit is used to connect to the IO-Link master station communication cable, convert the IO-Link communication level signal into a serial port signal, and provide power supply voltage to the power module; The cascade circuit is used to connect the communication cable of the next-level IO-Link slave station, transmit the communication level signal of the next-level IO-Link system to the circuit of this level, and provide the power supply voltage to the next level; The digital quantity interface circuit is used to connect the main control module with an external input or output digital quantity device.

2. The IO-Link slave circuit supporting cascade according to claim 1, characterized in that: The main control module includes a microcontroller U1, which is GD32F103VCT6.

3. The IO-Link slave circuit supporting cascade according to claim 2, characterized in that: The IO-Link communication circuit includes an IO-Link communication transceiver chip U2, a current limiting resistor R1, a resistor R2, a resistor R3, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6 and a capacitor C7. The first pin of the IO-Link communication transceiver chip U2 is connected to the capacitor C1 and a 3.3V power supply, and the other end of the capacitor C1 is grounded. The second pin of the IO-Link communication transceiver chip U2 is connected to the 3.3V power supply and the parallel capacitor C6 and the resistor R3. The other ends of the capacitor C6 and the resistor R3 are grounded. The third pin of the IO-Link communication transceiver chip U2 is the data receiving port of the chip and is connected to the parallel capacitor C7 and the resistor R2. The other ends of the capacitor C7 and the resistor R2 are grounded. The fourth pin of the IO-Link communication transceiver chip U2 is a fault diagnosis pin, which is connected to the current limiting resistor R1 to enable the output of the chip. The fifth pin of the IO-Link communication transceiver chip U2 is the data sending port, the sixth pin of the IO-Link communication transceiver chip U2 is the overload diagnosis port of the chip, the seventh, eighth and thirteenth pins of the IO-Link communication transceiver chip U2 are connected to GND, the ninth pin of the IO-Link communication transceiver chip U2 is connected to capacitor C5, and the other end of capacitor C5 is grounded, the tenth pin of the IO-Link communication transceiver chip U2 is connected to capacitor C4, and the other end of capacitor C4 is grounded, the eleventh pin of the IO-Link communication transceiver chip U2 is connected to capacitor C3, and the other end of capacitor C3 is grounded, the ninth pin, tenth pin and eleventh pin of the IO-Link communication transceiver chip U2 are connected as the I / O receiving pin of the chip, the twelfth pin of the IO-Link communication transceiver chip U2 is connected to capacitor C2 and a 24V power supply, and the other end of capacitor C2 is grounded.

4. The IO-Link slave circuit supporting cascade according to claim 3, characterized in that: The cascade circuit includes an RS485 transceiver U3, a capacitor C10 and a resistor R11. Pin 1 of the RS485 transceiver U3 is connected to pin 87 of the microcontroller U1, pins 2 and 3 of the RS485 transceiver U3 are connected to pin 88 of the microcontroller U1, and pin 4 of the RS485 transceiver U3 is connected to pin 86 of the microcontroller U1.

5. The IO-Link slave circuit supporting cascade according to claim 1, characterized in that: The digital interface circuit includes an optocoupler output circuit and an optocoupler input circuit.

6. The IO-Link slave circuit supporting cascade according to claim 1, characterized in that: The power supply module includes a DCDC power conversion chip U4, a capacitor C11, a capacitor C12, a capacitor C13, a resistor R21, a resistor R22, a capacitor C15, a capacitor C14, a voltage regulator D1, an inductor L1, a capacitor C16, a capacitor C17, a resistor R23, a resistor R24, a resistor R25 and a resistor R26. The capacitors C11, C12 and C13 are connected in parallel between the second pin of the DCDC power conversion chip U4 and the ground. The second pin of the DCDC power conversion chip U4 is grounded through the series resistors R21 and R22. The fourth pin of the DCDC power conversion chip U4 is grounded through the capacitor C15. The capacitor C14 is connected in parallel between the second pin of the DCDC power conversion chip U4 and the ground. Connected between pin 1 and pin 8 of the DCDC power conversion chip U4, the voltage regulator D1 is connected between pin 8 and pin 7 of the DCDC power conversion chip U4, the inductor L1 and the parallel capacitors C18 and C19 are connected in series between pin 8 and pin 7 of the DCDC power conversion chip U4, the series capacitor C16 and resistor R23 are connected in series and then connected in parallel with capacitor C17 between pin 6 of the DCDC power conversion chip U4 and ground, the resistors R24, R25 and R26 are connected in series between the output pin of the power module and ground, and the pin 5 of the DCDC power conversion chip U4 is grounded through resistor R26.

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