Network port communication detection module and interface chip

Abstract

The utility model discloses a network port communication detection module and an interface chip, and relates to the technical field of network port communication. The circuit comprises a chip power supply detection circuit. The chip power supply detection circuit comprises a first AND gate unit, a first phase inverter and a first indicating lamp unit. Wherein a power supply pin of the interface chip is coupled with the input end of the first AND gate unit, the output end of the first AND gate unit is coupled with the input end of the first phase inverter, and the output end of the first phase inverter is coupled with the input end of the first indicator light unit, so that the power supply pin of the interface chip is coupled with the input end of the first AND gate unit through light of the first indicator light unit. And indicating the operation condition of the power supply pin of the interface chip. Therefore, when register information of the PHY chip cannot be read in the function test or use process of the network communication module, whether the voltage of the power supply pin of the PHY chip is abnormal or not can be checked through on-off of the first indicator lamp unit.

Description

Technical Field

[0001] The utility model relates to the technical field of network port communication, in particular to a network port communication detection module and an interface chip. Background Art

[0002] Currently, the network ports of some controller boards usually process information using a main control chip, which then sends the output signal to a physical layer interface (PHY) chip, which then passes through a network transformer and a network socket to the receiving end.

[0003] With the increasing development of network circuit modules, the main control chip in the network circuit module usually does not have any abnormalities. However, occasionally, an abnormality may occur that the PHY chip cannot recognize. As a result, during the functional testing or use of the network communication module, the PHY chip register information cannot be read and the problem cannot be corrected. Utility Model Content

[0004] In view of the problem that when a physical layer interface chip has an abnormality, it is impossible to read the register information of the PHY chip and find the problem point, the present utility model is proposed to provide a network port communication detection module and interface chip that overcome the above problem or at least partially solve the above problem.

[0005] Based on the first aspect of the present utility model, a network port communication detection module is provided, wherein the network port communication detection module includes a chip power supply detection circuit, and the chip power supply detection circuit includes a first AND gate unit, a first inverter and a first indicator light unit; wherein,

[0006] The power supply pin of the interface chip is coupled to the input end of the first AND gate unit, and the output end of the first AND gate unit is coupled to the input end of the first inverter, and the output end of the first inverter is coupled to the input end of the first indicator light unit to indicate the operating status of the power supply pin of the interface chip through the light of the first indicator light unit.

[0007] In an optional utility model, the first AND gate unit is a two-input AND gate circuit, wherein a first input terminal of the first AND gate unit is coupled to a power supply pin of the interface chip, and a second input terminal is coupled to a first reference voltage, and the first reference voltage is a high level;

[0008] When the voltage of the power supply pin of the interface chip is undervoltage, the first AND gate unit outputs a low level; when the voltage of the power supply pin of the interface chip is normal, the first AND gate unit outputs a high level.

[0009] In an optional utility model, the first indicator light unit includes a first switch tube, a first light-emitting diode, and a first resistor, wherein the base of the first switch tube is coupled to the output end of the first inverter, one end of the first resistor is coupled to the anode of the first light-emitting diode, and the other end is coupled to the power supply, the cathode of the first light-emitting diode is coupled to the collector of the first switch tube, and the emitter of the first switch tube is grounded; wherein,

[0010] The first switch tube is in a cut-off state when the first inverter outputs a low level, and the first light-emitting diode is powered off, so as to indicate that the voltage of the power supply pin of the interface chip is normal;

[0011] The first switch tube is in a conducting state when the first inverter outputs a high level, and the first light-emitting diode is powered on and emits light to indicate that the voltage of the power supply pin of the interface chip is undervoltage.

[0012] In an optional utility model, the first indicator light unit includes a first switch tube, a first light-emitting diode, and a first resistor, wherein the base of the first switch tube is coupled to the output end of the first inverter, one end of the first resistor is coupled to the anode of the first light-emitting diode, and the other end is coupled to the power supply, the cathode of the first light-emitting diode is coupled to the emitter of the first switch tube, and the collector of the first switch tube is grounded; wherein,

[0013] The first switch tube forms a cut-off state when the first inverter outputs a high level, and the first light-emitting diode is powered off, so as to indicate that the voltage of the power supply pin of the interface chip is undervoltage;

[0014] The first switch tube is in a conducting state when the first inverter outputs a low level, and the first light-emitting diode is powered on and emits light to indicate that the voltage of the power supply pin of the interface chip is normal.

[0015] In an optional utility model, the chip power supply detection circuit further includes a first pull-down resistor, one end of the first pull-down resistor is grounded, and the other end is coupled to the input end of the first inverter.

[0016] An optional utility model content, the chip power supply detection circuit also includes a first pull-up resistor, one end of the first pull-up resistor is coupled to the power supply, and the other end is coupled to the input end of the first indicator light unit.

[0017] An optional utility model content, the network port communication detection module includes a chip clock detection circuit, the chip clock detection circuit includes a second AND gate unit, a second inverter and a second indicator light unit; wherein,

[0018] The clock pin of the interface chip is coupled to the input end of the second AND gate unit, and the output end of the second AND gate unit is coupled to the input end of the second inverter, and the output end of the second inverter is coupled to the input end of the second indicator light unit to indicate the operation status of the clock pin of the interface chip through the light of the second indicator light unit.

[0019] In an optional utility model, the second AND gate unit is a two-input AND gate circuit, wherein a first input terminal of the second AND gate unit is coupled to a clock pin of the interface chip, and a second input terminal is coupled to a second reference voltage, and the second reference voltage is a high level;

[0020] When the clock pin of the interface chip is at a low level, the second AND gate unit outputs a low level; when the clock pin of the interface chip is at a high level, the second AND gate unit outputs a high level.

[0021] An optional utility model content, the network port communication detection module includes a chip data detection circuit, the chip data detection circuit includes a third AND gate unit, a third inverter and a third indicator light unit; wherein,

[0022] The data pin of the interface chip is coupled to the input end of the third AND gate unit, and the output end of the third AND gate unit is coupled to the input end of the third inverter, and the output end of the third inverter is coupled to the input end of the third indicator light unit to indicate the operation status of the data pin of the interface chip through the light of the third indicator light unit.

[0023] In an optional utility model, the third AND gate unit is a two-input AND gate circuit, wherein a first input terminal of the third AND gate unit is coupled to a data pin of the interface chip, and a second input terminal is coupled to a third reference voltage, and the third reference voltage is a high level;

[0024] When the data pin of the interface chip is at a low level, the third AND gate unit outputs a low level. When the voltage of the data pin of the interface chip is at a high level, the third AND gate unit outputs a high level.

[0025] An optional utility model content, the network port communication detection module includes a chip reset detection circuit, the chip reset detection circuit includes a fourth AND gate unit, a fourth inverter and a fourth indicator light unit; wherein,

[0026] The reset pin of the interface chip is coupled to the input end of the fourth AND gate unit, and the output end of the fourth AND gate unit is coupled to the input end of the fourth inverter, and the output end of the fourth inverter is coupled to the input end of the fourth indicator light unit to indicate the operation status of the reset pin of the interface chip through the light of the fourth indicator light unit.

[0027] In an optional utility model, the fourth AND gate unit is a two-input AND gate circuit, wherein a first input terminal of the fourth AND gate unit is coupled to a reset pin of the interface chip, and a second input terminal is coupled to a fourth reference voltage, and the fourth reference voltage is a high level;

[0028] When the reset pin of the interface chip is at a low level, the fourth AND gate unit outputs a low level; and when the reset pin of the interface chip is at a high level, the fourth AND gate unit outputs a high level.

[0029] Based on the second aspect of the present utility model, an interface chip is further provided, wherein the interface chip includes the network port communication detection module as described in any one of the above utility models.

[0030] Compared with the prior art, the present invention includes a chip power supply detection circuit, which includes a first AND gate unit, a first inverter, and a first indicator light unit. The power supply pin of the interface chip is coupled to the input end of the first AND gate unit, and the output end of the first AND gate unit is coupled to the input end of the first inverter, and the output end of the first inverter is coupled to the input end of the first indicator light unit, so as to indicate the operation status of the power supply pin of the interface chip through the light of the first indicator light unit. Therefore, during the functional test or use of the network communication module, if the register information of the PHY chip cannot be read, the power supply pin voltage of the PHY chip can be checked by turning on and off the first indicator light unit to check whether it is abnormal.

[0031] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be construed as limiting the present invention. The same reference numerals are used throughout the accompanying drawings to denote the same components.

[0033] In the attached figure:

[0034] Figure 1 This is a schematic structural diagram of a chip power supply detection circuit provided by an embodiment of the present utility model;

[0035] Figure 2 This is a structural diagram of another chip power supply detection circuit provided by an embodiment of the present utility model;

[0036] Figure 3 This is a structural diagram of a second network port communication detection module provided by an embodiment of the present utility model;

[0037] Figure 4 This is a structural diagram of a third network port communication detection module provided by an embodiment of the present utility model;

[0038] Figure 5 This is a structural diagram of a fourth network port communication detection module provided by an embodiment of the present utility model;

[0039] Figure 1: 1. Chip power supply detection circuit; 11. First AND gate unit; 12. First inverter; 13. First indicator light unit; 131. First switch tube; 132. First light emitting diode; 133. First resistor; 14. First pull-down resistor; 15. First pull-up resistor; 16. First filter capacitor; 17. First filter resistor; 2. Chip clock detection circuit; 21. Second AND gate unit; 22. Second inverter; 23. Second indicator light unit; 231. Second switch tube; 232. Second light emitting diode; 233. Second resistor; 24. Second pull-down resistor; 25. Second pull-up resistor; 26. Second filter capacitor; 27. Second filter Resistor; 3. Chip data detection circuit; 31. Third AND gate unit; 32. Third inverter; 33. Third indicator light unit; 331. Third switch tube; 332. Third light-emitting diode; 333. Third resistor; 34. Third pull-down resistor; 35. Third pull-up resistor; 36. Third filter capacitor; 37. Third filter resistor; 4. Chip reset detection circuit; 41. Fourth AND gate unit; 42. Fourth inverter; 43. Fourth indicator light unit; 431. Fourth switch tube; 432. Fourth light-emitting diode; 433. Fourth resistor; 44. Fourth pull-down resistor; 45. Fourth pull-up resistor; 46. Fourth filter capacitor; 47. Fourth filter resistor. DETAILED DESCRIPTION

[0040] The following describes exemplary embodiments of the present invention in more detail with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0041] Currently, the network ports of some controller boards usually process information using a main control chip, which then sends the output signal to a physical layer interface (PHY) chip, which then passes through a network transformer and a network socket to the receiving end.

[0042] With the increasing development of network circuit modules, the main control chip in the network circuit module usually does not have any abnormalities. However, occasionally, an abnormality may occur that the PHY chip cannot recognize. As a result, during the functional testing or use of the network communication module, the PHY chip register information cannot be read and the problem cannot be corrected.

[0043] Based on the above technical problems, an embodiment of the present utility model is proposed. The embodiment of the present utility model may include a chip power supply detection circuit, and the chip power supply detection circuit includes a first AND gate unit, a first inverter and a first indicator light unit. Among them, the power supply pin of the interface chip is coupled to the input end of the first AND gate unit, and the output end of the first AND gate unit is coupled to the input end of the first inverter, and the output end of the first inverter is coupled to the input end of the first indicator light unit, so as to indicate the operation status of the power supply pin of the interface chip through the light of the first indicator light unit. Therefore, during the functional test or use of the network communication module, when the register information of the PHY chip cannot be read, the power supply pin voltage of the PHY chip can be checked by turning on and off the first indicator light unit to check whether it is abnormal.

[0044] Reference Figure 1-5 An embodiment of the present invention provides a network port communication detection module, which may include a chip power supply detection circuit 1, which includes a first AND gate unit 11, a first inverter 12, and a first indicator light unit 13. The power supply pin of the interface chip is coupled to the input of the first AND gate unit 11, and the output of the first AND gate unit 11 is coupled to the input of the first inverter 12. The output of the first inverter 12 is coupled to the input of the first indicator light unit 13, so that the light of the first indicator light unit 13 indicates the operating status of the power supply pin of the interface chip.

[0045] In an embodiment of the present invention, the chip power supply detection circuit 1 is used to detect whether the voltage of the power supply pin (VDD pin) of the PHY chip is abnormal. The chip power supply detection circuit 1 may include a first AND gate unit 11, a first inverter 12, and a first indicator light unit 13. The first AND gate unit 11 is an AND gate circuit. The first AND gate unit 11 has at least two input terminals. When the input voltages of at least two input terminals are both high, the first AND gate unit 11 outputs a high level. If the input voltage of one input terminal is low, the first AND gate unit 11 outputs a low level. One of the input terminals of the first AND gate unit 11 is coupled to the power supply pin of the interface chip. The other input terminals of the first AND gate unit 11, except for the input terminal coupled to the power supply pin, are each coupled to a high level. Therefore, when the voltage of the power supply pin is normal, for example, typically 3.3V (volts), the first AND gate unit 11 outputs a high level. When the voltage of the power supply pin is undervoltage, the first AND gate unit 11 outputs a low level.

[0046] High and low levels refer to the voltage levels of a signal. A high level generally represents a logic 1 (True), while a low level generally represents a logic 0 (False). For example, a high level corresponds to a voltage range of 2.4V to 5V, while a low level corresponds to a voltage range of 0V to 0.8V.

[0047] The first inverter 12 is used to convert voltage levels. For example, when a high level is input to the input of the first inverter 12, the output of the first inverter 12 outputs a low level. When a low level is input to the input of the first inverter 12, the output of the first inverter 12 outputs a high level. The input of the first inverter 12 is coupled to the output of the first AND gate unit 11, thereby converting the voltage level output by the output of the first AND gate unit 11, avoiding interference during voltage transmission, and shaping the voltage input to the first AND gate unit 11, thereby improving the transmission stability of the voltage signal and the detection accuracy of the circuit.

[0048] The first indicator light unit 13 may include a switching electronic device and a light-emitting electronic device. The output of the first inverter 12 is coupled to the input of the first indicator light unit 13. Thus, the on and off states of the switching electronic device in the first indicator light unit 13 can be controlled by the level of the output of the first inverter 12. In the on state, the light-emitting electronic device is powered on and emits light, while in the off state, the light-emitting electronic device is powered off. Therefore, during functional testing or use of the network communication module, if the register information of the PHY chip cannot be read, the on and off of the light-emitting electronic device in the first indicator light unit 13 can be used to check whether the voltage on the power supply pin of the PHY chip is abnormal.

[0049] For example, when the light-emitting electronic device in the first indicator light unit 13 emits light, the voltage of the power supply pin of the PHY chip is determined to be abnormal. When the light-emitting electronic device in the first indicator light unit 13 does not emit light, the voltage of the power supply pin of the PHY chip is determined to be normal.

[0050] An optional embodiment of the utility model, referring to Figure 1 and Figure 2 As shown, the first AND gate unit 11 is a two-input AND gate circuit, wherein the first input terminal of the first AND gate unit 11 is coupled to the power supply pin of the interface chip, and the second input terminal is coupled to a first reference voltage, and the first reference voltage is a high level. When the voltage of the power supply pin of the interface chip is undervoltage, the first AND gate unit 11 outputs a low level, and when the voltage of the power supply pin of the interface chip is normal, the first AND gate unit 11 outputs a high level.

[0051] In an embodiment of the present invention, the first AND gate unit 11 can be a two-input AND gate circuit, wherein the first input end of the first AND gate unit 11 is coupled to the power supply pin of the interface chip, and the second input end of the first AND gate unit 11 is coupled to a first reference voltage (VDD_REF), and the first reference voltage is a high level. For example, the first reference voltage can be 3.3V, or about 3.5V. When the voltage of the power supply pin of the interface chip is undervoltage (the corresponding voltage value is within the low-level voltage range), the first AND gate unit 11 outputs a low level. When the voltage of the power supply pin of the interface chip is normal (the corresponding voltage value is within the high-level voltage range), the first AND gate unit 11 outputs a high level.

[0052] An optional embodiment of the utility model, referring to Figure 1As shown, the first indicator light unit 13 includes a first switch 131, a first light-emitting diode 132, and a first resistor 133. The base of the first switch 131 is coupled to the output of the first inverter 12. One end of the first resistor 133 is coupled to the anode of the first light-emitting diode 132, and the other end is coupled to the power supply (VCC). The cathode of the first light-emitting diode 132 is coupled to the collector of the first switch 131, and the emitter of the first switch 131 is grounded (GND). When the first inverter 12 outputs a low level, the first switch 131 is turned off, and the first light-emitting diode 132 is powered off, indicating that the voltage of the power supply pin of the interface chip is normal. When the first inverter 12 outputs a high level, the first switch 131 is turned on, and the first light-emitting diode 132 is powered on and illuminated, indicating that the voltage of the power supply pin of the interface chip is undervoltage.

[0053] In the embodiment of the present invention, the first indicator light unit 13 may include a first switch tube 131, a first light emitting diode 132 and a first resistor 133, wherein the first switch tube 131 is a switch electronic device, which may be one of the following types: NPN transistor and PNP transistor

[0054] In some embodiments, when the first switch 131 is an NPN transistor, the base of the first switch 131 is coupled to the output of the first inverter 12, one end of the first resistor 133 is coupled to the anode of the first light-emitting diode 132, and the other end of the first resistor 133 is coupled to a power supply, for example, 5V. The cathode of the first light-emitting diode 132 is coupled to the collector of the first switch 131, and the emitter of the first switch 131 is grounded. Thus, when the first switch 131 is in the on state, the first light-emitting diode 132 is powered on and emits light, and when the first switch 131 is in the off state, the first light-emitting diode 132 is powered off and does not emit light.

[0055] Correspondingly, when the voltage at the power supply pin of the interface chip is normal, the first AND gate unit 11 outputs a high level, which in turn outputs a low level via the first inverter 12. The first switch 131 remains in the off state due to the low level, and the first light-emitting diode 132 does not emit light. When the voltage at the power supply pin of the interface chip is abnormal, the first AND gate unit 11 outputs a low level, which in turn outputs a high level via the first inverter 12. The first switch 131 becomes conductive due to the high level, and the first light-emitting diode 132 emits light. Thus, a user can determine whether the power supply pin voltage is abnormal based on whether the first light-emitting diode 132 emits light.

[0056] Another optional embodiment of the utility model, referring to Figure 2 As shown, when the first switch 131 is a PNP transistor, the base of the first switch 131 is coupled to the output terminal of the first inverter 12, one end of the first resistor 133 is coupled to the anode of the first light-emitting diode 132, and the other end of the first resistor 133 is coupled to the power supply. The cathode of the first light-emitting diode 132 is coupled to the emitter of the first switch 131, and the collector of the first switch 131 is grounded. Thus, when the first switch 131 is in the on state, the first light-emitting diode 132 is powered on and emits light, and when the first switch 131 is in the off state, the first light-emitting diode 132 is powered off and does not emit light.

[0057] Correspondingly, when the voltage at the power supply pin of the interface chip is normal, the first AND gate unit 11 outputs a high level, which in turn outputs a low level via the first inverter 12. The first switch 131 is turned on by the low level, and the first light-emitting diode 132 emits light. When the voltage at the power supply pin of the interface chip is abnormal, the first AND gate unit 11 outputs a low level, which in turn outputs a high level via the first inverter 12. The first switch 131 remains off by the high level, and the first light-emitting diode 132 does not emit light. Thus, a user can determine whether the power supply pin voltage is abnormal based on whether the first light-emitting diode 132 emits light.

[0058] An optional embodiment of the utility model, referring to Figure 1 and Figure 2 As shown, the chip power supply detection circuit 1 further includes a first pull-down resistor 14 , one end of the first pull-down resistor 14 is grounded, and the other end is coupled to the input end of the first inverter 12 .

[0059] In the embodiment of the present invention, one end of the first pull-down resistor 14 is grounded, and the other end is coupled to the input end of the first inverter 12, so that the first pull-down resistor 14 can be coupled to the input end of the first inverter 12. Therefore, it is possible to ensure that the input end of the first inverter 12 maintains a low level in an idle state (no external signal input), thereby stabilizing the input signal of the first inverter 12.

[0060] An optional embodiment of the utility model, referring to Figure 1 and Figure 2 As shown, the chip power supply detection circuit 1 further includes a first pull-up resistor 15 , one end of the first pull-up resistor 15 is coupled to the power supply, and the other end is coupled to the input end of the first indicator light unit 13 .

[0061] In an embodiment of the present invention, one end of the first pull-up resistor 15 is coupled to the power supply, and the other end of the first pull-up resistor 15 is coupled to the input end of the first indicator light unit 13, thereby providing a pull-up voltage, which can increase the voltage value of the high level output by the input end of the first indicator light unit 13 (also known as the output end of the first inverter 12), thereby enhancing the driving capability of the first indicator light unit 13.

[0062] In some optional utility model embodiments, referring to Figure 1 and Figure 2 As shown, the chip power supply detection circuit 1 may further include a first filter capacitor 16 and a first filter resistor 17, wherein the first filter capacitor 16 and the first filter resistor 17 are arranged in parallel, and a first connection point between the first filter capacitor 16 and the first filter resistor 17 is grounded, and a second connection point between the first filter capacitor 16 and the first filter resistor 17 is coupled to the base of the first switching transistor 131. This can stabilize the voltage input to the first switching transistor 131, thereby improving the operating stability and response accuracy of the first switching transistor 131.

[0063] An optional embodiment of the utility model, referring to Figure 3 As shown, the network port communication detection module includes a chip clock detection circuit 2, which includes a second AND gate unit 21, a second inverter 22, and a second indicator light unit 23. The clock pin of the interface chip is coupled to the input of the second AND gate unit 21, and the output of the second AND gate unit 21 is coupled to the input of the second inverter 22. The output of the second inverter 22 is coupled to the input of the second indicator light unit 23, so that the light of the second indicator light unit 23 indicates the operating status of the clock pin of the interface chip.

[0064] In an embodiment of the present invention, the chip clock detection circuit 2 is used to detect whether the voltage of the clock pin (MDC pin) of the PHY chip is abnormal. The chip clock detection circuit 2 may include a second AND gate unit 21, a second inverter 22, and a second indicator light unit 23. The second AND gate unit 21 is an AND gate circuit. The second AND gate unit 21 has at least two input terminals. When the input voltages of at least two input terminals are both high, the second AND gate unit 21 outputs a high level. If the input voltage of one input terminal is low, the second AND gate unit 21 outputs a low level. One of the input terminals of the second AND gate unit 21 is coupled to the clock pin of the interface chip. The other input terminals of the second AND gate unit 21, except the input terminal coupled to the clock pin, are each coupled to a high level. Therefore, when the voltage of the clock pin is normal, the clock pin remains at a high level, and the second AND gate unit 21 outputs a high level. When the voltage of the clock pin is abnormal, the clock pin is at a low level, and the second AND gate unit 21 outputs a low level.

[0065] The second inverter 22 is used to convert voltage levels. For example, when a high level is input to the input of the second inverter 22, the output of the second inverter 22 outputs a low level. When a low level is input to the input of the second inverter 22, the output of the second inverter 22 outputs a high level. The input of the second inverter 22 is coupled to the output of the second AND gate unit 21, thereby converting the voltage level output by the output of the second AND gate unit 21, avoiding interference during voltage transmission, and shaping the voltage input to the second AND gate unit 21, thereby improving the transmission stability of the voltage signal and the detection accuracy of the circuit.

[0066] The second indicator light unit 23 may include a switching electronic device and a light-emitting electronic device. The output of the second inverter 22 is coupled to the input of the second indicator light unit 23. The on and off states of the switching electronic device in the second indicator light unit 23 can be controlled by the level of the output of the second inverter 22. In the on state, the light-emitting electronic device is powered on and emits light, while in the off state, the light-emitting electronic device is powered off. Therefore, if the register information of the PHY chip cannot be read during functional testing or use of the network communication module, the on and off of the light-emitting electronic device in the second indicator light unit 23 can be used to check whether the clock pin voltage of the PHY chip is abnormal.

[0067] For example, when the light-emitting electronic device in the second indicator light unit 23 emits light, the clock pin voltage of the PHY chip is determined to be abnormal. When the light-emitting electronic device in the second indicator light unit 23 does not emit light, the clock pin voltage of the PHY chip is determined to be normal.

[0068] In an optional embodiment of the utility model, the second AND gate unit 21 is a two-input AND gate circuit, wherein a first input terminal of the second AND gate unit 21 is coupled to a clock pin of the interface chip, and a second input terminal is coupled to a second reference voltage, and the second reference voltage is a high level. When the clock pin of the interface chip is at a low level, the second AND gate unit 21 outputs a low level, and when the clock pin of the interface chip is at a high level, the second AND gate unit 21 outputs a high level.

[0069] In an embodiment of the present invention, the second AND gate unit 21 can be a two-input AND gate circuit, wherein the first input end of the second AND gate unit 21 is coupled to the clock pin of the interface chip, and the second input end of the second AND gate unit 21 is coupled to a second reference voltage (MDC_REF), and the second reference voltage is a high level. For example, the second reference voltage can be 3.3V or about 3.5V. When the voltage of the clock pin of the interface chip is undervoltage (the corresponding voltage value is within the low level voltage range), the second AND gate unit 21 outputs a low level. When the voltage of the clock pin of the interface chip is normal (the corresponding voltage value is within the high level voltage range), the second AND gate unit 21 outputs a high level.

[0070] In an embodiment of the present invention, the second indicator light unit 23 may include a second switch tube 231, a second light-emitting diode 232 and a second resistor 233, wherein the second switch tube 231 is a switching electronic device, which may be one of the following types: NPN transistor and PNP transistor.

[0071] In some embodiments, reference Figure 3 As shown, if the second switch 231 is an NPN transistor, the base of the second switch 231 is coupled to the output of the second inverter 22, one end of the second resistor 233 is coupled to the anode of the second light-emitting diode 232, and the other end of the second resistor 233 is coupled to a power supply, which can be, for example, 5V. The cathode of the second light-emitting diode 232 is coupled to the collector of the second switch 231, and the emitter of the second switch 231 is grounded. Thus, when the second switch 231 is in the on state, the second light-emitting diode 232 is powered on and emits light, and when the second switch 231 is in the off state, the second light-emitting diode 232 is powered off and does not emit light.

[0072] Correspondingly, when the clock pin voltage of the interface chip is normal, the second AND gate unit 21 outputs a high level, which in turn outputs a low level via the second inverter 22. The second switch 231 remains in the off state due to the low level, and the second light-emitting diode 232 does not emit light. When the clock pin voltage of the interface chip is abnormal, the second AND gate unit 21 outputs a low level, which in turn outputs a high level via the second inverter 22. The second switch 231 is turned on due to the high level, and the second light-emitting diode 232 emits light. Thus, a user can determine whether the clock pin voltage is abnormal based on whether the second light-emitting diode 232 emits light.

[0073] In another optional embodiment of the utility model, when the second switch tube 231 is a PNP transistor, the base of the second switch tube 231 is coupled to the output terminal of the second inverter 22, one end of the second resistor 233 is coupled to the anode of the second light-emitting diode 232, and the other end of the second resistor 233 is coupled to the power supply, the cathode of the second light-emitting diode 232 is coupled to the emitter of the second switch tube 231, and the collector of the second switch tube 231 is grounded. Thus, when the second switch tube 231 is in the on state, the second light-emitting diode 232 is powered on and emits light, and when the second switch tube 231 is in the off state, the second light-emitting diode 232 is powered off and does not emit light.

[0074] Correspondingly, when the clock pin voltage of the interface chip is normal, the second AND gate unit 21 outputs a high level, which in turn outputs a low level via the second inverter 22. The second switch 231 is turned on by the low level, and the second light-emitting diode 232 emits light. When the clock pin voltage of the interface chip is abnormal, the second AND gate unit 21 outputs a low level, which in turn outputs a high level via the second inverter 22. The second switch 231 remains off by the high level, and the second light-emitting diode 232 does not emit light. Thus, a user can determine whether the clock pin voltage is abnormal based on whether the second light-emitting diode 232 emits light.

[0075] An optional embodiment of the utility model, referring to Figure 3 As shown, the chip clock detection circuit 2 further includes a second pull-down resistor 24 , one end of the second pull-down resistor 24 is grounded, and the other end is coupled to the input end of the second inverter 22 .

[0076] In an embodiment of the present invention, one end of the second pull-down resistor 24 is grounded, and the other end is coupled to the input end of the second inverter 22, so that the second pull-down resistor 24 can be coupled to the input end of the second inverter 22. As a result, it can be ensured that the input end of the second inverter 22 maintains a low level in an idle state (no external signal input), thereby stabilizing the input signal of the second inverter 22.

[0077] An optional embodiment of the utility model, referring to Figure 3 As shown, the chip clock detection circuit 2 further includes a second pull-up resistor 25 , one end of the second pull-up resistor 25 is coupled to the power supply, and the other end is coupled to the input end of the second indicator light unit 23 .

[0078] In an embodiment of the present invention, one end of the second pull-up resistor 25 is coupled to the power supply, and the other end of the second pull-up resistor 25 is coupled to the input end of the second indicator light unit 23, thereby providing a pull-up voltage, which can increase the voltage value of the high level output by the input end of the second indicator light unit 23 (also known as the output end of the second inverter 22), thereby enhancing the driving capability of the second indicator light unit 23.

[0079] In some optional utility model embodiments, referring to Figure 3 As shown, the chip clock detection circuit 2 may further include a second filter capacitor 26 and a second filter resistor 27, wherein the second filter capacitor 26 and the second filter resistor 27 are arranged in parallel, and a first connection point between the second filter capacitor 26 and the second filter resistor 27 is grounded, and a second connection point between the second filter capacitor 26 and the second filter resistor 27 is coupled to the base of the second switching transistor 231. This can stabilize the voltage input to the second switching transistor 231, thereby improving the operating stability and response accuracy of the second switching transistor 231.

[0080] An optional embodiment of the utility model, referring to Figure 4 As shown, the network port communication detection module includes a chip data detection circuit 3, which includes a third AND gate unit 31, a third inverter 32, and a third indicator light unit 33. The data pin of the interface chip is coupled to the input of the third AND gate unit 31, and the output of the third AND gate unit 31 is coupled to the input of the third inverter 32. The output of the third inverter 32 is coupled to the input of the third indicator light unit 33, so that the light of the third indicator light unit 33 indicates the operating status of the data pin of the interface chip.

[0081] In an embodiment of the present invention, the chip data detection circuit 3 is used to detect whether the voltage of the data pin (MDIO pin) of the PHY chip is abnormal. The chip data detection circuit 3 may include a third AND gate unit 31, a third inverter 32, and a third indicator light unit 33. The third AND gate unit 31 is an AND gate circuit. The third AND gate unit 31 has at least two input terminals. When the input voltage of at least two input terminals is high, the third AND gate unit 31 outputs a high level. If the input voltage of one input terminal is low, the third AND gate unit 31 outputs a low level. One input terminal of the third AND gate unit 31 is coupled to the data pin of the interface chip. The other input terminals of the third AND gate unit 31, except the input terminal coupled to the data pin, are each coupled to a high level. Therefore, when the voltage of the data pin is normal, the data pin remains at a high level, and the third AND gate unit 31 outputs a high level. When the voltage of the data pin is abnormal, the data pin is at a low level, and the third AND gate unit 31 outputs a low level.

[0082] The third inverter 32 is used to convert voltage levels. For example, when a high level is input to the input of the third inverter 32, the output of the third inverter 32 outputs a low level. When a low level is input to the input of the third inverter 32, the output of the third inverter 32 outputs a high level. The input of the third inverter 32 is coupled to the output of the third AND gate unit 31, thereby converting the voltage level output by the output of the third AND gate unit 31, avoiding interference during voltage transmission, and shaping the voltage input to the third AND gate unit 31, thereby improving the transmission stability of the voltage signal and the detection accuracy of the circuit.

[0083] The third indicator light unit 33 may include a switching electronic device and a light-emitting electronic device. The output of the third inverter 32 is coupled to the input of the third indicator light unit 33. The voltage level at the output of the third inverter 32 controls the on and off states of the switching electronic device in the third indicator light unit 33. In the on state, the light-emitting electronic device is powered on and emits light, while in the off state, the light-emitting electronic device is powered off. Therefore, if the register information of the PHY chip cannot be read during functional testing or use of the network communication module, the on and off of the light-emitting electronic device in the third indicator light unit 33 can be used to check whether the data pin voltage of the PHY chip is abnormal.

[0084] For example, when the light-emitting electronic device in the third indicator light unit 33 emits light, it is determined that the data pin voltage of the PHY chip is abnormal. When the light-emitting electronic device in the third indicator light unit 33 does not emit light, it is determined that the data pin voltage of the PHY chip is normal.

[0085] In an optional embodiment of the utility model, the third AND gate unit 31 is a two-input AND gate circuit, wherein a first input terminal of the third AND gate unit 31 is coupled to a data pin of the interface chip, and a second input terminal is coupled to a third reference voltage, wherein the third reference voltage is a high level. When the data pin of the interface chip is at a low level, the third AND gate unit 31 outputs a low level; when the voltage of the data pin of the interface chip is at a high level, the third AND gate unit 31 outputs a high level.

[0086] In an embodiment of the present invention, the third AND gate unit 31 may be a two-input AND gate circuit, wherein a first input of the third AND gate unit 31 is coupled to a data pin of the interface chip, and a second input of the third AND gate unit 31 is coupled to a third reference voltage (MDIO_REF), wherein the third reference voltage is a high level. For example, the third reference voltage may be approximately 3.3V or 3.5V. When the voltage of the data pin of the interface chip is undervoltage (the corresponding voltage value is within a low voltage range), the third AND gate unit 31 outputs a low level. When the voltage of the data pin of the interface chip is normal (the corresponding voltage value is within a high voltage range), the third AND gate unit 31 outputs a high level.

[0087] In an embodiment of the present invention, the third indicator light unit 33 may include a third switch tube 331, a third light-emitting diode 332 and a third resistor 333, wherein the third switch tube 331 is a switching electronic device, which may be one of the following types: NPN transistor and PNP transistor.

[0088] In some embodiments, reference Figure 4 As shown, if the third switch 331 is an NPN transistor, the base of the third switch 331 is coupled to the output of the third inverter 32, one end of the third resistor 333 is coupled to the anode of the third light-emitting diode 332, and the other end of the third resistor 333 is coupled to a power supply, which can be, for example, 5V. The cathode of the third light-emitting diode 332 is coupled to the collector of the third switch 331, and the emitter of the third switch 331 is grounded. Thus, when the third switch 331 is in the on state, the third light-emitting diode 332 is powered on and emits light, and when the third switch 331 is in the off state, the third light-emitting diode 332 is powered off and does not emit light.

[0089] Correspondingly, when the data pin voltage of the interface chip is normal, the third AND gate unit 31 outputs a high level, which is then outputted via the third inverter 32 as a low level. The third switch 331 remains in an off state due to the low level, and the third light-emitting diode 332 does not emit light. When the data pin voltage of the interface chip is abnormal, the third AND gate unit 31 outputs a low level, which is then outputted via the third inverter 32 as a high level. The third switch 331 is turned on due to the high level, and the third light-emitting diode 332 emits light. Thus, a user can determine whether the data pin voltage is abnormal based on whether the third light-emitting diode 332 emits light.

[0090] In another optional embodiment of the utility model, when the third switch tube 331 is a PNP transistor, the base of the third switch tube 331 is coupled to the output terminal of the third inverter 32, one end of the third resistor 333 is coupled to the anode of the third light-emitting diode 332, and the other end of the third resistor 333 is coupled to the power supply, the cathode of the third light-emitting diode 332 is coupled to the emitter of the third switch tube 331, and the collector of the third switch tube 331 is grounded. Thus, when the third switch tube 331 is in the on state, the third light-emitting diode 332 is powered on and emits light, and when the third switch tube 331 is in the off state, the third light-emitting diode 332 is powered off and does not emit light.

[0091] Correspondingly, when the data pin voltage of the interface chip is normal, the third AND gate unit 31 outputs a high level, which, after passing through the third inverter 32, outputs a low level. The third switch 331 is turned on by the low level, and the third light-emitting diode 332 emits light. When the data pin voltage of the interface chip is abnormal, the third AND gate unit 31 outputs a low level, which, after passing through the third inverter 32, outputs a high level. The third switch 331 remains off by the high level, and the third light-emitting diode 332 does not emit light. Thus, a user can determine whether the data pin voltage is abnormal based on whether the third light-emitting diode 332 emits light.

[0092] An optional embodiment of the utility model, referring to Figure 4 As shown, the chip data detection circuit 3 further includes a third pull-down resistor 34 , one end of the third pull-down resistor 34 is grounded, and the other end is coupled to the input end of the third inverter 32 .

[0093] In an embodiment of the present invention, one end of the third pull-down resistor 34 is grounded, and the other end is coupled to the input end of the third inverter 32, so that the third pull-down resistor 34 can be coupled to the input end of the third inverter 32. As a result, it can be ensured that the input end of the third inverter 32 maintains a low level in an idle state (no external signal input), thereby playing a role in stabilizing the input signal of the third inverter 32.

[0094] An optional embodiment of the utility model, referring to Figure 4 As shown, the chip data detection circuit 3 further includes a third pull-up resistor 35 , one end of the third pull-up resistor 35 is coupled to the power supply, and the other end is coupled to the input end of the third indicator light unit 33 .

[0095] In an embodiment of the present invention, one end of the third pull-up resistor 35 is coupled to the power supply, and the other end of the third pull-up resistor 35 is coupled to the input end of the third indicator light unit 33, thereby providing a pull-up voltage, which can increase the voltage value of the high level output by the input end of the third indicator light unit 33 (also known as the output end of the third inverter 32), thereby enhancing the driving capability of the third indicator light unit 33.

[0096] In some optional utility model embodiments, referring to Figure 4 As shown, the chip data detection circuit 3 may further include a third filter capacitor 36 and a third filter resistor 37, wherein the third filter capacitor 36 and the third filter resistor 37 are arranged in parallel, and a first connection point between the third filter capacitor 36 and the third filter resistor 37 is grounded, and a second connection point between the third filter capacitor 36 and the third filter resistor 37 is coupled to the base of the third switch tube 331. This can stabilize the voltage input to the third switch tube 331, thereby improving the operating stability and response accuracy of the third switch tube 331.

[0097] An optional embodiment of the utility model, referring to Figure 5 As shown, the network port communication detection module includes a chip reset detection circuit 4, which includes a fourth AND gate unit 41, a fourth inverter 42, and a fourth indicator light unit 43. The reset pin of the interface chip is coupled to the input of the fourth AND gate unit 41, and the output of the fourth AND gate unit 41 is coupled to the input of the fourth inverter 42. The output of the fourth inverter 42 is coupled to the input of the fourth indicator light unit 43, so that the light of the fourth indicator light unit 43 indicates the operation status of the reset pin of the interface chip.

[0098] In an embodiment of the present invention, the chip reset detection circuit 4 is used to detect whether the voltage of the reset pin (NRESET pin) of the PHY chip is abnormal. The chip reset detection circuit 4 may include a fourth AND gate unit 41, a fourth inverter 42, and a fourth indicator light unit 43, wherein the fourth AND gate unit 41 is an AND gate circuit, the fourth AND gate unit 41 has at least two input terminals, and when the input voltages of at least two input terminals are both high, the fourth AND gate unit 41 outputs a high level. If the input voltage of one of the input terminals is low, the fourth AND gate unit 41 outputs a low level. One of the input terminals of the fourth AND gate unit 41 is coupled to the reset pin of the interface chip, and the other input terminals of the fourth AND gate unit 41, except the input terminal coupled to the reset pin, are respectively coupled to a high level, so that when the voltage of the reset pin is in a normal state, the reset pin remains in a high level state, and the fourth AND gate unit 41 outputs a high level. When the reset pin is reset, it maintains a low level for a period of time, and the reset pin outputs a low level. Correspondingly, the fourth AND gate unit 41 outputs a low level.

[0099] The fourth inverter 42 is used to convert voltage levels. For example, when a high level is input to the input of the fourth inverter 42, the output of the fourth inverter 42 outputs a low level. When a low level is input to the input of the fourth inverter 42, the output of the fourth inverter 42 outputs a high level. The input of the fourth inverter 42 is coupled to the output of the fourth AND gate unit 41, thereby converting the voltage level output by the output of the fourth AND gate unit 41, avoiding interference during voltage transmission, and shaping the voltage input to the fourth AND gate unit 41, thereby improving the transmission stability of the voltage signal and the detection accuracy of the circuit.

[0100] The fourth indicator light unit 43 may include a switching electronic device and a light-emitting electronic device. The output of the fourth inverter 42 is coupled to the input of the fourth indicator light unit 43. The level of the output of the fourth inverter 42 controls the on and off states of the switching electronic device in the fourth indicator light unit 43. In the on state, the light-emitting electronic device is powered on and emits light, while in the off state, the light-emitting electronic device is powered off. Therefore, if the register information of the PHY chip cannot be read during functional testing or use of the network communication module, the on and off of the light-emitting electronic device in the fourth indicator light unit 43 can be used to check whether the reset pin voltage of the PHY chip is abnormal.

[0101] For example, when the light-emitting electronic device in the fourth indicator light unit 43 emits light, it is determined that the reset pin of the PHY chip performs the reset function. When the light-emitting electronic device in the fourth indicator light unit 43 does not emit light, it is determined that the reset pin voltage of the PHY chip is normal.

[0102] In an optional embodiment of the utility model, the fourth AND gate unit 41 is a two-input AND gate circuit, wherein a first input terminal of the fourth AND gate unit 41 is coupled to a reset pin of the interface chip, and a second input terminal is coupled to a fourth reference voltage, wherein the fourth reference voltage is a high level. When the reset pin of the interface chip is at a low level, the fourth AND gate unit 41 outputs a low level; when the reset pin of the interface chip is at a high level, the fourth AND gate unit 41 outputs a high level.

[0103] In an embodiment of the present invention, the fourth AND gate unit 41 can be a two-input AND gate circuit, wherein the first input terminal of the fourth AND gate unit 41 is coupled to the reset pin of the interface chip, and the second input terminal of the fourth AND gate unit 41 is coupled to a fourth reference voltage (NRESET_REF), wherein the fourth reference voltage is a high level. For example, the fourth reference voltage can be 3.3V or about 3.5V. When the voltage of the reset pin of the interface chip is at a low level (the corresponding voltage value is within the voltage range of the low level), the fourth AND gate unit 41 outputs a low level. When the reset pin of the interface chip is in a non-reset state, the voltage is at a high level (the corresponding voltage value is within the voltage range of the high level), the fourth AND gate unit 41 outputs a high level.

[0104] In an embodiment of the present invention, the fourth indicator light unit 43 may include a fourth switch tube 431, a fourth light-emitting diode 432 and a fourth resistor 433, wherein the fourth switch tube 431 is a switching electronic device, which may be one of the following types: NPN transistor and PNP transistor.

[0105] In some embodiments, reference Figure 5 As shown, if the fourth switch 431 is an NPN transistor, the base of the fourth switch 431 is coupled to the output of the fourth inverter 42, one end of the fourth resistor 433 is coupled to the anode of the fourth light-emitting diode 432, and the other end of the fourth resistor 433 is coupled to a power supply, which can be, for example, 5V. The cathode of the fourth light-emitting diode 432 is coupled to the collector of the fourth switch 431, and the emitter of the fourth switch 431 is grounded. Thus, when the fourth switch 431 is in the on state, the fourth light-emitting diode 432 is powered on and emits light, and when the fourth switch 431 is in the off state, the fourth light-emitting diode 432 is powered off and does not emit light.

[0106] Correspondingly, when the reset pin of the interface chip is in a normal state, the fourth AND gate unit 41 outputs a high level, which, after passing through the fourth inverter 42, outputs a low level. The fourth switch 431 remains in an off state due to the low level, and the fourth light-emitting diode 432 does not emit light. When the reset pin voltage of the interface chip is reset, the fourth AND gate unit 41 outputs a low level, which, after passing through the fourth inverter 42, outputs a high level. The fourth switch 431 becomes conductive due to the high level, and the fourth light-emitting diode 432 emits light. Thus, a user can determine whether the reset pin voltage is abnormal based on whether the fourth light-emitting diode 432 emits light.

[0107] In another optional embodiment of the utility model, when the fourth switch tube 431 is a PNP transistor, the base of the fourth switch tube 431 is coupled to the output terminal of the fourth inverter 42, one end of the fourth resistor 433 is coupled to the anode of the fourth light-emitting diode 432, and the other end of the fourth resistor 433 is coupled to the power supply, the cathode of the fourth light-emitting diode 432 is coupled to the emitter of the fourth switch tube 431, and the collector of the fourth switch tube 431 is grounded. Thus, when the fourth switch tube 431 is in the on state, the fourth light-emitting diode 432 is powered on and emits light, and when the fourth switch tube 431 is in the off state, the fourth light-emitting diode 432 is powered off and does not emit light.

[0108] Correspondingly, when the reset pin of the interface chip is in a normal state, the fourth AND gate unit 41 outputs a high level, which in turn outputs a low level via the fourth inverter 42. The fourth switch tube 431 is turned on by the low level, and the fourth light-emitting diode 432 emits light. When the reset pin of the interface chip outputs a low level during a reset, the fourth AND gate unit 41 outputs a low level, which in turn outputs a high level via the fourth inverter 42. The fourth switch tube 431 remains off by the high level, and the fourth light-emitting diode 432 does not emit light. Thus, a user can determine whether the reset pin voltage is abnormal based on whether the fourth light-emitting diode 432 emits light. For example, the state of the fourth light-emitting diode 432 can be used to determine whether the reset pin has been properly reset.

[0109] An optional embodiment of the utility model, referring to Figure 5 As shown, the chip reset detection circuit 4 further includes a fourth pull-down resistor 44 , one end of which is grounded, and the other end of which is coupled to the input end of the fourth inverter 42 .

[0110] In an embodiment of the present invention, one end of the fourth pull-down resistor 44 is grounded, and the other end is coupled to the input end of the fourth inverter 42, so that the fourth pull-down resistor 44 can be coupled to the input end of the fourth inverter 42. As a result, it can be ensured that the input end of the fourth inverter 42 maintains a low level in an idle state (no external signal input), thereby stabilizing the input signal of the fourth inverter 42.

[0111] An optional embodiment of the utility model, referring to Figure 5 As shown, the chip reset detection circuit 4 further includes a fourth pull-up resistor 45 , one end of which is coupled to the power supply, and the other end of which is coupled to the input end of the fourth indicator light unit 43 .

[0112] In an embodiment of the present invention, one end of the fourth pull-up resistor 45 is coupled to the power supply, and the other end of the fourth pull-up resistor 45 is coupled to the input end of the fourth indicator light unit 43, thereby providing a pull-up voltage, which can increase the input end of the fourth indicator light unit 43 (also known as the output end of the fourth inverter 42) to output a high-level voltage value, thereby enhancing the driving capability of the fourth indicator light unit 43.

[0113] In some optional utility model embodiments, referring to Figure 5 As shown, the chip reset detection circuit 4 may further include a fourth filter capacitor 46 and a fourth filter resistor 47, wherein the fourth filter capacitor 46 and the fourth filter resistor 47 are arranged in parallel, and a first connection point between the fourth filter capacitor 46 and the fourth filter resistor 47 is grounded, and a second connection point between the fourth filter capacitor 46 and the fourth filter resistor 47 is coupled to the base of the fourth switch tube 431. This can stabilize the voltage input to the fourth switch tube 431, thereby improving the operating stability and response accuracy of the fourth switch tube 431.

[0114] In an embodiment of the present utility model, a current limiting resistor can be set in the chip power supply detection circuit 1, the chip clock detection circuit 2, the chip data detection circuit 3 and the chip reset detection circuit 4. For example, the current limiting circuit can be set between the pin of the interface chip and the AND gate unit, and / or the current limiting resistor can be connected in series between the input end of the indicator light unit and the output end of the inverter. No further restrictions are made here.

[0115] An embodiment of the present utility model further discloses an interface chip, which includes the network port communication detection module as described in any one of the above utility models.

[0116] In an embodiment of the present utility model, the interface chip refers to a PHY chip, which can check whether the power supply pin voltage of the PHY chip is abnormal by turning on and off the first indicator light unit 13 during the functional test or use of the network communication module through the chip power supply detection circuit 1, the chip clock detection circuit 2, the chip data detection circuit 3 and the chip reset detection circuit 4. By turning on and off the second indicator light unit 23, it can be checked whether the clock pin voltage of the PHY chip is abnormal. By turning on and off the third indicator light unit 33, it can be checked whether the data pin voltage of the PHY chip is abnormal. By turning on and off the fourth indicator light unit 43, it can be checked whether the reset pin voltage of the PHY chip is abnormal. In this way, the corresponding problem point when an abnormality occurs in the PHY chip can be checked.

[0117] In summary, the embodiment of the present invention discloses a network port communication detection module and an interface chip. The embodiment of the present invention may include a chip power supply detection circuit 1, and the chip power supply detection circuit 1 includes a first AND gate unit 11, a first inverter 12, and a first indicator light unit 13. The power supply pin of the interface chip is coupled to the input end of the first AND gate unit 11, and the output end of the first AND gate unit 11 is coupled to the input end of the first inverter 12, and the output end of the first inverter 12 is coupled to the input end of the first indicator light unit 13, so as to indicate the operation status of the power supply pin of the interface chip through the light of the first indicator light unit 13. Therefore, during the functional test or use of the network communication module, if the register information of the PHY chip cannot be read, the first indicator light unit 13 can be turned on and off to check whether the power supply pin voltage of the PHY chip is abnormal.

[0118] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0119] It is easy for those skilled in the art to think that any combination of the above embodiments is feasible, so any combination of the above embodiments is an implementation scheme of the present invention. However, due to space limitations, this specification will not describe them in detail here.

[0120] In the description provided herein, numerous specific details are described. However, it is understood that embodiments of the present invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques are not shown in detail so as not to obscure the understanding of this description.

[0121] Similarly, it should be understood that in order to streamline the present invention and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the present invention, various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof.

[0122] Furthermore, those skilled in the art will appreciate that although some embodiments described herein include certain features included in other embodiments but not other features, combinations of features from different embodiments are intended to be within the scope of the present invention and to form different embodiments. For example, in the claims, any of the claimed embodiments may be used in any combination.

Claims

1. A network port communication detection module, characterized in that: The network port communication detection module comprises a chip power supply detection circuit (1), and the chip power supply detection circuit (1) comprises a first AND gate unit (11), a first inverter (12) and a first indicator light unit (13); wherein, The power supply pin of the interface chip is coupled to the input end of the first AND gate unit (11), and the output end of the first AND gate unit (11) is coupled to the input end of the first inverter (12), and the output end of the first inverter (12) is coupled to the input end of the first indicator light unit (13), so as to indicate the operation status of the power supply pin of the interface chip through the light of the first indicator light unit (13).

2. The network port communication detection module according to claim 1, characterized in that: The first AND gate unit (11) is a two-input AND gate circuit, wherein a first input end of the first AND gate unit (11) is coupled to a power supply pin of the interface chip, and a second input end is coupled to a first reference voltage, and the first reference voltage is a high level; When the voltage of the power supply pin of the interface chip is undervoltage, the first AND gate unit (11) outputs a low level; when the voltage of the power supply pin of the interface chip is normal, the first AND gate unit (11) outputs a high level.

3. The network port communication detection module according to claim 1, wherein: The first indicator light unit (13) comprises a first switch tube (131), a first light emitting diode (132) and a first resistor (133); the base of the first switch tube (131) is coupled to the output end of the first inverter (12); one end of the first resistor (133) is coupled to the positive electrode of the first light emitting diode (132), and the other end is coupled to the power supply; the cathode of the first light emitting diode (132) is coupled to the collector of the first switch tube (131); and the emitter of the first switch tube (131) is grounded; wherein, The first switch tube (131) is in a cut-off state when the first inverter (12) outputs a low level, and the first light-emitting diode (132) is powered off, to indicate that the voltage of the power supply pin of the interface chip is normal; The first switch tube (131) is in a conducting state when the first inverter (12) outputs a high level, and the first light-emitting diode (132) is powered on and emits light to indicate that the voltage of the power supply pin of the interface chip is undervoltage.

4. The network port communication detection module according to claim 1, characterized in that: The first indicator light unit (13) comprises a first switch tube (131), a first light emitting diode (132) and a first resistor (133); the base of the first switch tube (131) is coupled to the output end of the first inverter (12); one end of the first resistor (133) is coupled to the positive electrode of the first light emitting diode (132), and the other end is coupled to a power supply; the cathode of the first light emitting diode (132) is coupled to the emitter of the first switch tube (131); and the collector of the first switch tube (131) is grounded; wherein, The first switch tube (131) is in a cut-off state when the first inverter (12) outputs a high level, and the first light-emitting diode (132) is powered off, so as to indicate that the voltage of the power supply pin of the interface chip is undervoltage; The first switch tube (131) is in a conducting state when the first inverter (12) outputs a low level, and the first light-emitting diode (132) is powered on and emits light to indicate that the voltage of the power supply pin of the interface chip is normal.

5. The network port communication detection module according to claim 1, characterized in that: The chip power supply detection circuit (1) further includes a first pull-down resistor (14), one end of the first pull-down resistor (14) is grounded, and the other end is coupled to the input end of the first inverter (12).

6. The network port communication detection module according to claim 1, characterized in that: The chip power supply detection circuit (1) further includes a first pull-up resistor (15), one end of the first pull-up resistor (15) is coupled to the power supply, and the other end is coupled to the input end of the first indicator light unit (13).

7. The network port communication detection module according to claim 1, characterized in that: The network port communication detection module includes a chip clock detection circuit (2), and the chip clock detection circuit (2) includes a second AND gate unit (21), a second inverter (22) and a second indicator light unit (23); wherein, The clock pin of the interface chip is coupled to the input end of the second AND gate unit (21), and the output end of the second AND gate unit (21) is coupled to the input end of the second inverter (22), and the output end of the second inverter (22) is coupled to the input end of the second indicator light unit (23), so as to indicate the operation status of the clock pin of the interface chip through the light of the second indicator light unit (23).

8. The network port communication detection module according to claim 7, characterized in that: The second AND gate unit (21) is a two-input AND gate circuit, wherein a first input terminal of the second AND gate unit (21) is coupled to a clock pin of the interface chip, and a second input terminal is coupled to a second reference voltage, and the second reference voltage is a high level; When the clock pin of the interface chip is at a low level, the second AND gate unit (21) outputs a low level; when the clock pin of the interface chip is at a high level, the second AND gate unit (21) outputs a high level.

9. The network port communication detection module according to claim 1, characterized in that: The network port communication detection module includes a chip data detection circuit (3), and the chip data detection circuit (3) includes a third AND gate unit (31), a third inverter (32) and a third indicator light unit (33); wherein, The data pin of the interface chip is coupled to the input end of the third AND gate unit (31), and the output end of the third AND gate unit (31) is coupled to the input end of the third inverter (32), and the output end of the third inverter (32) is coupled to the input end of the third indicator light unit (33), so as to indicate the operation status of the data pin of the interface chip through the light of the third indicator light unit (33).

10. The network port communication detection module according to claim 9, characterized in that: The third AND gate unit (31) is a two-input AND gate circuit, wherein a first input terminal of the third AND gate unit (31) is coupled to a data pin of the interface chip, and a second input terminal is coupled to a third reference voltage, and the third reference voltage is a high level; When the data pin of the interface chip is at a low level, the third AND gate unit (31) outputs a low level; when the voltage of the data pin of the interface chip is at a high level, the third AND gate unit (31) outputs a high level.

11. The network port communication detection module according to claim 1, characterized in that: The network port communication detection module includes a chip reset detection circuit (4), and the chip reset detection circuit (4) includes a fourth AND gate unit (41), a fourth inverter (42) and a fourth indicator light unit (43); wherein, The reset pin of the interface chip is coupled to the input end of the fourth AND gate unit (41), and the output end of the fourth AND gate unit (41) is coupled to the input end of the fourth inverter (42), and the output end of the fourth inverter (42) is coupled to the input end of the fourth indicator light unit (43), so as to indicate the operation status of the reset pin of the interface chip through the light of the fourth indicator light unit (43).

12. The network port communication detection module according to claim 11, characterized in that: The fourth AND gate unit (41) is a two-input AND gate circuit, wherein a first input terminal of the fourth AND gate unit (41) is coupled to a reset pin of the interface chip, and a second input terminal is coupled to a fourth reference voltage, and the fourth reference voltage is a high level; When the reset pin of the interface chip is at a low level, the fourth AND gate unit (41) outputs a low level; when the reset pin of the interface chip is at a high level, the fourth AND gate unit (41) outputs a high level.

13. An interface chip, characterized in that: The interface chip includes the network port communication detection module according to any one of claims 1 to 12.

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