Device for capturing startup time sequence of OPS computer mainboard

Abstract

The utility model relates to a device for grabbing a startup time sequence of an OPS computer mainboard, which comprises a main control circuit board, and a USB controller, a USB interface and eight connecting pins are arranged on the main control circuit board; eight time sequence signal acquisition channels are correspondingly established between the main control circuit board and the eight connecting pins, and the main control circuit board is connected with the OPS computer mainboard through the eight connecting pins to obtain time sequence signals; a time sequence signal transmission path is established between the main control circuit board and the USB controller, and the USB controller is connected with an external terminal through a USB interface to output a plurality of time sequence signals; the whole device is small in size, multiple in time sequence acquisition channels, simple in debugging operation, convenient to carry and use, capable of being well matched with a large screen for debugging, convenient to observe logic time sequences of multiple groups of signals, and beneficial to rapidly solving the problem of startup abnormity of an OPS computer.

Description

Technical Field

[0001] The utility model relates to the technical field of OPS computers, and more particularly to a device for capturing the startup timing of an OPS computer mainboard. Background Art

[0002] An OPS (Open Pluggable Specification) computer is a small, portable computer pre-installed with an operating system that can be plugged directly into a monitor, keyboard, and mouse. OPS computers are commonly used in business meetings, classrooms, and public entertainment venues. However, with the increasing demand for smart classrooms and intelligent conferencing, large screens are also experiencing a host of new interface features, such as eDP, I2S audio signals, and network link signals. The richer the interface functionality between OPS computers and large screens, the more complex the OPS computer motherboard design becomes. Complex, coupled functions are more susceptible to external interference, leading to unexpected crashes, display failures, and startup issues when used with different large screens. Currently, the industry typically uses traditional oscilloscopes for debugging. However, oscilloscopes are large, complex to operate, and have limited debugging circuits. They are not very convenient for observing the logic timing of multiple signals and are not an effective solution to the many issues that can cause OPS computer startup errors. Utility Model Content

[0003] The technical problem to be solved by the present invention is to provide a device for capturing the startup timing of an OPS computer motherboard in response to the above-mentioned defects of the prior art.

[0004] The technical solution adopted by the utility model to solve its technical problems is: a device for capturing the startup timing of an OPS computer motherboard, the device comprising a main control circuit board, wherein the main control circuit board is provided with a USB controller, a USB interface and eight connecting pins; eight timing signal acquisition channels are correspondingly established between the main control circuit board and the eight connecting pins, the main control circuit board is connected to the OPS computer motherboard through the eight connecting pins to obtain timing signals; a timing signal transmission path is established between the main control circuit board and the USB controller, and the USB controller is connected to an external terminal through the USB interface to output multiple timing signals.

[0005] In some embodiments, each of the connecting pins is connected to the OPS computer motherboard via a timing line.

[0006] In some embodiments, the main control circuit board includes a development board, on which an MCU and MCU peripheral circuits are provided.

[0007] In some embodiments, the USB controller includes a USB control chip and a USB control chip peripheral circuit, and the USB control chip and the USB control chip peripheral circuit are both provided on a development board.

[0008] In some embodiments, the development board is also provided with a memory and memory peripheral circuits.

[0009] In some embodiments, the memory is FLASH flash memory.

[0010] In some embodiments, the model of the MCU is RP2040.

[0011] In some embodiments, the USB interface is a TYPE-C interface.

[0012] The beneficial effect of the present invention is that, different from the prior art, in the device for capturing the startup timing of an OPS computer motherboard of the present invention, the main control circuit board can establish a connection with the OPS computer motherboard through eight connecting pins, thereby obtaining the corresponding timing signal generated by the OPS computer motherboard through eight timing acquisition channels, and then transmitting it to the USB controller through the timing signal transmission path. After the USB controller establishes a connection with the external terminal through the USB interface, it will output the corresponding timing signal to the external terminal for processing. The overall device is small in size, has more timing acquisition channels, and is simple to debug, which is conducive to portable use. It can be well matched with a large screen for debugging, conveniently observing the logical timing of multiple groups of signals, and helps to quickly solve the problem of abnormal startup of the OPS computer. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a schematic diagram of a device for capturing the startup timing of an OPS computer motherboard in an embodiment of the utility model;

[0014] Figure 2 This is an application topology diagram of a device for capturing the startup timing of an OPS computer motherboard in an embodiment of the present utility model;

[0015] Figure 3 1 is a circuit diagram of the MCU in the embodiment of the present utility model;

[0016] Figure 4 This is a circuit diagram of a USB controller in an embodiment of the present utility model;

[0017] Figure 5 This is a circuit diagram of a memory in an embodiment of the present utility model;

[0018] Figure 6 It is a circuit diagram of the indicator light and the connecting pin in the embodiment of the utility model. DETAILED DESCRIPTION

[0019] The terms "first," "second," "third," and "fourth," etc., in the specification, claims, and accompanying drawings of the present invention are used to distinguish between different items, not to describe a specific order. Furthermore, the terms "including," "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, apparatus, product, or device comprising a series of steps or elements is not limited to the listed steps or elements, but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to the process, method, product, or device.

[0020] References to "embodiments" herein mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present invention. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0021] "Multiple" refers to two or more. "And / or" describes the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, or B exists alone. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0022] Moreover, the terms "up, down, front, back, left, right, upper end, lower end" and the like indicating directions are all based on the posture and position of the device or apparatus described in this solution during normal use.

[0023] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention more clear, the following will be described clearly and completely in conjunction with the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] The present invention provides a device 100 for capturing the startup sequence of an OPS computer motherboard. Figures 1 to 6As shown in , the device 100 includes a main control circuit board 10, which is provided with a USB controller 12, a USB interface 13 and eight connecting pins; eight timing signal acquisition channels are established between the main control circuit board 10 and the eight connecting pins, and the main control circuit board 10 is connected to the OPS computer motherboard 200 through the eight connecting pins to obtain timing signals; a timing signal transmission path is established between the main control circuit board 10 and the USB controller 12, and the USB controller 12 is connected to the external terminal through the USB interface 13 to output multiple timing signals.

[0025] Among them, eight connecting pins such as Figure 1 、 2 The figures are A0-A7, respectively. An external terminal, such as a PC 300 or a mobile phone 400, transmits multiple timing signals to the PC or mobile phone via the USB controller 12 via the USB interface 13. This facilitates analysis and processing of the acquired timing signals by relevant technicians via the PC or mobile phone. This simple operation improves the efficiency of portable analysis and processing of timing issues in OPS computers, helps shorten product development cycles, and enhances product maintainability. This effectively resolves the industry's current difficulty in debugging timing when using OPS computers with large screens.

[0026] In this embodiment, each connecting pin is connected to the OPS computer motherboard 200 via a timing line. For example, one of the connecting pins is connected to the CPU of the OPS computer motherboard 200 via a timing line, and is mainly used to obtain PLTRST# from the OPS computer motherboard 200. PLTRST# is the PCH reset signal. When this signal appears, it means that the ME has been initialized and is ready to enter the BIOS code initialization. This signal is used to check whether the PCH of the OPS motherboard 200 is damaged. Another connecting pin is connected to the standby power supply of the OPS computer motherboard 200 via another timing line, and is mainly used to obtain RSMRST# from the OPS computer motherboard 200. RSMRST# is the motherboard standby power. If this signal is always low, it means that the large screen is not powering the OPS computer, and the power status of the large screen and the OPS computer 80-pin connector needs to be checked. The other three connecting pins are connected to the PCH of the OPS computer motherboard 200 through three other timing lines, mainly used to obtain the corresponding SLP_S3#, SLP_S4#, and SLP_S5# timing signals (the timing line for SLP_S5# is not shown). The SLP_S3#, SLP_S4#, and SLP_S5# timing signals are sleep signals, hibernation signals, and soft shutdown signals, respectively. These signals can be used to check whether the ACPI status is normal when the OPS computer motherboard 200 interacts with the large screen. It is understandable that, according to actual debugging needs, the remaining connecting pins can also establish corresponding connections with the OPS computer motherboard 200 through other timing lines one by one to obtain other timing signals. The selection of each connecting pin can be random.

[0027] In this embodiment, the main control circuit board 10 includes a development board, on which an MCU 11 and MCU peripheral circuits are provided. For specific circuit structures, see Figure 3 The model of MCU11 is RP2040. The USB controller 12 includes a USB control chip and a peripheral circuit of the USB control chip. The USB control chip and the peripheral circuit of the USB control chip are both located on the development board. For the specific circuit structure, please refer to Figure 4 The development board also has a memory 14 and memory peripheral circuits. For the specific circuit structure, please refer to Figure 5 The memory 14 is a FLASH flash memory. Figure 6 This is a circuit diagram of the indicator lights and connection pins.

[0028] In this embodiment, the USB interface 13 is a TYPE-C interface, which establishes a data transmission connection with an external terminal through the USB protocol.

[0029] In this embodiment, the OPS computer motherboard 200 is an X86 multi-timing signal motherboard.

[0030] It should be understood that ordinary technical workers in this field can make improvements or changes based on the above description, and all these improvements and changes should fall within the scope of protection of the claims attached to this utility model.

Claims

1. A device for capturing the startup sequence of an OPS computer motherboard, characterized by: The device includes a main control circuit board, which is provided with a USB controller, a USB interface and eight connecting pins; eight timing signal acquisition channels are correspondingly established between the main control circuit board and the eight connecting pins, and the main control circuit board is connected to the OPS computer motherboard through the eight connecting pins to obtain timing signals; a timing signal transmission path is established between the main circuit board and the USB controller, and the USB controller is connected to an external terminal through the USB interface to output multiple timing signals.

2. The device for capturing the startup sequence of an OPS computer motherboard according to claim 1, characterized in that: Any of the connecting pins is connected to the OPS computer mainboard via a timing line.

3. The device for capturing the startup sequence of an OPS computer motherboard according to claim 1, characterized in that: The main control circuit board includes a development board, on which an MCU and MCU peripheral circuits are arranged.

4. The device for capturing the startup sequence of an OPS computer motherboard according to claim 3, characterized in that: The USB controller includes a USB control chip and a USB control chip peripheral circuit, and the USB control chip and the USB control chip peripheral circuit are both arranged on a development board.

5. The device for capturing the startup sequence of an OPS computer motherboard according to claim 3, characterized in that: The development board is also provided with a memory and memory peripheral circuits.

6. The device for capturing the startup sequence of an OPS computer motherboard according to claim 5, characterized in that: The memory is FLASH flash memory.

7. The device for capturing the startup sequence of an OPS computer motherboard according to any one of claims 3 to 6, characterized in that: The model of the MCU is RP2040.

8. The device for capturing the startup sequence of an OPS computer motherboard according to claim 1, characterized in that: The USB interface is a TYPE-C interface.

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