Display module and display device

Abstract

The utility model provides a display module and a display device.The display module of one embodiment comprises a display panel and a flexible circuit board electrically connected with the display panel, the display panel comprises a plurality of first pins, the flexible circuit board comprises a plurality of second pins, and the first pins and the second pins are electrically connected in a one-to-one correspondence mode; the plurality of second pins comprise a plurality of test pins which are arranged adjacently, the flexible circuit board further comprises a test network, the test network comprises a plurality of first wires and signal ports which are electrically connected with the first wires in a one-to-one correspondence mode, the signal ports are used for receiving test signals, and the adjacent test pins are electrically isolated. According to the display module provided by the embodiment of the invention, the adjacent test pins are electrically isolated, so that the display stability is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display module and a display device. Background Art

[0002] As the application scenarios of display products become more and more diverse, displays are gradually developing towards becoming thinner and lighter with narrower bezels. The peripheral wiring area will become narrower and narrower, and peripheral circuit structure defects will occur more frequently. Therefore, relevant tests need to be performed on the array substrate of the display during the production process to ensure the yield of the display.

[0003] Currently, after the array substrate reliability test, the display has X horizontal RB (red and blue) bright lines and Y vertical G (green) bright lines defects. Summary of the Invention

[0004] In order to solve at least one of the above problems, the first aspect of the present disclosure provides a display module, comprising: a display panel and a flexible circuit board electrically connected to the display panel,

[0005] The display panel includes a plurality of first pins, the flexible circuit board includes a plurality of second pins, the plurality of first pins and the plurality of second pins are electrically connected in a one-to-one correspondence, and the plurality of second pins include a plurality of test pins arranged adjacent to each other.

[0006] The flexible circuit board also includes a test network, which includes a plurality of first traces and signal ports electrically connected to the first traces in a one-to-one correspondence, and the signal ports are used to receive or output test signals.

[0007] Adjacent test pins are electrically isolated from each other.

[0008] Optionally, at least one test pin among the plurality of test pins receives a high-frequency signal during testing, and / or the test signal is used to perform an electrical test on a gate drive circuit in the display panel.

[0009] Optionally, the flexible circuit board includes a plurality of first pads, a plurality of second pads, and a plurality of second traces, and the number of the first pads, the second pads, and the second traces are equal.

[0010] A first end of the second trace is electrically connected to the first pad, and a second end is electrically connected to the test pin.

[0011] The second pad is electrically connected to an end of the first trace that is not electrically connected to the signal port, and the first pad is electrically isolated from the second pad.

[0012] Optionally, the flexible circuit board includes a first conductive layer and a second conductive layer.

[0013] The first pad and the second pad are located on the first conductive layer or the first pad and the second pad are located on the second conductive layer.

[0014] Optionally, a distance between a first pad and a second pad connected to a first trace and a second trace that receive a same test signal is in a range of 0.12 mm to 0.5 mm.

[0015] Optionally, the flexible circuit board includes a main circuit board and an auxiliary circuit board.

[0016] The main circuit board and the auxiliary circuit board are electrically isolated, and

[0017] The test pin and the test network are arranged on the auxiliary circuit board, and one end of the first trace that is not electrically connected to the signal port is electrically connected to the corresponding test pin.

[0018] Optionally, the first pin electrically connected to the test pin is located on one side of other first pins except the first pin electrically connected to the test pin.

[0019] Optionally, the auxiliary circuit board includes a plurality of second traces electrically connected to the first traces in a one-to-one correspondence, and the auxiliary circuit board includes a plurality of conductive layers.

[0020] The corresponding electrically connected first routing lines and the second routing lines are located in the same conductive layer, and two adjacent first routing lines and / or two adjacent second routing lines are located in different conductive layers.

[0021] Optionally, the flexible circuit board includes a first area and a second area.

[0022] The first region includes a first conductive layer, a second conductive layer, and a first insulating layer located between the first conductive layer and the second conductive layer, and the second region includes a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, and a third conductive layer stacked in sequence.

[0023] The test network is arranged in the second area, and one end of the first trace that is not electrically connected to the signal port is electrically connected to the corresponding second pin.

[0024] Optionally, the second pin is arranged on the first conductive layer, and the test network is arranged on the third conductive layer.

[0025] The second region further includes a plurality of via holes and conductive portions disposed in the via holes.

[0026] The via hole penetrates from the surface of the first insulating layer close to the first conductive layer to the surface of the second insulating layer away from the first conductive layer, and the test pin is electrically connected to the first trace through the conductive portion.

[0027] The flexible circuit board also includes a third trace electrically connected to the other second pins except the test pin, and the orthographic projection of the via hole in the first insulating layer does not overlap with the orthographic projection of the third trace in the first insulating layer.

[0028] Optionally, the second area includes: a row of the vias and at least two rows of the signal ports,

[0029] The arrangement directions of the plurality of vias and the signal ports in each row of signal ports are substantially the same,

[0030] The test network further includes a plurality of fourth traces electrically connected to the vias in a one-to-one correspondence, and the fourth traces having one end electrically connected to an adjacent via and the other end electrically connected to the signal ports located in different rows.

[0031] A second aspect of the present disclosure provides a display device comprising the display module described above.

[0032] The beneficial effects of the present disclosure are as follows:

[0033] In response to the current existing problems, the present disclosure develops a display module and a display device, and provides a plurality of second pins electrically connected to the first pins in the display panel in a one-to-one correspondence. The plurality of second pins include test pins, and adjacent test pins are electrically isolated. Therefore, even if the test network is corroded after the signal endurance test, it will not affect the circuit structure in the display panel, thereby avoiding the occurrence of RB bright lines and G bright lines. At the same time, it can also improve the stability of the display module in extreme environments, and has broad application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0035] Figure 1 A schematic structural diagram of a display module according to an embodiment of the present disclosure is shown;

[0036] Figure 2 A schematic structural diagram illustrating a binding area of ​​a display panel in a display module according to an embodiment of the present disclosure is shown;

[0037] Figure 3 and Figure 4 A partial wiring diagram of a flexible circuit board in a display module during a reliability test according to an embodiment of the present disclosure is shown;

[0038] Figure 5 A partial wiring diagram of a flexible circuit board in a display module according to another embodiment of the present disclosure is shown;

[0039] Figure 6 A schematic structural diagram of a display module according to another embodiment of the present disclosure is shown;

[0040] Figure 7 A schematic structural diagram of a display module according to another embodiment of the present disclosure is shown;

[0041] Figure 8 Show Figure 7 A partial cross-sectional schematic diagram of the embodiment shown;

[0042] Figure 9 A partial wiring diagram of a flexible circuit board in a display module according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0043] To more clearly illustrate the present disclosure, the present disclosure is further described below in conjunction with preferred embodiments and accompanying drawings. Similar components in the accompanying drawings are represented by the same or similar reference numerals. Those skilled in the art should understand that the specific description below is illustrative rather than restrictive and should not be used to limit the scope of protection of the present disclosure.

[0044] It should be noted that the terms “having”, “including”, “comprising”, etc. described in the present disclosure are all open-ended, that is, when describing a module as “having”, “including” or “comprising” a first element, a second element and / or a third element, it means that the module includes other elements in addition to the first element, the second element and / or the third element. In addition, ordinal numbers such as “first”, “second” and “third” in the present disclosure are not intended to limit a specific order, but are only used to distinguish between various parts. In the present disclosure, when describing layer A and layer B as “set on the same layer”, it means that layer A and layer B are made of the same material and the same process.

[0045] The inventors discovered that display products exhibited X-horizontal RB bright lines and Y-vertical G bright lines after undergoing an 85 / 85 signal tolerance test. A series of analyses revealed that in these defective display products, a short circuit occurred between the signal lines GCK and GND, and between the signal lines NCB and NOUT, used for electrical testing on the flexible circuit board electrically connected to the display panel. The GCK, NCB, and NOUT lines are all traces in the test network for the gate driver on array (GOA) circuit in the display module. The GCK and NCB lines are clock signal lines in the GOA test network, the NOUT line is the output signal line of the GOA test network, and the GND line is the ground signal line. The signals received by these signal lines are also high-frequency signals. Among them, the abnormality of the signal line GCK causes the vertical G bright line on the right side of the display panel, and the signal line NCB affects the signal line NOUT, resulting in the horizontal RB bright line. X-ray inspection found that the signal line GCK / GCB wiring has varying degrees of corrosion. Other GOA signal lines also have varying degrees of corrosion and a greater corrosion risk.

[0046] Further research revealed that the display panel is typically electrically connected to corresponding pins on the flexible circuit board via pins in the binding area. The flexible circuit board contains test network traces for GOA testing. These traces receive external test signals and transmit them via the test pins on the flexible circuit board to the pins in the binding area, where they are fed into the GOA on the display panel for electrical testing. This indicates that the pins used for GOA testing include one or more groups of adjacent pins. Since the pins are set adjacent to each other, the wiring layout of the test network connected to them is very tight; not only the signal lines GCK, signal line NCB, and signal line NCB in the GOA test network are high-frequency signal lines, but other signal lines in the GOA test network are also high-frequency signal lines. The output waveforms of these signal lines can reach a voltage difference of more than 14V. During the signal endurance test experiment, since the flexible circuit board runs in a high temperature and high humidity environment for a long time, the signal line receives a high-frequency signal with a large voltage difference for a long time, resulting in the GOA test network being the most susceptible to corrosion in the entire display module. As a result, the GOA test network in the display module after the signal endurance test has a corrosion short circuit, resulting in X horizontal RB bright line and Y vertical G bright line defects.

[0047] In addition, except for the GOA test network in the LTPO display panel, the GOA test networks in other types of display panels also have the problem of poor RB bright lines and G bright lines, although the specific signals are different, because they also have the characteristics of adjacent pins, high-frequency signals and large voltage differences.

[0048] In order to solve at least one of the above problems, an embodiment of the present disclosure provides a display module, comprising: a display panel and a flexible circuit board electrically connected to the display panel,

[0049] The display panel includes a plurality of first pins, the flexible circuit board includes a plurality of second pins, the plurality of first pins and the plurality of second pins are electrically connected in a one-to-one correspondence, and the plurality of second pins include a plurality of test pins arranged adjacent to each other.

[0050] The flexible circuit board also includes a test network, which includes a plurality of first traces and signal ports electrically connected to the first traces in a one-to-one correspondence, and the signal ports are used to receive or output test signals.

[0051] Adjacent test pins are electrically isolated from each other.

[0052] In this embodiment, by providing multiple second pins that are electrically connected one-to-one with the first pins in the display panel, the multiple second pins include test pins and a test network, and adjacent test pins are electrically isolated. Therefore, even if the test network is corroded after the signal endurance test, it will not affect the circuit structure in the display panel, thereby avoiding the occurrence of RB bright lines and G bright lines, and at the same time, it can improve the stability of the display module in extreme environments.

[0053] The display module of the embodiment of the present disclosure is described in detail below with reference to specific examples.

[0054] In a specific example, refer to Figure 1 As shown, the display module includes a display panel 1 and a flexible circuit board 2 electrically connected to the display panel 1. The display panel 1 includes a plurality of first pins 11, and the flexible circuit board 2 includes a plurality of second pins 21 electrically connected to the plurality of first pins 11 in a one-to-one correspondence. The plurality of second pins 21 include a plurality of test pins 21-1 arranged adjacent to each other.

[0055] In the embodiment of the present disclosure, the plurality of second pins 21 include a plurality of test pins 21-1 arranged adjacently, which means that there are test pins arranged adjacently among the plurality of second pins 21, and is not intended to limit the test pins to be adjacent to each other. That is, the test pins of the embodiment of the present disclosure include Figure 1 That is, there may be multiple groups of test pins in the second pin 21, for example Figure 1 As shown, the first group of test pins 21-1 (black-filled rectangles) arranged on the left and the second group of test pins 21-1 arranged on the right are not arranged adjacent to each other, but the test pins in the first group of test pins 21-1 are arranged adjacent to each other and the test pins in the second group of test pins 21-1 (black-filled rectangles) are arranged adjacent to each other.

[0056] Reference Figure 2 As shown, since the second pins 21 are arranged in a one-to-one correspondence with the first pins 11 , the first pins 11 electrically connected to the test pin 21 - 1 are also divided into two groups.

[0057] Continue to refer to Figure 1 As shown, the flexible circuit board 2 also includes a test network 22 corresponding to the multiple test pins 21-1 arranged adjacently. The test network includes multiple first traces 221 and signal ports 222 electrically connected to the first traces 221 in a one-to-one correspondence. The signal ports 222 are used to receive or output test signals. The test signals received by the signal ports 222 refer to, for example, various clock signals, power signals, etc. The test signals output by the signal ports 222 refer to, for example, feedback test output signals. The above test signals are all used to perform electrical tests on the response circuit module in the display panel. Figure 1 The example shown includes two groups of multiple test pins 21 - 1 arranged adjacent to each other, and correspondingly also includes two groups of test networks 22 .

[0058] Of course, the number of groups of multiple test pins arranged adjacent to each other in the embodiment of the present disclosure is not limited to Figure 1 The two groups shown are not intended to limit the number of test networks to two groups, and the specific setting method depends on the design requirements of the actual product.

[0059] In particular, in the embodiment of the present disclosure, adjacent test pins 21 - 1 are electrically isolated from each other. Optionally, at least one of the plurality of test pins receives a high-frequency signal during testing, and / or the test signal is used to perform an electrical test on the gate drive circuit in the display panel 1 .

[0060] Through this arrangement, for the second pin 21-1 that receives high-frequency signals in display module testing processes such as signal endurance testing, or for the second pin 21-1 used to test the gate drive circuit in display module testing processes such as signal endurance testing, even if the signal line transmitting high-voltage and high-frequency signals has undergone reliability corrosion after being exposed to a high-temperature and high-humidity environment for a long time, since the test pin can be kept electrically isolated, the related circuit modules of the display panel can also be protected from the effects of corrosion, thereby avoiding poor display of RB bright lines and G bright lines and improving the stability of the display panel under extreme conditions.

[0061] Specifically in this example, refer to Figure 1As shown, the flexible circuit board 2 includes a plurality of first pads 23, a plurality of second pads 24, and a plurality of second traces 25. The number of first pads 23, second pads 24, and second traces 25 is equal. Specifically, a first end of the second trace 25 is electrically connected to the first pad 23, and a second end is electrically connected to the test pin 21-1. The second pad 24 is electrically connected to the end of the first trace 221 that is not electrically connected to the signal port 222. The first pad 23 and the second pad 24 are electrically isolated.

[0062] In this embodiment, by providing an electrically isolated first solder pad 23 and a second solder pad 24, it is ensured that each test pin 21-1 and its corresponding first trace 221 are electrically isolated, so that when any first trace 221 in the test network 22 is corroded after the signal endurance test and causes a short circuit between the first traces 221, the test pins 21-1 can always be electrically isolated, thereby preventing the relevant circuit modules of the display panel from being affected by corrosion, improving the signal quality in the flexible circuit board 2, and avoiding the occurrence of poor display of RB bright lines and G bright lines. In addition, by providing an electrically isolated first solder pad 23 and a second solder pad 24 to isolate the test pin 21-1 from the corresponding test network, the stability of the display panel under extreme conditions during use can also be improved.

[0063] Optionally, the first pad 23 and the second pad 24 together form a pad for a resistor. During a signal-tolerance test, the first pad 23 and the second pad 24 are used to carry a resistance of 0Ω, thereby electrically connecting the corresponding first trace 221, the second pad 24, the first pad 23, the second trace 25, and the test pin 21-1. During mass production, this resistor is not installed, thereby electrically isolating the test pins 21-1.

[0064] Through this setting, during the signal endurance test, the signal port 222 electrically connected via the first trace 221 receives the test signal and transmits it to the test pin 21-1 via the path formed by the second pad 24, the resistor, the first pad 23, and the second trace 25, and then transmits it to the corresponding circuit to be tested in the display panel 1 via the electrical connection between the test pin 21-1 and the first pin 11, or the self-test signal pin 21-1 obtained by the test is output to the signal port 222 via the path formed by the second trace 25, the first pad 23, the resistor, and the second pad 24, and the high-frequency test signal is connected through the signal port 222 and the signal waveform is detected at the corresponding signal port, thereby helping to debug the circuit in the display panel (for example, GOA).

[0065] Optionally, considering the manufacturing process of the mounted resistor, the first pad 23 and the second pad 24 should be in the same conductive layer.

[0066] Specifically, the flexible circuit board 2 includes a first conductive layer and a second conductive layer, and the first pads 23 and the second pads 24 are located on the first conductive layer or the first pads and the second pads are located on the second conductive layer.

[0067] In addition, refer to Figure 1 As shown, the distance a between the first pad 23 and the second pad 24 is limited by the package size of the resistor used.

[0068] Optionally, in order to save the space occupied by the first pad 23, the second pad 24 and the resistor to be mounted thereon, the resistor should be a chip resistor. For example, the resistor can be a 0201 package resistor with a smaller package size. In order to ensure a better mounting effect than a conventional 0201 package resistor, the distance between the first pad and the second pad connected to the first trace and the second trace corresponding to receiving the same test signal can be in the range of 0.12mm-0.5mm. For example, the distance a between the first pad 23 and the second pad 24 can be 0.12mm-0.26mm, so as to meet the package size of Panasonic's 0201 package chip resistor, or the distance a between the first pad 23 and the second pad 24 can be 0.27mm-0.5mm, so as to meet the package size of KEMET's 0201 package chip resistor.

[0069] Of course, the above size range is only exemplary and not intended to be limiting. When using 0201 package chip resistors from other companies, or using chip resistors in other large-size packages if space permits, the distance a between the first pad 23 and the second pad 24 will meet other ranges.

[0070] Figure 3 The structure of the flexible circuit board in this embodiment that is electrically isolated by using the first pad and the second pad is shown by a partial wiring diagram of an exemplary flexible display module. Figure 4 Exemplary Figure 3 The flexible circuit board in the signal endurance test uses the structure after the first pad and the second pad are connected to each other for signal communication.

[0071] It should be noted that, for clarity, Figure 3 and Figure 4 The figure only shows a group of first solder pads 23 and second solder pads 24 and the circuit connection relationship formed by the group of first solder pads 23 and second solder pads 24 by way of example, but the present application is not intended to be limited to this. In actual application, the number of first solder pads 23 and second solder pads 24 depends on the number of test pins 21-1 that need to be electrically isolated, which will not be elaborated in this article.

[0072] Specifically for this example, Figure 3As can be seen, the yellow bright line and block in the figure mark a test pin 21-1, and the second trace 25 and the first pad 23 electrically connected thereto. Figure 3 As can be seen in the figure, the first pad 23 and the second pad 24 are conventional square pads for carrying resistors. At this time, there is no resistor between the first pad 23 and the second pad 24, and the test pin 21-1 is electrically isolated from the corresponding first trace 221 and the signal port 222 by utilizing the electrically isolated first pad 23 and the second pad 24.

[0073] in addition, Figure 3 The figure also shows other first traces 221 and second traces 222 of the test network. It should be understood by those skilled in the art that, although not shown in the screenshot, these first traces 221 and second traces 222 also have first pads 23 and 24 arranged in a one-to-one correspondence. Figure 3 Also shown are larger signal ports FOP_TEST_L1 and FOP_TEST_L2, which are used for testing other circuit modules in the display module and will not be described in detail herein.

[0074] Reference Figure 4 As shown in the figure, the circuit structure with electrical connection relationship is marked with yellow bright lines and blocks. Figure 4 As can be seen in the figure, the first pad 23 and the second pad 24 are conventional square pads for carrying resistors. After a 0Ω resistor is installed between the first pad 23 and the second pad 24, it is in the signal endurance test stage. The test pin 21-1 forms an electrical path by electrically connecting the first pad 23 and the second pad 24 electrically connected by the resistor and the corresponding first trace 221 and the signal port 222, so that the path can be used to receive the test signal or output the test signal to complete the signal endurance test of the corresponding circuit structure in the display panel 1.

[0075] More preferably, refer to Figure 4 As shown, the flexible circuit board 2 also includes a component area (such as Figure 4 The component area includes a plurality of components, which are electrically connected to other second pins through signal lines. The first soldering pad 23 and the second soldering pad 24 should be arranged on the side of the component area close to the second pin 21, or the first soldering pad 23 and the second soldering pad 24 should be arranged between the component area and the second pin 21, that is, the first soldering pad 23 and the second soldering pad 24 should be arranged as close to the second pin 21 as possible. Such an arrangement can maximize the blocking of the influence of the GOA test circuit on the circuit in the display panel.

[0076] This approach achieves electrical isolation between all first traces 221 and all test pins 21-1, thereby preventing the impact of corroded and short-circuited first traces 221 on test pins 21-1. This, in turn, prevents display defects such as RB and G bright lines on the display panel 1. It also enhances the electromagnetic compatibility of the flexible circuit board against static electricity and radio frequency interference. Furthermore, this structural approach protects the display panel's display function without affecting the signal endurance testing function. Furthermore, by simply providing two solder pads between the electrically connected traces on top of the existing structure, the structure is simple, requiring minimal modifications compared to existing structures and not significantly increasing design and production costs.

[0077] Alternatively, the first and second pads 23, 24 are not used to carry resistors, but rather form a closely spaced pad group. During reliability testing, these pads 23, 24 are short-circuited during reflow soldering by opening windows above them during the packaging process (e.g., coverlay). A conductive layer, such as solder paste, is then printed during the surface mount technology (SMT) process. This allows the first and second pads 23, 24 to be short-circuited together, thereby electrically connecting the corresponding first trace 221, second pad 24, first pad 23, second trace 25, and test pin 21-1. During mass production, the coverlay or ink coating over the pad group can be eliminated, and the conductive layer, such as solder paste, can be omitted during the SMT process to electrically isolate the test pins 21-1.

[0078] Through this setting, during the signal endurance test, the signal port 222 electrically connected via the first trace 221 receives the test signal and transmits it to the test pin 21-1 via the path formed by the second pad 24, the first pad 23, and the second trace 25, and then transmits it to the corresponding circuit to be tested in the display panel 1 via the electrical connection between the test pin 21-1 and the first pin 11, or the self-test signal pin 21-1 obtained by the test is output to the signal port 222 via the path formed by the second trace 25, the first pad 23, and the second pad 24, and the high-frequency test signal is connected through the signal port 222 and the signal waveform is detected at the corresponding signal port, thereby helping to debug the circuit in the display panel (for example, GOA).

[0079] It is also worth mentioning that in this example, no resistors are required during the endurance test phase, which is less expensive than a structure with resistors.

[0080] In this example, the specific connection method of the electrical isolation and point connection between the test network 22 and the test pin 21-1 through the pad group composed of the first pad 23 and the second pad 24 is the same as Figure 3 and Figure 4 The method shown in is similar and will not be repeated here.

[0081] Figure 5 Another example of local wiring of a flexible circuit board that satisfies the pad group structure is shown.

[0082] Reference Figure 5 As shown, unlike the pad structure equipped with resistors, when a pad group structure without resistors is adopted, the shapes of the first pad 23 and the second pad 24 do not have to be limited to the resistor package, that is, during the design, the first pad 23 and the second pad 24 can be in various shapes.

[0083] It should be noted that the first pad 23 and the second pad 24 serve as a pad group for electrically isolating the test network 22 from the test pad 21-1 to protect the circuit structure in the display panel 1. Therefore, the distance a between the first pad 23 and the second pad 24 should be able to effectively provide electrical isolation protection. Therefore, the distance between the first pad 23 and the second pad 24 should be greater than the minimum process dimension of the patterning, that is, the distance a between the first pad 23 and the second pad 24 should be greater than or equal to 0.1 mm.

[0084] In addition, considering the manufacturing process, in order to form an effective short-circuit connection through the printed conductive layer during the surface mount process (SMT) and reflow soldering, the distance between the first pad 23 and the second pad 24 should be as close as possible.

[0085] Of course, also considering the manufacturing process, the first pad 23 and the second pad 24 should be on the same conductive layer. Specifically, the flexible circuit board 2 includes a first conductive layer and a second conductive layer, and the first pad 23 and the second pad 24 are located in the first conductive layer or the first pad 23 and the second pad 24 are located in the second conductive layer.

[0086] In some other optional embodiments, referring to Figure 6 As shown, the flexible circuit board electrically connected to the display panel 1 includes a main circuit board 2 - 1 and an auxiliary circuit board 2 - 2 .

[0087] The main circuit board 2-1 and the auxiliary circuit board 2-2 are electrically isolated, meaning they are two independently configured circuit boards. The display panel 1 includes a plurality of first pins 11', and the flexible circuit board includes a plurality of second pins 21' corresponding to the plurality of first pins 11'. The plurality of second pins 21' include a plurality of adjacent test pins 21-1'. A test network 22' corresponding to the test pins 21-1' and the test pins 21' is provided on the auxiliary circuit board 2-2.

[0088] The test network 22' includes a plurality of first traces 221 and signal ports 222 electrically connected to the first traces 221 in a one-to-one correspondence. One end of the first trace 222 not electrically connected to the signal port 222 is electrically connected to the corresponding test pin 21-1'.

[0089] Specifically, refer to Figure 6 As shown, the first pin 11-1' electrically connected to the test pin 21-1' is located on one side of other first pins 11' except the first pin 11-1' electrically connected to the test pin 21-1', so that all test networks related to the test pin 21-1' are conveniently set on the auxiliary circuit board 2-2.

[0090] It should be noted that Figure 6 The components and wiring in the main circuit board 2 - 1 are omitted. Those skilled in the art will understand that the main circuit board 2 - 1 includes the components and wiring required for display and / or touch control of the display panel 1 .

[0091] Through the above arrangement, by utilizing an independent auxiliary circuit board 2-2 to separately establish a test network 22' associated with an adjacent test pin 21-1', it is possible to directly and physically isolate the wiring that provides the various signals required for normal display to the display panel 1 from the test network 22' that provides high-frequency signals and / or test signals for GOA testing. Furthermore, by providing a separately provided auxiliary circuit board 2-2, the wiring space for the test network 22' is directly increased. This ensures that even if a first trace 221 in the test network 22' corrodes under the high temperature and high humidity conditions of the signal endurance test, it will not short-circuit with other adjacent first traces 221. Consequently, even when the other end of the first trace 221 is electrically connected to the test pin 21-1', the test pin 21-1' in the display module remains electrically isolated, thereby preventing display defects such as RB bright lines and G bright lines on the display panel 1. Furthermore, this arrangement ensures product stability when the display module is used in extreme environments.

[0092] It is worth mentioning that, in this embodiment, the flexible circuit board hole plate of the display module in the reliability testing stage and the display module in the mass production stage is the same, which reduces the difficulty of the preparation process and reduces the process cost.

[0093] Reference Figure 6 As shown, since the test networks 22' are all arranged on the auxiliary circuit board 2-2, the wiring space in the auxiliary circuit board 2-2 is freer.

[0094] Alternatively, as Figure 6As shown in , the auxiliary circuit board 2-2 also includes a plurality of second traces 25 electrically connected to the first traces 221 in a one-to-one correspondence. One end of each second trace 25 is electrically connected to the end of the first trace 221 that is not electrically connected to the signal port 222, and the other end is electrically connected to the test pin 21-1'. The auxiliary circuit board 2-2 includes multiple conductive layers, wherein the corresponding electrically connected first traces and second traces are located on the same conductive layer, and two adjacent first traces and / or two adjacent second traces are located on different conductive layers.

[0095] Exemplarily, the second trace 25 includes a trace 25-1 electrically connected to the 2n-1th test pin 21-1' and a trace 25-2 electrically connected to the 2n-th test pin 21-1', and the first trace 221 includes a first trace 221-1 electrically connected to the trace 25-1 and a first trace 221-2 electrically connected to the trace 25-2. The auxiliary circuit board 2-2 includes a first conductive layer, a second conductive layer, and an insulating layer disposed between the first conductive layer and the second conductive layer. The trace 25-1 and the first trace 221-1 are disposed on the first conductive layer, and the trace 25-2 and the first trace 221-2 are disposed on the second conductive layer. At the same time, the signal ports 222 can also be arranged in at least two rows, with the first trace 221-1 electrically connected to the signal ports 222 in the even-numbered rows and the first trace 221-2 electrically connected to the signal ports 222 in the odd-numbered rows, where n is an integer greater than or equal to 1. Of course, the first trace 221-1 can also be electrically connected to the even-numbered rows of signal ports 222, and the first trace 221-2 can also be electrically connected to the even-numbered rows of signal ports 222. Of course, this is only exemplary, and odd-numbered traces can also be electrically connected to even-numbered rows of signal ports.

[0096] Through the above arrangement, the spatial flexibility of the auxiliary circuit board 2 - 2 can be fully utilized, the wiring distance between adjacent test pins 21 - 1 ′ can be increased, and the electrical isolation between adjacent test pins 21 - 1 ′ can be ensured.

[0097] Figure 7 and Figure 8 Another optional embodiment is provided, which differs from the embodiment described above in that the flexible circuit board includes a first area 2-1 and a second area 2-2, the first area 2-1 includes a first conductive layer L11, a second conductive layer L12 and a first insulating layer L21 located between the first conductive layer L11 and the second conductive layer L12, the second area 2-2 includes a first conductive layer L11, a first insulating layer L21, a second conductive layer L12, a second insulating layer L22, and a third conductive layer L13 stacked in sequence, the test network is arranged in the second area 2-2, and the end of the first trace 221 that is not electrically connected to the signal port is electrically connected to the corresponding second pin 21-1.

[0098] In this embodiment, a wiring layer is added to a local area of ​​the flexible circuit board and a test network is placed in this local area. The test network, which is susceptible to corrosion and short circuits during the signal endurance test, is placed in the added wiring layer. The increased wiring space provided by the additional wiring layer is then utilized to increase the spacing between the first traces in the test network. As a result, even if corrosion occurs in the first traces of the test network after the signal endurance test, short circuits between adjacent traces will not occur. This electrically isolates adjacent test pins in the display module, thereby preventing display defects such as RB and G bright lines from occurring in display panel 1. This arrangement also enhances the flexible circuit board's anti-static and electromagnetic compatibility against radio frequency interference, ensuring product stability when the display module is used in extreme environments.

[0099] It's also worth noting that in this embodiment, the display module used in the reliability testing phase uses the same flexible printed circuit board perforations as the display module used in mass production, reducing both manufacturing complexity and costs. Furthermore, the layout of the first pins associated with the test network does not need to be re-arranged. This structure does not affect the layout and wiring of the display panel 1, thereby reducing design costs.

[0100] Optionally, combined Figure 8 and Figure 9 As shown, the second pin 21 is set in the first conductive layer L11, the test network is set in the third conductive layer L13, the second area 2-2 also includes a plurality of vias TK and a conductive portion set in the via TK, the via TK passes through the surface of the first insulating layer L1 close to the first conductive layer L1 to the surface of the second insulating layer L22 away from the first conductive layer L11, the test pin 21-1 is electrically connected to the first trace 221 via the conductive portion, the flexible circuit board also includes a third trace 26, the third trace 26 is electrically connected to the other second pins 21 except the test pin 21-1, and the orthographic projection of the via TK in the first insulating layer L21 does not overlap with the orthographic projection of the third trace 26 in the first insulating layer L21.

[0101] This configuration ensures that the conductive portion in the via TK avoids the third trace 26 , thereby ensuring that the test network does not interfere with the circuit structure in the display panel 1 .

[0102] Further optionally, referring to Figure 9 As shown, in order to increase the wiring space of the test network by using the conductive layer added in the longitudinal direction, thereby increasing the spacing between the first traces 221, the second area 2-2 ( Figure 9The area enclosed in green (in the middle) includes a row of vias TK and two rows of signal ports 222. The number of signal ports 222 can be greater than two rows. The vias TK and the signal ports 222 in each row are arranged in substantially the same direction. The test network also includes a plurality of fourth traces 223 electrically connected to each of the vias TK. Each fourth trace 223, one end of which is electrically connected to an adjacent via TK, has its other end electrically connected to a signal port 222 in a different row.

[0103] Specific to Figure 9 In the example of , the test network further includes a plurality of fourth traces 223 electrically connected to the vias TK in a one-to-one correspondence, wherein the fourth trace 223 having one end electrically connected to the 2n-1th via is electrically connected to the signal port 222 of the odd-numbered row at the other end, and the fourth trace 223 having one end electrically connected to the 2n-th via is electrically connected to the signal port 222 of the other of the even-numbered row of the second row at the other end, where n is an integer greater than or equal to 1. Of course, the order in which the fourth traces 223 are connected to the odd-numbered rows and the even-numbered rows can be reversed, that is, the fourth trace 223 having one end electrically connected to the 2n-1th via is electrically connected to the signal port 222 of the even-numbered row at the other end, and the fourth trace 223 having one end electrically connected to the 2n-th via is electrically connected to the signal port 222 of the odd-numbered row at the other end.

[0104] Further references Figure 9 As shown, specifically, the second area 2-2 in the example in the figure includes a test network for two groups of GOA electrical tests. Among them, the mark in the signal port 222 represents the signal received or output by the signal port 222. Figure 9 As shown, one group of signal ports 222 for electrical testing of GOA includes an output port EOUT, a first clock port ECB, a second clock port ECX, and an initial signal port HSTV, while another group of signal ports 222 for electrical testing of GOA includes an output port GOUT, a first clock port CLK1, a second clock port HCB, and an initial signal port HSTV. Of course, the naming of the signal ports is merely exemplary and is not intended to be limiting. Figure 9 Also shown are signal lines corresponding to other second pins except the test pin 21-1, for example, ELVSS represents a signal line providing a low-level power signal, ELVDD represents a signal line providing a high-level power signal, and GND represents a ground line. Of course, this is only exemplary, and the laying method of these signal lines may be different for different examples.

[0105] Corresponding to the display module in the above embodiment that uses the first pad 23 and the second pad 24 to electrically isolate the test network from the test pin 21-1, the testing method of the display module may specifically include: electrically connecting the first pad and the second pad one by one, and electrically testing the display panel by inputting or outputting the test signal through the signal port.

[0106] Optionally, electrically connecting the first pad and the second pad in a one-to-one correspondence includes: mounting a zero-resistance resistor between the first pad and the second pad.

[0107] Specifically, during the debugging stage of the display module, a zero-resistance chip resistor is welded or bound between the first pad and the second pad. The chip resistor can be a chip resistor with a 0201 packaging process, or other chip resistors that meet the packaging design dimensions of the first pad and the second pad.

[0108] Alternatively, electrically connecting the first pad and the second pad in a one-to-one correspondence includes: opening a plurality of windows in the display module, each window exposing the first pad, the second pad, and the area between the first pad and the second pad to be electrically connected, and coating a metal layer in the windows.

[0109] Specifically, during the sample debugging stage, an overlay window is made above the first pad and the second pad. The window needs to expose the two pads and the area between them at the same time. During the SMT process, solder paste is printed upward. During reflow soldering, the solder paste is short-circuited due to the close distance, thereby forming an electrical connection between the first pad and the second pad.

[0110] Through the above settings, the test network is isolated by using the first and second pads, which ensures the stability of the display module while meeting the signal endurance test, improves the display effect, and extends the product life. At the same time, the anti-static and electromagnetic compatibility of the flexible circuit board with respect to radio frequency interference is enhanced, and the stability of the power line / signal line in certain extreme environments is improved.

[0111] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, which implements the display module described above.

[0112] Since the display module included in the display device provided in the embodiment of the present disclosure corresponds to the display modules provided in the above-mentioned embodiments, the previous implementation is also applicable to the usage method provided in this embodiment and will not be described in detail in this embodiment.

[0113] In this embodiment, the display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, car display, digital photo frame or navigation system. By loading the above display module, the display device can avoid poor display and improve product stability and life.

[0114] Obviously, the above embodiments of the present disclosure are merely examples for clearly illustrating the present disclosure, and are not intended to limit the implementation methods of the present disclosure. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is impossible to list all the implementation methods here. All obvious changes or modifications derived from the technical solutions of the present disclosure are still within the scope of protection of the present disclosure.

Claims

1. A display module, characterized in that: include: a display panel and a flexible circuit board electrically connected to the display panel, The display panel includes a plurality of first pins, the flexible circuit board includes a plurality of second pins, the plurality of first pins and the plurality of second pins are electrically connected in a one-to-one correspondence, and the plurality of second pins include a plurality of test pins arranged adjacent to each other. The flexible circuit board further includes a test network corresponding to the plurality of test pins, the test network including a plurality of first traces and signal ports electrically connected to the first traces in a one-to-one correspondence, the signal ports being used to receive or output test signals. Wherein, adjacent test pins are electrically isolated from each other.

2. The display module according to claim 1, wherein: At least one test pin among the plurality of test pins receives a high-frequency signal during testing, and / or the test signal is used to perform an electrical test on a gate drive circuit in the display panel.

3. The display module according to claim 1, wherein: The flexible circuit board includes a plurality of first pads, a plurality of second pads, and a plurality of second traces, wherein the number of the first pads, the number of the second pads, and the number of the second traces are equal. A first end of the second trace is electrically connected to the first pad, and a second end is electrically connected to the test pin. The second pad is electrically connected to an end of the first trace that is not electrically connected to the signal port, and the first pad is electrically isolated from the second pad.

4. The display module according to claim 3, wherein: The flexible circuit board includes a first conductive layer and a second conductive layer. The first pad and the second pad are located in the first conductive layer, or the first pad and the second pad are located in the second conductive layer.

5. The display module according to claim 4, wherein: The distance between the first pad and the second pad connected to the first trace and the second trace that receive the same test signal is in the range of 0.12 mm to 0.5 mm.

6. The display module according to claim 1, wherein: The flexible circuit board includes a main circuit board and an auxiliary circuit board, wherein: The main circuit board and the auxiliary circuit board are electrically isolated, and The test pin and the test network are arranged on the auxiliary circuit board, and one end of the first trace that is not electrically connected to the signal port is electrically connected to the corresponding test pin.

7. The display module according to claim 6, wherein: The first pin electrically connected to the test pin is located on one side of the other first pins except the first pin electrically connected to the test pin.

8. The display module according to claim 6, wherein: The auxiliary circuit board includes a plurality of second traces electrically connected to the first traces in a one-to-one correspondence, and the auxiliary circuit board includes a plurality of conductive layers. The first routing lines and the second routing lines that are electrically connected to each other are located in the same conductive layer, and two adjacent first routing lines and / or two adjacent second routing lines are located in different conductive layers.

9. The display module according to claim 1, wherein: The flexible circuit board includes a first area and a second area. The first region includes a first conductive layer, a second conductive layer, and a first insulating layer located between the first conductive layer and the second conductive layer, and the second region includes the first conductive layer, the first insulating layer, the second conductive layer, the second insulating layer, and a third conductive layer stacked in sequence. The test network is arranged in the second area, and one end of the first trace that is not electrically connected to the signal port is electrically connected to the corresponding second pin.

10. The display module according to claim 9, wherein: The second pin is arranged on the first conductive layer, and the test network is arranged on the third conductive layer. The second region further includes a plurality of via holes and conductive parts disposed in the via holes. The via hole passes through from the surface of the first insulating layer close to the first conductive layer to the surface of the second insulating layer away from the first conductive layer, and the test pin is electrically connected to the first trace via the conductive portion. The flexible circuit board also includes a third trace, which is electrically connected to other second pins of the second pins except the test pin, and the orthographic projection of the via in the first insulating layer does not overlap with the orthographic projection of the third trace in the first insulating layer.

11. The display module according to claim 10, wherein: The second area includes: a row of the vias and at least two rows of the signal ports, The arrangement directions of the plurality of vias and the signal ports in each row of signal ports are substantially the same, The test network further includes a plurality of fourth traces electrically connected to the vias in a one-to-one correspondence, and the fourth traces having one end electrically connected to an adjacent via and the other end electrically connected to the signal ports located in different rows.

12. A display device, characterized in that: A display module comprising any one of claims 1-11.

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