Main control board based on optical port and PCIe transmission

Abstract

The utility model relates to the technical field of image data transmission, and discloses a main control board based on an optical port and PCIe transmission, the main control board is provided with the optical port, a PCIe interface, a DDR3 and an FPGA, and the optical port is used as a data input interface to be connected with the FPGA; the DDR3 is connected with the FPGA and is used for storing data input through the optical port; the PCIe interface serves as a data output interface to be connected with the FPGA and is used for outputting data in the DDR3. According to the scheme, the problem of cross-clock data conversion of the image data between the optical port and the PCIe is solved, conversion of the image data between the optical port and the PCIe interface is achieved under the condition that the optical port transmission rate and the PCIe rate are compatible, then efficient and real-time concurrent data transmission is achieved, and therefore the bottleneck problem of multi-camera image transmission is solved.

Description

Technical Field

[0001] The utility model relates to the technical field of image data transmission, in particular to a main control board based on optical port and PCIe transmission. Background Art

[0002] With the rapid development of digital image processing technology, multi-camera systems are becoming increasingly common in various applications such as autonomous driving, industrial inspection, medical imaging, and security monitoring. These systems often need to process large amounts of high-resolution image data, and how to efficiently transmit and process this data has become a key technology.

[0003] FPGAs, with their high concurrent processing capabilities and customizability, are an ideal choice for solving this problem. They enable real-time data processing and transmission, meeting high-performance, multi-tasking requirements. However, as the number and resolution of cameras increase, the need for data transmission bandwidth also increases, placing higher demands on system interface design. An efficient, real-time, concurrent data transmission system is needed to meet these requirements. Summary of the Invention

[0004] In order to solve the problems in the prior art, the purpose of the embodiment of the present utility model is to provide a main control board based on optical port and PCIe transmission, which can achieve efficient and real-time concurrent data transmission, thereby solving the bottleneck problem of multi-camera image transmission.

[0005] In order to achieve the above purpose, the embodiment of the present invention provides a main control board based on optical port and PCIe transmission, which is provided with optical port, PCIe interface, DDR3 and FPGA.

[0006] The optical port is connected to the FPGA as a data input interface;

[0007] The DDR3 is connected to the FPGA and is used to store data input through the optical port;

[0008] The PCIe interface is connected to the FPGA as a data output interface, and is used to output the data in the DDR3.

[0009] Preferably, the main control board is connected to the flying camera through the optical port for receiving image data from the flying camera; the main control board is connected to the host computer through the PCIe interface for outputting the image data.

[0010] Preferably, the FPGA has built-in optical port data writing DDR3 logic, PCIe reading DDR3 logic, flight camera image data control logic and MIG IP core, and the MIG IP core is connected to DDR3.

[0011] The optical port data writing DDR3 logic is connected to the optical port and the MIG IP core respectively, and is used to receive image data from the optical port and cooperate with the MIG IP to write the image data into the DDR3;

[0012] The PCIe read DDR3 logic is connected to the PCIe interface and the MIG IP core respectively, and is used to cooperate with the MIGIP to read the image data in the DDR3 and output the image data through the PCIe interface;

[0013] The flight camera image data control logic is respectively connected to the optical port data write DDR3 logic and the PCIe read DDR3 logic, and is used to realize the function of the optical port data write DDR3 logic to write the image data from the optical port into DDR3, and to realize the function of the PCIe read DDR3 logic to read the image data in DDR3 and output the image data through the PCIe interface.

[0014] Preferably, the FPGA has a built-in transceiver IP core, and the optical port data writing DDR3 logic cooperates with the transceiver IP core to realize the function of receiving image data from the optical port.

[0015] Preferably, the FPGA has a built-in AXI IP core, the optical port data write DDR3 logic and the PCIe read DDR3 logic are connected to the AXI IP core using an AXI4 bus, and the AXI IP core is connected to the MIG IP core using an AXI4 bus.

[0016] Preferably, the FPGA has a built-in XDMA, the PCIe DDR3 reading logic is connected to the XDMA using an AXI4 bus, and the XDMA is connected to the PCIe interface.

[0017] Preferably, an MSI interrupt is configured in the XDMA, which is used to send an interrupt to the host computer when the FPGA receives an image data, so as to notify the host computer that it can request an image.

[0018] Preferably, the clock frequency of the AXI4 bus is 125 MHz, the data bit width is 64 bits, and the address width is 64 bits; the channel width of the PCIe interface is X4, and the reference clock frequency is 100 MHz.

[0019] Preferably, the main control board is also provided with a clock circuit, including clock 1 and clock 2, and the clock 1 and clock 2 are respectively connected to the FPGA, the clock 1 is used to provide the clock required for the optical port to work, and the clock 2 is used to provide the clock required for the FPGA to work.

[0020] Preferably, the clock 1 is a differential clock with a frequency of 156.25 MHz; the clock 2 has a frequency of 40 MHz.

[0021] Through the above technical solution, the main control board combines the optical port control logic, PCIe control logic and image link control logic in the FPGA to implement an image link transmission solution based on the optical port and PCIe. This solves the problem of cross-clock data conversion between the optical port and PCIe. While being compatible with the optical port transmission rate and PCIe rate, it realizes the conversion of image data between the optical port and PCIe interface, thereby achieving efficient and real-time concurrent data transmission, thereby solving the bottleneck problem of multi-camera image transmission.

[0022] Other features and advantages of the embodiments of the present invention will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following detailed description, they are used to explain the embodiments of the present invention, but do not constitute a limitation of the embodiments of the present invention. In the accompanying drawings:

[0024] Figure 1 This is a schematic diagram of the structure of the main control board of the utility model;

[0025] Figure 2 This is a schematic diagram of the FPGA structure of the utility model. DETAILED DESCRIPTION

[0026] The following describes the specific implementation of the embodiment of the present invention in detail with reference to the accompanying drawings. It should be understood that the specific implementation described herein is only used to illustrate and explain the embodiment of the present invention and is not intended to limit the embodiment of the present invention.

[0027] The embodiment of the utility model proposes a main control board based on optical port and PCIe transmission, such as Figure 1 As shown, the main control board is provided with an optical port, a PCIe interface, a DDR3 and an FPGA. The optical port is connected to the FPGA as a data input interface; the DDR3 is connected to the FPGA for storing data input through the optical port; the PCIe interface is connected to the FPGA as a data output interface for outputting the data in the DDR3.

[0028] Furthermore, the main control board is connected to the flying camera through the optical port for receiving image data from the flying camera; the main control board is connected to the host computer through the PCIe interface for outputting the image data.

[0029] The main control board receives image data from the flight camera board via the optical port and transmits it to a host computer, such as an industrial PC, via the PCIe interface. DDR3 is used to store image data and some control signals. The FPGA is the control core of the main control board, controlling the optical port, DDR3, and PCIe interface. By combining PCIe and optical interfaces, an efficient, real-time, concurrent data transmission system can be implemented, solving the bottleneck problem of multi-camera image transmission. This system not only improves data transmission speed and efficiency, but also ensures data integrity and real-time performance, meeting the requirements of various high-performance image processing applications.

[0030] Furthermore, the resources used by the link part of the main control board for flight camera image transmission are as follows: Figure 1 As shown, it includes two clocks: Clock 1 and Clock 2. Clock 1 is a differential clock with a frequency of 156.25 MHz, used to provide the clock required for the optical port operation. Clock 2 is a 40 MHz clock used to provide the clock required for the FPGA operation. The FPGA uses a PLL to generate clock signals of other frequencies for use by other logic.

[0031] Furthermore, in order to forward the image data of the flight camera board to the industrial computer, it is necessary to design FPGA control logic to control the optical port, PCIe interface and DDR3. Figure 2 As shown, the FPGA has built-in optical port data writing DDR3 logic, PCIe reading DDR3 logic, flight camera image data control logic and MIG IP core. The MIG IP core is connected to DDR3. The optical port data writing DDR3 logic is connected to the optical port and MIG IP core respectively, for receiving image data from the optical port and cooperating with the MIG IP to write image data into DDR3. The PCIe reading DDR3 logic is connected to the PCIe interface and MIG IP core respectively, for communicating with the MIG IP. The IP cooperates to realize reading the image data in DDR3 and outputting the image data through the PCIe interface; the flying camera image data control logic is respectively connected to the optical port data write DDR3 logic and the PCIe read DDR3 logic, so as to realize the function of the optical port data write DDR3 logic to read the image data from the optical port and write it into DDR3, and realize the function of the PCIe read DDR3 logic to read the image data in DDR3 and output the image data through the PCIe interface; the function implementation process of the optical port data write DDR3 logic and the PCIe read DDR3 logic is concurrent and does not interfere with each other.

[0032] Furthermore, if Figure 2As shown, the FPGA has a built-in transceiver IP core. The optical port data write DDR3 logic cooperates with the transceiver IP core to receive image data from the optical port. The FPGA also has a built-in AXI IP core. The optical port data write DDR3 logic and the PCIe DDR3 read logic are connected to the AXI IP core using the AXI4 bus, and the AXI IP core is connected to the MIG IP core using the AXI4 bus. The FPGA also has a built-in XDMA. The PCIe DDR3 read logic is connected to the XDMA using the AXI4 bus, and the XDMA is connected to the PCIe interface. An MSI interrupt is configured within the XDMA to send an interrupt to the host computer when the FPGA completes receiving image data, notifying the host computer that it can request an image. The AXI IP core uses the AXIInterconnect RTL.

[0033] The PCIe DDR3 read logic consists of two parts: one for acquiring IPC-related control signals and the other for reading and writing DDR3 logic. To acquire IPC control signals, the image link consists of three parts: the first part stores the image data's starting address and length; the second part requests the 0x00 address, indicating that the IPC has received an interrupt signal; and the third part requests the 0x10 address, indicating that the IPC has received all image data.

[0034] The PCIe interface uses XDMA to control access, implementing DMA principles to enable data access to the main control board and industrial computer. In the FPGA's image link, XDMA uses the AXI4 bus, which has a clock frequency of 125MHz, a data bit width of 64 bits, and a 64-bit address width. The PCIe interface has a channel width of X4 and a reference clock frequency of 100MHz. When the main control board receives an image from the flight camera board, it needs to send an interrupt to the industrial computer. Therefore, an MSI interrupt is configured in XDMA to notify the industrial computer that it can request image data. Image data requires a DMA read channel and a DMA write channel, requiring an additional C2H and H2C channels in XDMA.

[0035] The optical port data write logic for DDR3 includes a synchronous FIFO with a data width of 128 bits and a depth of 2048. This synchronous FIFO is responsible for buffering image data when the image data is valid. The optical port data write logic for DDR3 converts the image data into the AXI4 protocol and writes it to DDR3. It also exchanges signals with the flight camera board to receive image data.

[0036] Access to DDR3 requires the AXI4 protocol. The DDR3 control logic is implemented using the MIG IP core. The system clock is 200 MHz, the user clock is 200 MHz, and the DDR3 control clock is 800 MHz. The MIG IP core provides user access through the AXI4 interface, which operates at 200 MHz, with a 128-bit data width and a 64-bit address. Other modules within the FPGA connect to the AXI IP core via the AXI4 bus to access DDR3. DDR3 access by these modules is ultimately converted to accesses at 200 MHz, with a 128-bit data width and a 64-bit address.

[0037] In summary, the present invention's solution can write image data received from the optical port into DDR3 at a selectable bit width, allowing the industrial computer (host computer) to access the image data through the PCIe interface control designed in this solution. Ultimately, the main control board combines the optical port control logic, PCIe control logic, and image link control logic within the FPGA to implement an optical port- and PCIe-based image link transmission solution. This solves the problem of cross-clock data conversion between the optical port and PCIe. While maintaining compatibility between the optical port transmission rate and the PCIe rate, image data conversion between the optical port and PCIe interfaces is achieved, enabling efficient, real-time, and concurrent data transmission, thus resolving the bottleneck issue of multi-camera image transmission.

[0038] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements, but also other elements not expressly listed, or elements inherent to such process, method, commodity, or apparatus.

[0039] The above are merely embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should all be included within the scope of the claims of the present application.

Claims

1. A main control board based on optical port and PCIe transmission, characterized in that: The main control board is equipped with optical port, PCIe interface, DDR3 and FPGA. The optical port is connected to the FPGA as a data input interface; The DDR3 is connected to the FPGA and is used to store data input through the optical port; The PCIe interface is connected to the FPGA as a data output interface, and is used to output the data in the DDR3.

2. The main control board based on optical port and PCIe transmission according to claim 1, characterized in that: The main control board is connected to the flying camera through the optical port for receiving image data from the flying camera; the main control board is connected to the host computer through the PCIe interface for outputting the image data.

3. The main control board based on optical port and PCIe transmission according to claim 2, characterized in that: The FPGA has built-in optical port data writing DDR3 logic, PCIe reading DDR3 logic, flight camera image data control logic and MIG IP core, which is connected to DDR3. The optical port data writing DDR3 logic is connected to the optical port and the MIG IP core respectively, and is used to receive image data from the optical port and cooperate with the MIG IP to write the image data into the DDR3; The PCIe read DDR3 logic is connected to the PCIe interface and the MIG IP core respectively, and is used to cooperate with the MIG IP to read the image data in the DDR3 and output the image data through the PCIe interface; The flight camera image data control logic is respectively connected to the optical port data write DDR3 logic and the PCIe read DDR3 logic, and is used to realize the function of the optical port data write DDR3 logic to write the image data from the optical port into DDR3, and to realize the function of the PCIe read DDR3 logic to read the image data in DDR3 and output the image data through the PCIe interface.

4. The main control board based on optical port and PCIe transmission according to claim 3, characterized in that: The FPGA has a built-in transceiver IP core, and the optical port data writing DDR3 logic cooperates with the transceiver IP core to realize the function of receiving image data from the optical port.

5. The main control board based on optical port and PCIe transmission according to claim 3, characterized in that: The FPGA has a built-in AXI IP core. The optical port data write DDR3 logic and the PCIe read DDR3 logic are connected to the AXI IP core using an AXI4 bus. The AXI IP core is connected to the MIG IP core using an AXI4 bus.

6. The main control board based on optical port and PCIe transmission according to claim 5, characterized in that: The FPGA has a built-in XDMA, the PCIe DDR3 reading logic is connected to the XDMA using an AXI4 bus, and the XDMA is connected to the PCIe interface.

7. The main control board based on optical port and PCIe transmission according to claim 6, characterized in that: An MSI interrupt is configured in the XDMA, which is used to send an interrupt to the host computer when the FPGA receives an image data, informing the host computer that it can request an image.

8. The main control board based on optical port and PCIe transmission according to any one of claims 5 to 7, characterized in that: The clock frequency of the AXI4 bus is 125 MHz, the data bit width is 64 bits, and the address width is 64 bits; the channel width of the PCIe interface is X4, and the reference clock frequency is 100 MHz.

9. The main control board based on optical port and PCIe transmission according to any one of claims 1 to 6, characterized in that: The main control board is also provided with a clock circuit, including clock 1 and clock 2, which are connected to the FPGA respectively. The clock 1 is used to provide the clock required for the optical port to work, and the clock 2 is used to provide the clock required for the FPGA to work.

10. The main control board based on optical port and PCIe transmission according to claim 9, characterized in that: The clock 1 is a differential clock with a frequency of 156.25 MHz; the clock 2 has a frequency of 40 MHz.

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