Power supply management system of computing device and computing device

Abstract

According to the power supply management system of the computing device and the computing device, when the second terminal voltage of the control module is lower than the set value, the output power supply of the power supply unit is abnormal, at the moment, the switching module is switched to the standby power supply for supplying power, and the CPU is controlled to enter the standby state; the standby power supply supplies power to the standby voltage regulator and the memory voltage regulator, the standby voltage regulator is used for providing power for maintaining the standby function of each module in the standby state, and the memory voltage regulator is used for providing power for maintaining the original functions of the memory module and the data storage related module in the standby state. According to the embodiment of the invention, the universal DIMM can be matched based on the CPU on the market, the memory data protection after the power failure of the computing equipment is realized, the CPU does not need to support the NVDIMM, the NVDIMM does not need to be matched, and the hardware cost is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power supply, in particular to a power supply management system of a computing device and the computing device. BACKGROUND

[0002] Data and information of a computing device system are temporarily saved in a memory, and the data and information will be lost after the system is powered off, which will cause great loss to enterprises and individuals, so it is necessary to protect the memory data after the computing device system is powered off.

[0003] The current computing device product mainly uses NVDIMM (Non-volatile dual in-line memory module) on the computing device for memory data protection after the machine is powered off. After the machine is powered off, NVDIMM uses the backup power supply to write the data in DARM (Dynamic Random Access Memory) to its own NAND FLASH (Non-volatile Memory) for saving. When the machine is normally powered, NVDIMM reads the data in NAND FLASH to DRAM to continue the work before the computing device is powered off. In the scheme of using NVDIMM on the computing device for memory data protection after the system is powered off, the CPU selected by the computing device needs to support NVDIMM, and NVDIMM is more expensive than general DIMM (Dual In-line Memory Module), which leads to high cost of the computing device. CONTENT OF THE UTILITY MODEL

[0004] The purpose of the embodiment of the present application is to provide a power supply management system of a computing device and the computing device, so as to solve the problem that the existing scheme of protecting memory data after the system is powered off requires CPU to support NVDIMM and has high cost.

[0005] The power supply management system of a computing device provided by the embodiment of the present application comprises a power supply unit, a backup power supply, a logic module, a control module, a switching module, a standby voltage regulator and a memory voltage regulator.

[0006] The output end of the power supply unit is electrically connected to the VIN1 end of the switching module, the output end of the backup power supply is electrically connected to the VIN2 end of the switching module, the VOUT1 end of the switching module is electrically connected to the first end of the standby voltage regulator and the first end of the memory voltage regulator; the second end of the standby voltage regulator is electrically connected to the first end of the control module and the second end of the logic module.

[0007] The output terminal of the power supply unit is connected to the second terminal of the control module, the third terminal of the control module is connected to the fourth terminal of the logic module, the third terminal of the logic module is connected to the fifth terminal of the control module, and the first terminal of the logic module is connected to the controlled terminal of the switching module; the fourth terminal of the control module is used for signal connection with the CPU;

[0008] When the voltage at the second end of the control module is lower than the set value, the control module outputs a first control signal to the logic module; the logic module controls the switching module to switch to the backup power supply according to the first signal, and outputs a second control signal to the control module; the control module controls the CPU of the computing device to enter a standby state according to the second control signal; in the standby state, the standby voltage regulator and the memory voltage regulator are powered by the backup power supply.

[0009] In the above technical solution, when the voltage at the second terminal of the control module is lower than the set value, it indicates that the output power of the power supply unit is abnormal. At this time, the switching module switches to the backup power supply and controls the CPU to enter the standby state. The backup power supply supplies power to the standby voltage regulator and the memory voltage regulator. The standby voltage regulator is used to provide power to each module to maintain the standby function in the standby state, and the memory voltage regulator is used to provide power to the memory module and the data storage related modules to maintain their original functions in the standby state. This embodiment can be based on the CPU with a general DIMM on the market to achieve memory data protection after the computing device loses power. It does not require the CPU to support NVDIMM or to be paired with NVDIMM, thereby reducing hardware costs.

[0010] In some optional implementations, the system further includes: a CPU voltage regulator and a device voltage regulator;

[0011] VOUT1 of the switching module is also electrically connected to a first terminal of the CPU voltage regulator and a first terminal of the device voltage regulator;

[0012] The seventh terminal signal of the logic module is connected to the controlled terminal of the device voltage regulator, the sixth terminal signal of the logic module is connected to the controlled terminal of the CPU voltage regulator, and the fifth terminal signal of the logic module is connected to the controlled terminal of the memory voltage regulator;

[0013] When the computing device is in working state, the logic module controls the memory voltage regulator, the CPU voltage regulator and the device voltage regulator to turn on;

[0014] When the computing device is in a standby state, the logic module controls the memory voltage regulator to be turned on, and controls the CPU voltage regulator and the device voltage regulator to be turned off.

[0015] In the above technical solution, the CPU voltage regulator provides the power required for the normal operation of the CPU, and the device voltage regulator provides the power required for the normal operation of devices other than the CPU in the computing device.

[0016] In some optional implementations, the eighth end of the logic module is used to connect to the CPU of the computing device, and the ninth end of the logic module is used to connect to the CPU of the computing device.

[0017] After the computing device exits the working state and enters the standby state, the CPU sends an S3 low-level signal to the eighth terminal of the logic module, and the CPU sends an S5 high-level signal to the ninth terminal of the logic module. The logic module controls the CPU voltage regulator and the device voltage regulator to turn off according to these two signals, and controls the memory voltage regulator to remain on.

[0018] After the computing device exits the standby state and enters the working state, the CPU sends an S3 high-level signal to the eighth terminal of the logic module, and the CPU sends an S5 high-level signal to the ninth terminal of the logic module. The logic module controls the CPU voltage regulator and the device voltage regulator to turn on according to these two signals, and controls the memory voltage regulator to remain on.

[0019] After the computing device exits the working state and enters the shutdown state, the CPU sends an S3 low-level signal to the eighth terminal of the logic module, and the CPU sends an S5 low-level signal to the ninth terminal of the logic module. The logic module controls the memory voltage regulator, the CPU voltage regulator, and the device voltage regulator to shut down according to these two signals.

[0020] After the computing device exits the shutdown state and enters the working state, the CPU sends an S3 high-level signal to the eighth terminal of the logic module, and the CPU sends an S5 high-level signal to the ninth terminal of the logic module. The logic module controls the memory voltage regulator, the CPU voltage regulator, and the device voltage regulator to turn on according to these two signals.

[0021] In some optional embodiments, when the voltage at the second end of the control module is higher than a set value, the control module outputs a third control signal to the logic module; the logic module controls the switching module to switch to powering the power supply unit according to the third signal, controls the device voltage regulator and the CPU voltage regulator to turn on, and outputs a fourth control signal to the control module; the control module controls the CPU to enter a working state according to the fourth control signal.

[0022] In the above technical solution, when the voltage at the second end of the control module is higher than the set value, the output power of the power supply unit returns to normal. At this time, the switching module switches to power supply to the power supply unit, and controls the CPU to enter the working state. The power supply unit supplies power to the CPU voltage regulator, device voltage regulator, standby voltage regulator and memory voltage regulator. The device voltage regulator is used to provide the power required by each module in the working state, the memory voltage regulator is used to provide the power required by the memory module and data storage related modules in the working state, and the CPU voltage regulator is used to provide the power required by the CPU in the working state.

[0023] In some optional embodiments, the standby voltage regulator is configured to be electrically connected to a device module of the computing device and to be electrically connected to a CPU of the computing device;

[0024] The memory voltage regulator is configured to be electrically connected to a memory module of the computing device and to be electrically connected to a CPU of the computing device;

[0025] A CPU voltage regulator is configured to be electrically connected to a CPU of a computing device;

[0026] A device voltage regulator is configured to electrically connect to a device module of a computing device;

[0027] When the computing device is in standby mode, the standby voltage regulator provides a first power supply for the device module, CPU, control module and logic module for standby operation, and the memory voltage regulator provides a second power supply for the CPU and memory module for memory operation;

[0028] When the computing device is in working state, the standby voltage regulator provides the first power supply for standby operation to the device module, CPU, control module and logic module; the memory voltage regulator provides the second power supply for memory operation to the CPU and memory module; the CPU voltage regulator provides the third power supply for normal operation to the CPU; and the device voltage regulator provides the fourth power supply for normal operation to the device module.

[0029] In some optional implementations, the device module includes at least one of the following: HDD, FAN, OCP, and PCIe.

[0030] In the above technical solution, an HDD, or Hard Disk Drive, is a computer storage device used to store and retrieve digital data. On computing devices, HDDs are typically used to store large amounts of data, such as files, applications, and databases. A fan (FAN) generates heat when a computing device performs extensive data processing tasks. The fan helps expel hot air and draw in cool air to maintain a suitable operating temperature for the computing device. The Open Compute Project (OCP) is a hardware accelerator card for computing devices that can be connected to the computing device motherboard using a PCIe interface to increase the computing power, storage capacity, or network bandwidth of the computing device. PCIe, or Peripheral Component Interconnect Express, is a high-speed serial bus interface used to connect a computing device motherboard to other external devices. Computing device PCIe cards typically have multiple PCIe slots that can accommodate different types of expansion cards to meet the needs of different computing device applications.

[0031] In some optional embodiments, the input terminal of the backup power supply is connected to the VOUT2 terminal of the switching module;

[0032] When the computing device is in working state and the backup power supply is not fully charged, the power supply unit charges the backup power supply.

[0033] In the above technical solution, when the computing device is in working state, the VIN1 terminal of the switching module is connected to the VOUT1 terminal and VOUT2 terminal of the switching module, and the voltage at the VOUT2 terminal of the switching module charges the backup power supply. When the backup power supply is fully charged, the backup power supply itself turns off the charging function.

[0034] In some optional implementations, the VOUT1 terminal of the switching module is connected to the controlled terminal of the standby voltage regulator through a second voltage-dividing resistor;

[0035] The voltage of the VOUT1 terminal of the switching module is divided by the second voltage-dividing resistor, which pulls up the voltage of the controlled terminal of the standby voltage regulator, thereby turning on the standby voltage regulator.

[0036] In some optional implementations, the output end of the power supply unit is connected to the second end of the control module through a first voltage-dividing resistor.

[0037] In some optional embodiments, the power supply unit includes a redundant power supply unit, and the backup power supply includes a redundant backup power supply.

[0038] A computing device provided in an embodiment of the present application includes: a device module, a CPU, a memory module, and a power supply management system of a computing device such as any of the above. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0040] Figure 1 A circuit diagram of a power supply management system for a computing device provided in the first embodiment of the present application;

[0041] Figure 2 A circuit diagram of a power supply management system for a computing device provided in the second embodiment of the present application;

[0042] Figure 3 A circuit diagram of a power supply management system for a computing device provided in the third embodiment of the present application;

[0043] Figure 4 This is a circuit diagram of a power supply management system for a computing device provided in the fourth embodiment of the present application. DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0045] For ease of understanding, some terms that appear in the examples of this application are first explained:

[0046] Standby state: When the computing device is in standby state, it provides standby voltage to devices such as the CPU, BMC, CPU, PCIe, and provides working power to the memory module and related functional modules in the CPU.

[0047] Working state: The computing device is in working state, and all device functions are fully enabled.

[0048] Shutdown state: When the computing device is in shutdown state, it provides standby voltage to devices such as the CPU, BMC, CPU, and PCIe.

[0049] Voltage regulator: Generally requires power input and switch enable to power the device.

[0050] PSU: Power Supply Unit, power supply unit.

[0051] BBU: Battery Backup-up Unit, backup battery unit.

[0052] Electrical connection: connection line for electrical energy transmission, represented in the figures of the present embodiment by a solid line connection.

[0053] Signal connection: connection line for signal transmission of low voltage and weak current, represented in the figures of the present embodiment by a dashed line connection.

[0054] Please refer to Figure 1 , Figure 1 A power supply management system circuit structure of a computing device provided by the first embodiment of the present application, specifically comprising: a power supply unit, a backup power supply, a logic module, a control module, a switching module, a standby voltage regulator and a memory voltage regulator.

[0055] The output end of the power supply unit is electrically connected to the VIN1 end of the switching module, the output end of the backup power supply is electrically connected to the VIN2 end of the switching module, and the VOUT1 end of the switching module is electrically connected to the first end of the standby voltage regulator and the first end of the memory voltage regulator; the second end of the standby voltage regulator is electrically connected to the first end of the control module and the second end of the logic module; the output end of the power supply unit is signal connected to the second end of the control module, the third end of the control module is signal connected to the fourth end of the logic module, the third end of the logic module is signal connected to the fifth end of the control module, and the first end of the logic module is signal connected to the controlled end of the switching module; the fourth end of the control module is used for signal connection with the CPU.

[0056] When the voltage at the second end of the control module is lower than the set value, the control module outputs a first control signal to the logic module; the logic module controls the switching module to switch to the backup power supply for power supply according to the first signal, and outputs a second control signal to the control module; the control module controls the CPU to enter a standby state according to the second control signal; and the computing device is powered by the backup power supply for the standby voltage regulator and the memory voltage regulator in the standby state. In the above technical solution, when the voltage at the second end of the control module is lower than the set value, the output power of the power supply unit is abnormal, at this time, the switching module is switched to the backup power supply for power supply, and the CPU is controlled to enter the standby state, the standby voltage regulator is used to provide power for maintaining standby functions of each module in the standby state, and the memory voltage regulator is used to provide power for maintaining original functions of the memory module and the data-related module in the standby state. The present embodiment can realize memory data protection after power failure of the computing device based on the CPU matched with the general DIMM on the market, without the need of CPU supporting NVDIMM and matching NVDIMM, thereby reducing the hardware cost.

[0057] In some optional embodiments, the output end of the power supply unit is connected to the second end of the control module through a first voltage dividing resistor.

[0058] The first voltage divider resistor in this embodiment includes a resistor R1 and a resistor R2, the output end of the power supply unit is connected to the first end of the resistor R1, the second end of the resistor R2 is connected to the first end of the resistor R2, the second end of the resistor R2 is grounded, and the first end of the resistor R2 is connected to the second end of the control module.

[0059] Where R1 = 15.8KΩ and R2 = 2KΩ. The normal output voltage of the power supply unit is 12V. At this time, the second terminal of the control module detects a voltage of 1.348V at the first terminal of resistor R2. When the output voltage of the power supply unit drops to 11V, the power supply output is considered abnormal. At this time, the second terminal of the control module detects a voltage of 1.235V at the first terminal of resistor R2.

[0060] When the second end of the control module detects that the voltage at the first end of the resistor R2 is higher than 1.235V, the third end of the control module outputs a high level to pull up the voltage at the fourth end of the logic module; the logic module sets the voltage at the first end of the logic module to a high level based on the high voltage at the fourth end of the logic module; the controlled end of the switching module is connected to the first end of the logic module, and the controlled end of the switching module receives a high level, and connects the VIN1 end of the switching module to the VOUT1 end of the switching module, and the power supply unit supplies power to the standby voltage regulator and the memory voltage regulator.

[0061] In some optional implementations, the input end of the backup power supply is connected to the VOUT2 end of the switching module; when the computing device is in working state and the backup power supply is not fully charged, the power supply unit charges the backup power supply.

[0062] In the above technical solution, when the computing device is in working state, the VIN1 terminal of the switching module is connected to the VOUT1 terminal and VOUT2 terminal of the switching module, and the voltage at the VOUT2 terminal of the switching module charges the backup power supply. When the backup power supply is fully charged, the backup power supply itself turns off the charging function.

[0063] In some optional embodiments, the VOUT1 terminal of the switching module is connected to the controlled terminal of the standby voltage regulator through a second voltage-dividing resistor; the voltage of the VOUT1 terminal of the switching module after being divided by the second voltage-dividing resistor pulls up the controlled terminal voltage of the standby voltage regulator, turning on the standby voltage regulator.

[0064] In this embodiment, the VOUT1 end of the switching module is connected to the first end of the resistor R3, the second end of the resistor R3 is connected to the first end of the resistor R4, the second end of the resistor R4 is grounded, and the first end of the resistor R4 is connected to the controlled end of the standby voltage regulator. When the computing device is powered on for the first time, the power supply module outputs an enable signal to the controlled end of the standby voltage regulator through the switching module and the second voltage dividing resistor, and the standby voltage regulator is turned on. Thereafter, whether the computing device is in a working state or a standby state, the standby voltage regulator remains turned on. In the working state of the computing device, the power supply module outputs an enable signal to the controlled end of the standby voltage regulator through the switching module and the second voltage dividing resistor, and the standby voltage regulator is turned on. In the standby state of the computing device, the standby power supply outputs an enable signal to the controlled end of the standby voltage regulator through the switching module and the second voltage dividing resistor, and the standby voltage regulator is turned on.

[0065] In some optional embodiments, the power management system of the computing device further includes a CPU voltage regulator. The CPU voltage regulator provides power required for normal operation of the CPU.

[0066] In the working state of the computing device, the logic module controls the memory voltage regulator and the CPU voltage regulator to be turned on, and controls the VIN1 end and the VOUT1 end of the switching module to be in communication, so that the standby voltage regulator, the memory voltage regulator, and the CPU voltage regulator are powered by the power supply unit.

[0067] In the standby state of the computing device, the logic module controls the memory voltage regulator to be turned on and controls the CPU voltage regulator to be turned off, and controls the VIN2 end and the VOUT1 end of the switching module to be in communication, so that the standby voltage regulator and the memory voltage regulator are powered by the standby power supply.

[0068] In some optional embodiments, the power management system of the computing device further includes a device voltage regulator. The device voltage regulator provides power required for normal operation of various device modules, including FAN, HDD, PCIe, OCP, and the like.

[0069] In the working state of the computing device, the logic module controls the memory voltage regulator and the device voltage regulator to be turned on, and controls the VIN1 end and the VOUT1 end of the switching module to be in communication, so that the standby voltage regulator, the memory voltage regulator, and the device voltage regulator are powered by the power supply unit.

[0070] In the standby state of the computing device, the logic module controls the memory voltage regulator to be turned on and controls the device voltage regulator to be turned off, and controls the VIN2 end and the VOUT1 end of the switching module to be in communication, so that the standby voltage regulator and the memory voltage regulator are powered by the standby power supply.

[0071] In some optional embodiments, the power supply unit includes a redundant power supply unit, and the backup power supply includes a redundant backup power supply. For example, when the computing device is fully loaded, the total power consumption is 600W, the power supply unit includes two 800W PSUs, 1+1 redundancy, and the backup power supply includes two 60Wh BBUs as PSUs.

[0072] Please refer to Figure 2 , Figure 2 This is a circuit diagram of a power management system for a computing device, provided in the second embodiment of this application. This power management system also includes a CPU voltage regulator and a device voltage regulator. The CPU voltage regulator provides the power required for normal CPU operation, while the device voltage regulator provides the power required for normal operation of devices other than the CPU in the computing device.

[0073] Among them, VOUT1 of the switching module is also electrically connected to the first end of the CPU voltage regulator and the first end of the device voltage regulator; the seventh end signal of the logic module is connected to the controlled end of the device voltage regulator, the sixth end signal of the logic module is connected to the controlled end of the CPU voltage regulator, and the fifth end signal of the logic module is connected to the controlled end of the memory voltage regulator.

[0074] When the computing device is in working state, the logic module controls the memory voltage regulator, the CPU voltage regulator and the device voltage regulator to turn on;

[0075] When the computing device is in a standby state, the logic module controls the memory voltage regulator to be turned on, and controls the CPU voltage regulator and the device voltage regulator to be turned off.

[0076] In some optional embodiments, the standby voltage regulator is used to be electrically connected to the device module and to the CPU; the memory voltage regulator is used to be electrically connected to the memory module and to the CPU; the CPU voltage regulator is used to be electrically connected to the CPU; and the device voltage regulator is used to be electrically connected to the device module.

[0077] When the computing device is in standby mode, the standby voltage regulator provides a first power supply for the device module, CPU, control module and logic module for standby operation, and the memory voltage regulator provides a second power supply for the CPU and memory module for memory operation;

[0078] When the computing device is in working state, the standby voltage regulator provides the first power supply for standby operation to the device module, CPU, control module and logic module; the memory voltage regulator provides the second power supply for memory operation to the CPU and memory module; the CPU voltage regulator provides the third power supply for normal operation to the CPU; and the device voltage regulator provides the fourth power supply for normal operation to the device module.

[0079] In some optional implementations, the device module includes at least one of the following: HDD, FAN, OCP, and PCIe.

[0080] In the above technical solution, an HDD, or Hard Disk Drive, is a computer storage device used to store and retrieve digital data. On computing devices, HDDs are typically used to store large amounts of data, such as files, applications, and databases. A fan (FAN) generates heat when a computing device performs extensive data processing tasks. The fan helps expel hot air and draw in cool air to maintain a suitable operating temperature for the computing device. The Open Compute Project (OCP) is a hardware accelerator card for computing devices that can be connected to the computing device motherboard using a PCIe interface to increase the computing power, storage capacity, or network bandwidth of the computing device. PCIe, or Peripheral Component Interconnect Express, is a high-speed serial bus interface used to connect a computing device motherboard to other external devices. Computing device PCIe cards typically have multiple PCIe slots that can accommodate different types of expansion cards to meet the needs of different computing device applications.

[0081] In this embodiment, when the voltage at the second terminal of the control module falls below a set value, the control module outputs a first control signal to the logic module. Based on the first signal, the logic module controls the switching module to switch to the backup power supply and outputs a second control signal to the control module. Based on the second control signal, the control module controls the CPU to enter a standby state, activating the DDR self-refresh function so that the memory module can maintain current data. After the CPU enters the standby state, i.e., after the computing device enters the standby state, the logic module controls the device voltage regulator and the CPU voltage regulator to shut down. The backup power supply then powers the memory voltage regulator and the standby voltage regulator. This power-off power is applied to the computing device's FAN, HDD, PCIe, OCP, and other devices, reducing the computing device's power consumption by over 80%. When the computing device is in S3 state, it relies primarily on the backup power supply. At this time, the computing device consumes approximately 600W x 15% = 90W. Using two 60Wh BBUs for the backup power supply, the computing device can be powered for 120Wh ÷ 90W = 1.3 hours.

[0082] When the voltage at the second terminal of the control module exceeds a set value, the control module outputs a third control signal to the logic module. Based on the third signal, the logic module controls the switching module to switch power to the power supply unit, turning on the device voltage regulator and the CPU voltage regulator, and outputs a fourth control signal to the control module. Based on the fourth control signal, the control module controls the CPU to enter an operating state. After the CPU enters the operating state, i.e., after the computing device enters the operating state, the logic module controls the device voltage regulator and the CPU voltage regulator to turn on, and the power supply unit supplies power to the device voltage regulator, the CPU voltage regulator, the memory voltage regulator, and the standby voltage regulator.

[0083] In the above technical solution, when the voltage at the second end of the control module is lower than the set value, the output power of the power supply unit is abnormal. At this time, the switching module switches to the backup power supply and controls the CPU to enter the standby state. The standby power supply supplies power to the standby voltage regulator and the memory voltage regulator. The standby voltage regulator is used to provide power to each module to maintain the standby function in the standby state, and the memory voltage regulator is used to provide power to the memory module and the data storage related modules to maintain their original functions in the standby state.

[0084] When the voltage at the second end of the control module is higher than the set value, the output power of the power supply unit returns to normal. At this time, the switching module switches to power supply to the power supply unit and controls the CPU to enter the working state. The power supply unit supplies power to the CPU voltage regulator, device voltage regulator, standby voltage regulator and memory voltage regulator. The device voltage regulator is used to provide the power required by each module in the working state. The memory voltage regulator is used to provide the power required by the memory module and data storage related modules in the working state. The CPU voltage regulator is used to provide the power required by the CPU in the working state.

[0085] Please refer to Figure 3 , Figure 3 This is a circuit diagram of a power management system for a computing device provided in the third embodiment of this application. This differs from the second embodiment in that the eighth terminal of the logic module in this embodiment is connected to the CPU and is used to receive the S3 control signal sent by the CPU. The S3 control signal includes an S3 low-level signal and an S3 high-level signal.

[0086] When a computing device switches from working state to standby state, the workflow of the power supply management system is as follows:

[0087] When the computing device is in working state, the VIN1 end of the switching module is connected to the VOUT1 end and the VOUT2 end of the switching module, the VOUT2 end charges the backup power supply, and the VOUT1 end supplies power to the device voltage regulator, the CPU voltage regulator, the memory voltage regulator and the standby voltage regulator, and the device voltage regulator, the CPU voltage regulator, the memory voltage regulator and the standby voltage regulator remain turned on.

[0088] When the second terminal of the control module detects that the output voltage of the power supply unit is lower than the set value, the control module lowers the voltage of its third terminal, and the third terminal of the control module sends a low-level signal to the fourth terminal of the logic module. Based on the low-level signal from its fourth terminal, the logic module controls its first terminal to output a low-level signal to the controlled terminal of the switching module. Simultaneously, the third terminal of the logic module outputs a low-level signal to the fifth terminal of the control module. Upon receiving the low-level signal, the controlled terminal of the switching module controls the VIN2 terminal of the switching module to connect to the VOUT1 terminal, disconnecting the VIN1 terminal from the VOUT1 terminal, and switching to the backup power supply. After receiving the low-level signal from the fifth terminal of the control module, the fourth terminal of the control module sends a control signal to the CPU via the IPMI interface to enter standby mode, causing the computing device to enter standby mode. The CPU activates the DDR self-refresh function, allowing the memory module to retain current data.

[0089] After the computing device enters standby mode, the CPU sends a low-level signal (S3) to the eighth terminal of the logic module. Based on the S3 low-level signal, the logic module outputs a low-level signal to the controlled terminal of the device voltage regulator via its seventh terminal, shutting down the device voltage regulator. It then outputs a low-level signal to the controlled terminal of the CPU voltage regulator via its sixth terminal, shutting down the CPU voltage regulator. At this point, the backup power supply supplies power to the memory voltage regulator and the standby voltage regulator via the switching module.

[0090] When a computing device switches from standby mode to working mode, the power management system operates as follows:

[0091] When the computing device is in standby mode, the VIN2 end of the switching module is connected to the VOUT1 end of the switching module, and the VOUT1 end supplies power to the memory voltage regulator and the standby voltage regulator. The device voltage regulator and the CPU voltage regulator are turned off, and the memory voltage regulator and the standby voltage regulator remain on.

[0092] When the second terminal of the control module detects that the output voltage of the power supply unit is higher than a set value, the control module raises the voltage at its third terminal, and the third terminal of the control module sends a high-level signal to the fourth terminal of the logic module. Based on the high-level signal at its fourth terminal, the logic module controls its first terminal to output a high-level signal to the controlled terminal of the switching module. Simultaneously, the third terminal of the logic module outputs a high-level signal to the fifth terminal of the control module. Upon receiving the high-level signal, the controlled terminal of the switching module controls the VIN1 terminal of the switching module to connect the VOUT1 and VOUT2 terminals, disconnecting the VIN2 terminal from VOUT1. Power is supplied by the power supply unit, and the VOUT2 terminal charges the backup power supply. After receiving the high-level signal at the fifth terminal of the control module, the fourth terminal of the control module sends a control signal to the CPU via the IPMI interface to enter the operating state, causing the computing device to enter the operating state. The memory retains the data before the power outage, and the computing device continues the task it was performing before the power outage.

[0093] After the computing device enters the operating state, the CPU sends a high-level signal S3 to the eighth terminal of the logic module. Based on the high-level signal S3, the logic module outputs a high-level signal to the controlled terminal of the device voltage regulator via its seventh terminal, controlling the device voltage regulator to turn on. It then outputs a high-level signal to the controlled terminal of the CPU voltage regulator via its sixth terminal, controlling the CPU voltage regulator to turn on. At this point, the power supply unit supplies power to the device voltage regulator, CPU voltage regulator, memory voltage regulator, and standby voltage regulator via the switching module.

[0094] One or more of the above embodiments describe the operation of the power management system for a computing device in the working state and the standby state. In fact, a computing device also has a shutdown state in addition to the working state and the standby state. The following embodiments describe the operation of the power management system for a computing device in these three states.

[0095] Please refer to Figure 4 , Figure 4 This is a circuit diagram of a power management system for a computing device provided in the fourth embodiment of the present application. This embodiment differs from the second embodiment in that: the eighth terminal of the logic module in this embodiment is connected to the CPU, and the ninth terminal of the logic module is also connected to the CPU; the eighth terminal of the logic module is used to receive the S3 control signal sent by the CPU, and the ninth terminal of the logic module is used to receive the S5 control signal sent by the CPU. The S3 control signal includes an S3 high-level signal and an S3 low-level signal, and the S5 control signal includes an S5 high-level signal and an S5 low-level signal.

[0096] When a computing device switches from working state to standby state, the workflow of the power supply management system is as follows:

[0097] When the computing device is in working state, the VIN1 end of the switching module is connected to the VOUT1 end and the VOUT2 end of the switching module, the VOUT2 end charges the backup power supply, and the VOUT1 end supplies power to the device voltage regulator, the CPU voltage regulator, the memory voltage regulator and the standby voltage regulator, and the device voltage regulator, the CPU voltage regulator, the memory voltage regulator and the standby voltage regulator remain turned on.

[0098] When the second terminal of the control module detects that the output voltage of the power supply unit is lower than the set value, the control module lowers the voltage of its third terminal, and the third terminal of the control module sends a low-level signal to the fourth terminal of the logic module. Based on the low-level signal from its fourth terminal, the logic module controls its first terminal to output a low-level signal to the controlled terminal of the switching module. Simultaneously, the third terminal of the logic module outputs a low-level signal to the fifth terminal of the control module. Upon receiving the low-level signal, the controlled terminal of the switching module controls the VIN2 terminal of the switching module to connect to the VOUT1 terminal, disconnecting the VIN1 terminal from the VOUT1 terminal, and switching to the backup power supply. After receiving the low-level signal from the fifth terminal of the control module, the fourth terminal of the control module sends a control signal to the CPU via the IPMI interface to enter standby mode, causing the computing device to enter standby mode. The CPU activates the DDR self-refresh function, allowing the memory module to retain current data.

[0099] After the computing device enters standby mode, the CPU sends a low-level signal (S3) to the eighth terminal of the logic module, and a high-level signal (S5) to the ninth terminal of the logic module. Based on the low-level signal (S3) and the high-level signal (S5), the logic module outputs a low-level signal to the controlled terminal of the device voltage regulator via the seventh terminal of the logic module, shutting down the device voltage regulator. It then outputs a low-level signal to the controlled terminal of the CPU voltage regulator via the sixth terminal of the logic module, shutting down the CPU voltage regulator. At this point, the backup power supply supplies power to the memory voltage regulator and the standby voltage regulator via the switching module.

[0100] When a computing device switches from standby mode to working mode, the power management system operates as follows:

[0101] When the computing device is in standby mode, the VIN2 end of the switching module is connected to the VOUT1 end of the switching module, and the VOUT1 end supplies power to the memory voltage regulator and the standby voltage regulator. The device voltage regulator and the CPU voltage regulator are turned off, and the memory voltage regulator and the standby voltage regulator remain on.

[0102] When the second terminal of the control module detects that the output voltage of the power supply unit is higher than a set value, the control module raises the voltage of its third terminal, and the third terminal of the control module sends a high-level signal to the fourth terminal of the logic module. Based on the high-level signal at its fourth terminal, the logic module controls its first terminal to output a high-level signal to the controlled terminal of the switching module. Simultaneously, the third terminal of the logic module outputs a high-level signal to the fifth terminal of the control module. Upon receiving the high-level signal, the controlled terminal of the switching module controls the VIN1 terminal of the switching module to connect the VOUT1 and VOUT2 terminals, disconnecting the VIN2 terminal from VOUT1, allowing the power supply unit to supply power, while the VOUT2 terminal charges the backup power supply. After receiving the high-level signal at the fifth terminal of the control module, the fourth terminal of the control module sends a control signal to the CPU via the IPMI interface to enter the operating state, thus putting the computing device into operation.

[0103] After the computing device enters the operating state, the CPU sends a high-level signal (S3) to the eighth terminal of the logic module, and then a high-level signal (S5) to the ninth terminal of the logic module. Based on the high-level signals (S3 and S5), the logic module outputs a high-level signal to the controlled terminal of the device voltage regulator via the seventh terminal of the logic module, controlling the device voltage regulator to turn on. It then outputs a high-level signal to the controlled terminal of the CPU voltage regulator via the sixth terminal of the logic module, controlling the CPU voltage regulator to turn on. At this point, the power supply unit supplies power to the device voltage regulator, the CPU voltage regulator, the memory voltage regulator, and the standby voltage regulator via the switching module.

[0104] When a computing device switches from a working state to a shutdown state, the power supply management system operates as follows:

[0105] When the computing device is in working state, the VIN1 end of the switching module is connected to the VOUT1 end and the VOUT2 end of the switching module, the VOUT2 end charges the backup power supply, and the VOUT1 end supplies power to the device voltage regulator, the CPU voltage regulator, the memory voltage regulator and the standby voltage regulator, and the device voltage regulator, the CPU voltage regulator, the memory voltage regulator and the standby voltage regulator remain turned on.

[0106] When the computing device shuts down normally, the CPU sends a low-level signal S3 to the eighth terminal of the logic module, and then sends a low-level signal S5 to the ninth terminal of the logic module. Based on the low-level signals S3 and S5, the logic module outputs a low-level signal to the controlled terminal of the device voltage regulator via the seventh terminal of the logic module, controlling the device voltage regulator to shut down. The logic module then outputs a low-level signal to the controlled terminal of the CPU voltage regulator via the sixth terminal of the logic module, controlling the CPU voltage regulator to shut down. The logic module then outputs a low-level signal to the controlled terminal of the memory voltage regulator via the fifth terminal of the logic module, controlling the memory voltage regulator to shut down. The logic module then outputs a low-level signal to the switching module via the first terminal of the switching module, controlling the connection between the switching module's VIN2 and VOUT1 terminals. At this point, the backup power supply supplies power to the standby voltage regulator via the switching module.

[0107] When a computing device switches from shutdown to working state, the power management system operates as follows:

[0108] When the computing device is in a shutdown state, the VIN2 terminal and the VOUT1 terminal of the switching module are connected, and the backup power supply supplies power to the standby voltage regulator through the switching module.

[0109] When the computing device is powered on, the CPU sends a high-level signal (S3) to the eighth terminal of the logic module, and then a high-level signal (S5) to the ninth terminal of the logic module. Based on the high-level signals (S3 and S5), the logic module outputs a high-level signal to the switching module via its first terminal, controlling the switching module's VIN1 terminal to connect to VOUT1 and VOUT2. The logic module then outputs a high-level signal to the controlled terminal of the device voltage regulator via its seventh terminal, enabling the device voltage regulator to turn on. The logic module then outputs a high-level signal to the controlled terminal of the CPU voltage regulator via its sixth terminal, enabling the CPU voltage regulator to turn on. The logic module then outputs a high-level signal to the memory voltage regulator via its fifth terminal, enabling the memory voltage regulator to turn on. At this point, the power supply unit supplies power to the device voltage regulator, the CPU voltage regulator, the memory voltage regulator, and the standby voltage regulator via the switching module.

[0110] A computing device provided in an embodiment of the present application includes: a device module, a CPU, a memory module, and a power supply management system of a computing device such as any of the above.

[0111] In the embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interface, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0112] In addition, the units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0113] Furthermore, the functional modules in each embodiment of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0114] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any actual relationship or order between these entities or operations.

[0115] The above description is merely an embodiment of the present application and is not intended to limit the scope of protection of the present application. For those skilled in the art, various modifications and variations of the present application are possible. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A power supply management system for a computing device, characterized in that: include: Power supply unit, backup power supply, logic module, control module, switching module, standby voltage regulator and memory voltage regulator; The output end of the power supply unit is electrically connected to the VIN1 end of the switching module, the output end of the backup power supply is electrically connected to the VIN2 end of the switching module, the VOUT1 end of the switching module is electrically connected to the first end of the standby voltage regulator and the first end of the memory voltage regulator; the second end of the standby voltage regulator is electrically connected to the first end of the control module and the second end of the logic module; The output terminal of the power supply unit is connected to the second terminal of the control module by signal, the third terminal of the control module is connected to the fourth terminal of the logic module by signal, the third terminal of the logic module is connected to the fifth terminal of the control module by signal, and the first terminal of the logic module is connected to the controlled terminal of the switching module by signal; the fourth terminal of the control module is used for signal connection to the CPU of the computing device; When the voltage at the second end of the control module is lower than a set value, the control module outputs a first control signal to the logic module; the logic module controls the switching module to switch to the backup power supply according to the first signal, and outputs a second control signal to the control module; the control module controls the CPU to enter a standby state according to the second control signal; when the computing device is in the standby state, the standby voltage regulator and the memory voltage regulator are powered by the backup power supply.

2. The power supply management system according to claim 1, wherein: Also includes: CPU voltage regulator and device voltage regulator; VOUT1 of the switching module is also electrically connected to a first end of the CPU voltage regulator and a first end of the device voltage regulator; The seventh terminal signal of the logic module is connected to the controlled terminal of the device voltage regulator, the sixth terminal signal of the logic module is connected to the controlled terminal of the CPU voltage regulator, and the fifth terminal signal of the logic module is connected to the controlled terminal of the memory voltage regulator; When the computing device is in working state, the logic module controls the memory voltage regulator, the CPU voltage regulator and the device voltage regulator to be turned on; When the computing device is in a standby state, the logic module controls the memory voltage regulator to be turned on, and controls the CPU voltage regulator and the device voltage regulator to be turned off.

3. The power supply management system according to claim 2, wherein: When the voltage at the second end of the control module is higher than a set value, the control module outputs a third control signal to the logic module; the logic module controls the switching module to switch to supply power to the power supply unit according to the third signal, controls the device voltage regulator and the CPU voltage regulator to turn on, and outputs a fourth control signal to the control module; the control module controls the CPU to enter a working state according to the fourth control signal.

4. The power supply management system according to claim 2, wherein: The standby voltage regulator is configured to be electrically connected to a device module of the computing device and to be electrically connected to a CPU of the computing device; The memory voltage regulator is configured to be electrically connected to the memory module of the computing device and to be electrically connected to the CPU; The CPU voltage regulator is used to be electrically connected to the CPU of the computing device; The device voltage regulator is configured to be electrically connected to a device module of the computing device; When the computing device is in a standby state, the standby voltage regulator provides a first power supply for the device module, the CPU, the control module, and the logic module for standby operation, and the memory voltage regulator provides a second power supply for the CPU and the memory module for memory operation; When the computing device is in working state, the standby voltage regulator provides a first power supply for standby operation to the device module, CPU, control module and logic module, the memory voltage regulator provides a second power supply for memory operation to the CPU and memory module, the CPU voltage regulator provides a third power supply for normal operation to the CPU, and the device voltage regulator provides a fourth power supply for normal operation to the device module.

5. The power supply management system according to claim 4, wherein: The device module includes at least one of the following: HDD, FAN, OCP and PCIe.

6. The power supply management system according to claim 2, wherein: The eighth terminal of the logic module is used to connect to the CPU, and the ninth terminal of the logic module is used to connect to the CPU.

7. The power supply management system according to claim 1, wherein: The input end of the backup power supply is connected to the VOUT2 end of the switching module; When the computing device is in working state and the backup power supply is not fully charged, the power supply unit charges the backup power supply.

8. The power supply management system according to claim 1, wherein: The VOUT1 terminal of the switching module is connected to the controlled terminal of the standby voltage regulator through a second voltage-dividing resistor; The voltage of the VOUT1 terminal of the switching module divided by the second voltage-dividing resistor pulls up the voltage of the controlled terminal of the standby voltage regulator, turning on the standby voltage regulator.

9. The power supply management system according to claim 1, wherein: The output end of the power supply unit is connected to the second end of the control module through a first voltage dividing resistor.

10. A computing device, characterized in that include: A device module, a CPU, a memory module, and a power supply management system for a computing device as described in any one of claims 1 to 9.

Images