Bidirectional DC / DC converter

Abstract

The utility model discloses a bidirectional DC / DC converter. The bidirectional DC / DC converter comprises a buck-boost module, a control module and a first timer, the buck-boost module comprises a first switch and a second switch which are alternately closed, and the first timer is configured to trigger the control module to output a first pulse width signal and a second pulse width signal which are complementary to each other to the first switch and the second switch in a first counting period; the time difference between the rising edge of the first pulse width signal and the falling edge of the second pulse width signal is greater than the first time, and the time difference between the falling edge of the first pulse width signal and the rising edge of the second pulse width signal is greater than the second time, so that short circuit caused by simultaneous conduction of the first switch and the second switch can be avoided. In addition, it can be ensured that the bidirectional DC / DC converter can be seamlessly and rapidly switched between charging and discharging operations only by configuring a timer at the control module, the cost of the converter is reduced, and the reliability of the converter is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of switching power supply, in particular to a bidirectional DC / DC converter. BACKGROUND

[0002] The bidirectional DC / DC (Direct Current / Direct Current) converter is a power electronic device capable of realizing bidirectional conversion of electric energy, which can convert electric energy from one DC power supply to another DC power supply, and can feed back energy from the load to the power supply.

[0003] In the related art, when the bidirectional DC / DC converter is applied to new energy vehicles, uninterruptible power supply systems (UPS) and energy storage systems (ESS), the bidirectional DC / DC converter needs to additionally build a set of hardware logic gate circuit or improve the program of the control module of the bidirectional DC / DC converter to ensure that the bidirectional DC / DC converter can realize seamless and fast conversion between charging and discharging operations. However, the additional construction of a set of hardware logic gate circuit will increase the cost of the bidirectional DC / DC converter, and is also not conducive to reducing the size of the bidirectional DC / DC converter; improving the program of the control module of the bidirectional DC / DC converter will additionally increase the load of the control module, resulting in slower processing speed and poorer reliability, which does not meet the actual product use. CONTENT OF THE UTILITY MODEL

[0004] In view of the deficiencies of the prior art, the present application provides a bidirectional DC / DC converter, which aims to solve the technical problems of high cost and poor reliability of the bidirectional DC / DC converter in the prior art.

[0005] To solve the above problems, the present application provides a bidirectional DC / DC converter, which comprises:

[0006] a first input end, a second input end, a first output end and a second output end;

[0007] a bidirectional buck-boost circuit comprising at least one buck-boost module, the buck-boost module comprising a first switch and a second switch, a first end of the first switch being electrically connected to the first input end, a second end of the first switch being electrically connected to the first output end, a first end of the second switch being electrically connected to the first output end, and a second end of the second switch being electrically connected to the second input end and the second output end respectively;

[0008] a control module electrically connected to a control end of the first switch and a control end of the second switch respectively;

[0009] a first timer electrically connected to the control module, the first timer configured to trigger the control module to output a first pulse width signal to a control end of the first switch within a preset first counting period; or / and output a second pulse width signal to a control end of the second switch within the first counting period;

[0010] wherein the first pulse width signal and the second pulse width signal are complementary, a time difference between a rising edge of the first pulse width signal and a falling edge of the second pulse width signal is greater than a preset first time; or / and a time difference between a falling edge of the first pulse width signal and a rising edge of the second pulse width signal is greater than a preset second time.

[0011] Further, in the bidirectional DC / DC converter, the first timer counts in an increasing manner within a first half of the first counting period and counts in a decreasing manner within a second half of the first counting period; or,

[0012] the first timer counts in a decreasing manner within the first half of the first counting period and counts in an increasing manner within the second half of the first counting period.

[0013] Further, in the bidirectional DC / DC converter, the bidirectional buck-boost circuit includes two parallel buck-boost modules, the two buck-boost modules being a first buck-boost module and a second buck-boost module respectively;

[0014] wherein the first timer is configured to trigger the control module to output the first pulse width signal to a control end of a first switch in the first buck-boost module and output a third pulse width signal to a control end of a first switch in the second buck-boost module within the first counting period; or / and,

[0015] the control module outputs the second pulse width signal to a control end of a second switch in the first buck-boost module and outputs a fourth pulse width signal to a control end of a second switch in the second buck-boost module within the first counting period.

[0016] Further, in the bidirectional DC / DC converter, a time difference between a rising edge or / and a falling edge of the first pulse width signal and the third pulse width signal is equal to half of the first counting period; or / and,

[0017] a time difference between a rising edge or / and a falling edge of the second pulse width signal and the fourth pulse width signal is equal to half of the first counting period.

[0018] Further, in the bidirectional DC / DC converter, the bidirectional DC / DC converter further includes a second timer electrically connected to the control module, the bidirectional buck-boost circuit includes four parallel buck-boost modules, the four buck-boost modules being a first buck-boost module, a second buck-boost module, a third buck-boost module and a fourth buck-boost module respectively;

[0019] The second timer is configured to trigger the control module to output a fifth pulse width signal to the first switch in the third buck-boost module and a seventh pulse width signal to the first switch in the fourth buck-boost module in a preset second counting period, respectively; or / and,

[0020] In the second counting period, the control module outputs a sixth pulse width signal to the second switch in the third buck-boost module and an eighth pulse width signal to the second switch in the fourth buck-boost module, respectively.

[0021] Further, in the bidirectional DC / DC converter, the second timer is electrically connected to the first timer, and the first timer is further configured to trigger the second timer to count in the second counting period.

[0022] Further, in the bidirectional DC / DC converter, the first counting period is equal to the second counting period.

[0023] Further, in the bidirectional DC / DC converter, the time difference between the rising edge or / and the falling edge of the first pulse width signal and the fifth pulse width signal is equal to one fourth of the first counting period; or / and,

[0024] The time difference between the rising edge or / and the falling edge of the second pulse width signal and the sixth pulse width signal is equal to one fourth of the second counting period; or / and,

[0025] The time difference between the rising edge or / and the falling edge of the third pulse width signal and the seventh pulse width signal is equal to one fourth of the first counting period; or / and,

[0026] The time difference between the rising edge or / and the falling edge of the fourth pulse width signal and the eighth pulse width signal is equal to one fourth of the second counting period.

[0027] Further, in the bidirectional DC / DC converter, the second timer counts in an increasing manner in the first half of the second counting period and in a decreasing manner in the second half of the second counting period; or,

[0028] The second timer counts in a decreasing manner in the first half of the second counting period and in an increasing manner in the second half of the second counting period.

[0029] Further, in the bidirectional DC / DC converter, at least one of the first switch and the second switch is a MOS tube; or / and,

[0030] The control module is a digital signal processor.

[0031] The bidirectional DC / DC converter provided by the application comprises a bidirectional buck-boost circuit, a control module and a first timer. The buck-boost module comprises a first switch and a second switch which are alternately closed. The first timer is configured to trigger the control module to output a first pulse width signal and a second pulse width signal which are complementary to the first switch and the second switch within a first counting period. The time difference between the rising edge of the first pulse width signal and the falling edge of the second pulse width signal is greater than a first time, and the time difference between the falling edge of the first pulse width signal and the rising edge of the second pulse width signal is greater than a second time. Therefore, not only can the simultaneous conduction of the first switch and the second switch to form a short circuit be avoided, but also only one timer needs to be configured at the control module to ensure that the bidirectional DC / DC converter can be seamlessly and quickly converted between charging and discharging operations, thereby reducing the cost of the converter, avoiding program improvement of the control module and improving the reliability of the converter. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0033] Figure 1 The first structural diagram of the bidirectional DC / DC converter provided by the embodiment of the application;

[0034] Figure 2 The first flowchart of the pulse width signal modulation method provided by the embodiment of the application;

[0035] Figure 3 The first timing diagram of the bidirectional DC / DC converter provided by the embodiment of the application;

[0036] Figure 4 The second structural diagram of the bidirectional DC / DC converter provided by the embodiment of the application;

[0037] Figure 5 The second timing diagram of the bidirectional DC / DC converter provided by the embodiment of the application;

[0038] Figure 6 The third structural diagram of the bidirectional DC / DC converter provided by the embodiment of the application;

[0039] Figure 7 The second flowchart of the pulse width signal modulation method provided by the embodiment of the application;

[0040] Figure 8 The third timing diagram of the bidirectional DC / DC converter provided by the embodiment of the application. DETAILED DESCRIPTION

[0041] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort belong to the scope of protection of the present application.

[0042] It should be understood that the terms "comprising" and "including" as used in the specification and the appended claims indicate the presence of the described features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0043] It should also be understood that the terms used in the specification of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application. As used in the specification and the appended claims of the present application, the singular forms "a", "an" and "the" are intended to include the plural forms unless the context clearly indicates otherwise.

[0044] It should be further understood that the term "and / or" used in the specification and the appended claims of the present application means any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0045] Please refer to Figure 1 , Figure 1 The first structural diagram of a bidirectional DC / DC converter provided by the embodiments of the present application is shown.

[0046] As Figure 1 shown, a bidirectional DC / DC converter comprises:

[0047] a first input terminal Vin+, a second input terminal Vin-, a first output terminal Vout+ and a second output terminal Vout-;

[0048] a bidirectional buck-boost circuit comprising at least one buck-boost module 100, the buck-boost module 100 comprising a first switch and a second switch, a first end of the first switch being electrically connected to the first input terminal Vin+, a second end of the first switch being electrically connected to the first output terminal Vout+, a first end of the second switch being electrically connected to the first output terminal Vout+ of the bidirectional buck-boost circuit, and a second end of the second switch being electrically connected to the second input terminal Vin- and the second output terminal Vout- of the bidirectional buck-boost circuit, respectively;

[0049] a control module 200 electrically connected to a control end of the first switch and a control end of the second switch, respectively;

[0050] The first timer 300 is electrically connected to the control module 200, and the first timer 300 is configured to trigger the control module 200 to output a first pulse width signal to the control end of the first switch within a preset first counting period; or / and output a second pulse width signal to the control end of the second switch within the first counting period.

[0051] The first pulse width signal and the second pulse width signal are complementary, and the time difference between the rising edge of the first pulse width signal and the falling edge of the second pulse width signal is greater than a preset first time t1; or / and the time difference between the falling edge of the first pulse width signal and the rising edge of the second pulse width signal is greater than a preset second time t2.

[0052] Specifically, the control module 200 outputs the first pulse width signal to the control end of the first switch to control the on-off of the first switch, and at the same time, the control module 200 outputs the second pulse width signal to the control end of the second switch to control the on-off of the second switch. At least one of the first pulse width signal and the second pulse width signal is triggered by the first timer 300 to control the control module 200 to output, and the application preferably triggers the control module 200 to output both the first pulse width signal and the second pulse width signal by the first timer 300. The control module can be a digital signal processor (Digital Signal Processing, DSP).

[0053] Please refer to Figure 1 The first switch can be a MOS tube Q1, and the second switch can be a MOS tube Q2. The gate of the MOS tube Q1 serves as the control end of the first switch and is electrically connected to the control module 200. The source of the MOS tube Q1 is electrically connected to the first input end Vin+ through the inductor L1. The drain of the MOS tube Q1 is electrically connected to the first output end Vout+. The first output end Vout+ and the third end are provided with a capacitor C1. The gate of the MOS tube Q2 serves as the control end of the second switch and is electrically connected to the control module 200. The source of the MOS tube Q2 is electrically connected to the first output end Vout+. The drain of the MOS tube Q2 is electrically connected to the second input end Vin- and the second output end Vout-.

[0054] It should be noted that the first input end Vin+, the second input end Vin-, the first output end Vout+ and the second output end Vout- mentioned in the application do not represent that the current flows from the first input end Vin+, the second input end Vin- to the first output end Vout+ and the second output end Vout-. When the DC / DC converter is switched from one of the boost mode and the buck mode to the other mode, the current can flow from the first output end Vout+ and the second output end Vout- to the first input end Vin+ and the second input end Vin-.

[0055] In some embodiments, asFigure 2 As shown, the application also provides a pulse width signal modulation method, which comprises steps S110 and S120.

[0056] S110, generating a triangular carrier wave by using a first timer in a first counting period;

[0057] S120, modulating a first pulse width signal and a second pulse width signal at a preset first counting value based on the triangular carrier wave.

[0058] Specifically, the first pulse width signal PWM_1 and the second pulse width signal PWM_2 can both be level signals, and the first pulse width signal PWM_1 and the second pulse width signal PWM_2 are complementary. For example, Figure 3 As shown, in the working process of the bidirectional DC / DC converter, when the first pulse width signal PWM_1 is modulated as a high level signal and the second pulse width signal PWM_21 is modulated as a low level signal, the first switch in the buck-boost module 100 is turned on and the second switch in the buck-boost module 100 is turned off; when the first pulse width signal PWM_11 is modulated as a low level signal and the second pulse width signal PWM_21 is modulated as a high level signal, the first switch in the buck-boost module 100 is turned off and the second switch in the buck-boost module 100 is turned on, thereby enabling the bidirectional DC / DC converter to work in a boost mode or a buck mode, so as to realize the bidirectional flow of current.

[0059] The bidirectional DC / DC converter provided in the application comprises a first input end Vin+, a second input end Vin-, a first output end Vout+, a second output end Vout-, a bidirectional buck-boost circuit, a control module 200 and a first timer 300. The bidirectional buck-boost circuit comprises at least one buck-boost module 100. The buck-boost module 100 comprises a first switch and a second switch. The first end of the first switch is electrically connected to the first input end Vin+. The second end of the first switch and the first end of the second switch are electrically connected to the first output end Vout+. The second end of the second switch is electrically connected to the second input end Vin- and the second output end Vout- respectively. The control module 200 is electrically connected to the control ends of the first switch and the second switch respectively. The first timer 300 is electrically connected to the control module 200 and is configured to trigger the control module 200 to output complementary first and second pulse width signals to control the on-off of the first switch and the second switch within a first counting period. The time difference between the rising edge of the first pulse width signal and the falling edge of the second pulse width signal is greater than a first time t1. The time difference between the falling edge of the first pulse width signal and the rising edge of the second pulse width signal is greater than a second time t2. The bidirectional DC / DC converter can not only avoid the simultaneous conduction of the first switch and the second switch to form a short circuit, but also can ensure that the bidirectional DC / DC converter can realize seamless and fast conversion between charging and discharging operations only by configuring a timer at the control module 200, thereby reducing the cost of the converter, avoiding the program improvement of the control module 200 and improving the reliability of the converter.

[0060] In some embodiments, as shown in FIG. 1, Figure 3 In some embodiments, as shown in FIG. 1,

[0061] In the embodiment, if the first target counting value of the first timer 300 is greater than or equal to a preset first counting value a1 and less than or equal to a preset second counting value a2, the first pulse width signal PWM_11 is modulated as a preset first level signal and the second pulse width signal PWM_21 is modulated as a preset second level signal. If the first target counting value is greater than or equal to a preset third counting value a3 and less than or equal to a preset fourth counting value a4, the first pulse width signal PWM_11 is modulated as the second level signal and the second pulse width signal PWM_21 is modulated as the first level signal. The first level signal and the second level signal can be high level signals or low level signals. The first counting value a1 can be 0. The fourth counting value a4 can be the maximum counting value of the first timer 300. The sum of the second counting value a2 and the fifth counting value a5 is equal to one half of the first counting period.

[0062] Furthermore, the second count value a2 is smaller than the third count value a3, thereby achieving a time difference between a rising edge of the first pulse-width signal PWM_1 and a falling edge of the second pulse-width signal PWM_2 greater than a preset first time t1, and a time difference between a falling edge of the first pulse-width signal PWM_1 and a rising edge of the second pulse-width signal PWM_2 greater than a preset second time t2, thereby forming a dead interval, thereby preventing the first switch and the second switch from being turned on at the same time to form a short circuit.

[0063] In some embodiments, step S120 may include the following steps: if the first target count value of the first timer 300 is greater than or equal to the first count value a1 and less than or equal to a preset second count value a2, modulating the first pulse width signal PWM_1 into a high-level signal; if the first target count value of the first timer 300 is greater than or equal to the first count value a1 and less than or equal to a preset third count value a3, modulating the second pulse width signal PWM_2 into a low-level signal; wherein the third count value a3 is greater than the second count value a2; if the first target count value of the first timer 300 is greater than the second count value a2 and less than or equal to a preset fourth count value a4, modulating the first pulse width signal PWM_1 into a low-level signal; if the first target count value of the first timer 300 is greater than the third count value a3 and less than or equal to the fourth count value a4, modulating the second pulse width signal PWM_2 into a high-level signal.

[0064] In this embodiment, the first count value a1 can be the count value at the initial moment in the first counting cycle, the second count value a2 corresponds to the first time t1 and the second time t2 in the first counting cycle, and the third count value a3 corresponds to the third time t3 and the fourth time t4 in the first counting cycle; the first time t1 is less than the third time t3, the third time t3 is less than the fourth time t4, and the fourth time t4 is less than the second time t2.

[0065] In some embodiments, the first timer 300 may further count down in the first half of the first counting period, and count up in the second half of the first counting period.

[0066] In some embodiments, as Figure 4 As shown, the bidirectional buck-boost circuit includes two buck-boost modules 100 connected in parallel; wherein, the first timer 300 is configured to trigger the control module 200 to output at least one first control signal within a first counting cycle; or / and, within the first counting cycle, trigger the control module 200 to output at least one second control signal.

[0067] Specifically, in order to reduce the current ripple in the bidirectional DC / DC converter, the application can also be provided with two parallel buck-boost modules 100 in the bidirectional buck-boost circuit, the two buck-boost modules being a first buck-boost module and a second buck-boost module, and each of the two buck-boost modules 100 being provided with a first switch and a second switch, wherein the first switch and the second switch of one of the buck-boost modules 100 can be MOS tube Q1 and MOS tube Q2, the first switch and the second switch of the other buck-boost module 100 can be MOS tube Q3 and MOS tube Q4, the gate of MOS tube Q3 is electrically connected to the control module 200, the source of MOS tube Q3 is electrically connected to the first input end Vin+ through inductor L2, the drain of MOS tube Q3 is electrically connected to the first output end Vout+, the first output end Vout+ and the third end are provided with capacitor C2, the gate of MOS tube Q4 is electrically connected to the control module 200, the source of MOS tube Q4 is electrically connected to the first output end Vout+, and the drain of MOS tube Q4 is electrically connected to the second input end Vin- and the second output end Vout- respectively.

[0068] In some embodiments, the first timer 300 is configured to trigger the control module 200 to output two first pulse width signals (first pulse width signal and third pulse width signal respectively) and two second pulse width signals (second pulse width signal and fourth pulse width signal respectively) respectively within a first counting period.

[0069] Specifically, as shown in Figure 5 the first timer 300 is configured to trigger the control module 200 to output the first pulse width signal PWM_1 to the control end of the first switch in the first buck-boost module, output the third pulse width signal PWM_3 to the control end of the first switch in the second buck-boost module, output the second pulse width signal PWM_2 to the control end of the second switch in the first buck-boost module, and output the fourth pulse width signal PWM_4 to the control end of the second switch in the second buck-boost module within the first counting period.

[0070] Further, as shown in Figure 5 the time difference between the rising edge of the first pulse width signal and the rising edge of the third pulse width signal is equal to half of the first counting period; the time difference between the falling edge of the first pulse width signal and the falling edge of the third pulse width signal is equal to half of the first counting period; the time difference between the rising edge of the second pulse width signal and the rising edge of the fourth pulse width signal is equal to half of the first counting period; and the time difference between the falling edge of the second pulse width signal and the falling edge of the fourth pulse width signal is equal to half of the first counting period.

[0071] In the embodiment, the pulse width signals corresponding to the two first switches in the bidirectional buck-boost circuit can be the first pulse width signal PWM_1 and the third pulse width signal PWM_3, the pulse width signals corresponding to the two second switches in the bidirectional buck-boost circuit can be the second pulse width signal PWM_2 and the fourth pulse width signal PWM_4, the first pulse width signal PWM_1 and the second pulse width signal PWM_2 can be modulated into a set of complementary level signals with dead zones, and the third pulse width signal PWM_3 and the fourth pulse width signal PWM_4 can be modulated into another set of complementary level signals with dead zones.

[0072] As shown in Figure 4 , when the third pulse width signal PWM_3 and the fourth pulse width signal PWM_4 are modulated into high-level signals and low-level signals respectively, the MOS tube Q3 is turned on and the MOS tube Q4 is turned off; when the third pulse width signal PWM_3 and the fourth pulse width signal PWM_4 are modulated into low-level signals and high-level signals respectively, the MOS tube Q3 is turned off and the MOS tube Q4 is turned on, thereby making the two inductance current waveforms of the two parallel buck-boost modules 100 have a phase difference of 180 degrees, so that the ripple size of the total current of the bidirectional DC / DC converter can be reduced after the two-way ripple is staggered and superimposed, and the performance and reliability of the bidirectional DC / DC converter are improved.

[0073] In some embodiments, the application also provides a pulse width signal modulation method, which comprises the steps of: generating a triangular carrier using a first timer 300 within a first counting period; and modulating the first pulse width signal, the second pulse width signal, the third pulse width signal and the fourth pulse width signal based on the triangular carrier at a preset first counting value a1.

[0074] Specifically, as shown in Figure 5 , the first pulse width signal PWM_1, the second pulse width signal PWM_2, the third pulse width signal PWM_3 and the fourth pulse width signal PWM_4 can all be level signals, and the first pulse width signal PWM_1 and the second pulse width signal PWM_2 are modulated to be complementary, and the third pulse width signal PWM_3 and the fourth pulse width signal PWM_4 are modulated to be complementary.

[0075] During operation of the bidirectional DC / DC converter, when the first pulse width signal PWM_1 is modulated to a high level signal and the second pulse width signal PWM_2 is modulated to a low level signal, the first switch in the buck-boost module 100 is turned on and the second switch in the buck-boost module 100 is turned off; when the first pulse width signal PWM_1 is modulated to a low level signal and the second pulse width signal PWM_2 is modulated to a high level signal, the first switch in the buck-boost module 100 is turned off and the second switch in the buck-boost module 100 is turned on; when the third pulse width signal PWM_3 is modulated to a high level signal, When the fourth pulse-width signal PWM_4 is modulated to a low-level signal, the other first switch in the buck-boost module 100 is turned on, and the other second switch in the buck-boost module 100 is turned off. When the third pulse-width signal PWM_3 is modulated to a low-level signal, and the fourth pulse-width signal PWM_4 is modulated to a high-level signal, the other first switch in the buck-boost module 100 is turned off, and the other second switch in the buck-boost module 100 is turned on. This allows the bidirectional DC / DC converter to operate in either boost or buck mode, thereby achieving bidirectional current flow. Furthermore, a 180-degree phase difference exists between the two sets of pulse-width signals, resulting in a 180-degree phase difference between the two inductor current waveforms. The interleaving and superposition of the two ripples can reduce the ripple of the total current, thereby improving the performance and reliability of the bidirectional DC / DC converter.

[0076] In some embodiments, as Figure 5 As shown, the first timer 300 is further configured such that, within a first counting period, the trigger control module 200 outputs a third pulse width signal PWM_3 to the MOS transistor Q3 and a fourth pulse width signal PWM_4 to the MOS transistor Q4; if the first target count value is greater than or equal to a preset fifth count value a5, the first pulse width signal PWM_3 is a preset first level signal, the second pulse width signal PWM_4 is a preset second level signal, and the fifth count value a5 is less than the fourth count value a4; if the first target count value is greater than or equal to the first count value a1 and less than or equal to a preset sixth count value a6, the first pulse width signal PWM_3 is a second level signal, the second pulse width signal PWM_4 is a first level signal; the fifth count value a5 is less than the fourth count value a4, and the sixth count value a6 is less than the fifth count value a5 and greater than the third count value a3.

[0077] Furthermore, starting to modulate the third pulse width signal and the fourth pulse width signal at the preset first count value a1 may include: if the first target count value of the first timer 300 is greater than or equal to the first count value a1 and less than the preset fifth count value a5, modulating the third pulse width signal to a low level signal; if the first target count value of the first timer 300 is greater than or equal to the first count value a1 and less than the preset sixth count value a6, modulating the fourth pulse width signal to a high level; wherein the fifth count value a5 is greater than the sixth count value a6; if the first target count value of the first timer 300 is greater than the fifth count value a5 and less than or equal to the preset fourth count value, modulating the third pulse width signal to a high level signal; if the first target count value of the first timer 300 is greater than the sixth count value a6 and less than or equal to the fourth count value, modulating the fourth pulse width signal to a low level signal.

[0078] In this embodiment, the fifth count value a5 corresponds to a fifth time t5 and a sixth time t6 within the first counting cycle, and the sixth count value a6 corresponds to a seventh time t7 and an eighth time t8 within the counting cycle. The fifth time t5 is greater than the seventh time t7 and less than the sixth time t6, and the sixth time t6 is less than the eighth time t8. The time difference between the first time t1 and the sixth time t6 is equal to half the first counting cycle, the time difference between the third time t3 and the eighth time t8 is equal to half the first counting cycle, the time difference between the seventh time t7 and the fourth time t4 is equal to half the first counting cycle, and the time difference between the fifth time t5 and the second time t2 is equal to half the first counting cycle.

[0079] In some embodiments, as Figure 6 As shown, the bidirectional DC / DC converter also includes a second timer 400 electrically connected to the control module 200, and the bidirectional buck-boost circuit includes four buck-boost modules 100 connected in parallel; wherein the second timer 400 is configured to trigger the control module 200 to output at least one first pulse width signal within a preset second counting period; or / and, trigger the control module 200 to output at least one second pulse width signal within the second counting period.

[0080] Specifically, in order to further reduce the current ripple in the bidirectional DC / DC converter, the application can also be provided with four parallel buck-boost modules 100 in the bidirectional buck-boost circuit, the four buck-boost modules being a first buck-boost module, a second buck-boost module, a third buck-boost module and a fourth buck-boost module, and the four buck-boost modules 100 are each provided with a first switch and a second switch, the first switch and the second switch of the first buck-boost module 100 can be MOS tube Q1 and MOS tube Q2, the first switch and the second switch of the second buck-boost module 100 can be MOS tube Q3 and MOS tube Q4, the first switch and the second switch of the third buck-boost module 100 can be MOS tube Q5 and MOS tube Q6, and the first switch and the second switch of the fourth buck-boost module 100 can be MOS tube Q7 and MOS tube Q8.

[0081] The gate of the MOS tube Q5 is electrically connected to the control module 200, the source of the MOS tube Q5 is electrically connected to the first input end Vin+ through the inductor L3, the drain of the MOS tube Q5 is electrically connected to the first output end Vout+, and the first output end Vout+ and the third end are provided with the capacitor C3. The gate of the MOS tube Q6 is electrically connected to the control module 200, the source of the MOS tube Q6 is electrically connected to the first output end Vout+, and the drain of the MOS tube Q6 is electrically connected to the second input end Vin- and the second output end Vout-.

[0082] The gate of the MOS tube Q7 is electrically connected to the control module 200, the source of the MOS tube Q7 is electrically connected to the first input end Vin+ through the inductor L4, the drain of the MOS tube Q7 is electrically connected to the first output end Vout+, and the first output end Vout+ and the third end are provided with the capacitor C4. The gate of the MOS tube Q8 is electrically connected to the control module 200, the source of the MOS tube Q8 is electrically connected to the first output end Vout+, and the drain of the MOS tube Q8 is electrically connected to the second input end Vin- and the second output end Vout-.

[0083] In some embodiments, as shown in Figure 6 The second timer 400 is electrically connected to the first timer 300, and the first timer 300 is further configured to trigger the second timer 400 to count in the second counting period.

[0084] In the embodiment, the first timer 300 can be a master timer in the bidirectional DC / DC converter, the second timer 400 can be a slave timer in the bidirectional DC / DC converter, and after the first timer 300 counts for a period of time, the second timer 400 can be triggered to start counting in a second counting period thereof, so as to trigger the master control module to output two groups of first and second pulse width signals again (one group is the fifth and seventh pulse width signals, and the other group is the sixth and eighth pulse width signals), so that the master control module can output four groups of pulse width signals. As shown in Figure 8 the four groups of pulse width signals are respectively a group of first and second pulse width signals PWM_1 and PWM_2, a group of third and fourth pulse width signals PWM_3 and PWM_4, a group of fifth and sixth pulse width signals PWM_5 and PWM_6, and a group of seventh and eighth pulse width signals PWM_7 and PWM_8.

[0085] In some embodiments, as shown in Figure 7 the application also provides a pulse width signal modulation method, which comprises steps S210 and S220.

[0086] S210, if the first target counting value of the first timer is counted from a first counting value to a preset seventh counting value, the second timer is triggered to generate a triangular carrier in a preset second counting period;

[0087] S220, based on the triangular carrier, modulating preset fifth, sixth, seventh and eighth pulse width signals at a preset eighth counting value.

[0088] Specifically, as shown in Figure 8 the first, second, third, fourth, fifth, sixth, seventh and eighth pulse width signals PWM_1, PWM_2, PWM_3, PWM_4, PWM_5, PWM_6, PWM_7 and PWM_8 can all be level signals, and the first and second pulse width signals PWM_1 and PWM_2 are modulated to be complementary, the third and fourth pulse width signals PWM_3 and PWM_4 are modulated to be complementary, the fifth and sixth pulse width signals PWM_5 and PWM_6 are modulated to be complementary, and the seventh and eighth pulse width signals PWM_7 and PWM_8 are modulated to be complementary.

[0089] When the first pulse width signal PWM_1 is modulated as a high level signal and the second pulse width signal PWM_2 is modulated as a low level signal, the first switch in the first buck-boost module 100 is turned on and the second switch in the first buck-boost module 100 is turned off; when the first pulse width signal PWM_1 is modulated as a low level signal and the second pulse width signal PWM_2 is modulated as a high level signal, the first switch in the first buck-boost module 100 is turned off and the second switch in the first buck-boost module 100 is turned on.

[0090] When the third pulse width signal PWM_3 is modulated as a high level signal and the fourth pulse width signal PWM_4 is modulated as a low level signal, the first switch in the second buck-boost module 100 is turned on and the second switch in the second buck-boost module 100 is turned off; when the third pulse width signal PWM_3 is modulated as a low level signal and the fourth pulse width signal PWM_4 is modulated as a high level signal, the first switch in the second buck-boost module 100 is turned off and the second switch in the second buck-boost module 100 is turned on.

[0091] When the fifth pulse width signal PWM_5 is modulated as a high level signal and the sixth pulse width signal PWM_6 is modulated as a low level signal, the first switch in the third buck-boost module 100 is turned on and the second switch in the third buck-boost module 100 is turned off; when the fifth pulse width signal PWM_5 is modulated as a low level signal and the sixth pulse width signal PWM_6 is modulated as a high level signal, the first switch in the third buck-boost module 100 is turned off and the second switch in the third buck-boost module 100 is turned on.

[0092] When the seventh pulse width signal PWM_7 is modulated as a high level signal and the eighth pulse width signal PWM_8 is modulated as a low level signal, the first switch in the fourth buck-boost module 100 is turned on and the second switch in the fourth buck-boost module 100 is turned off; when the seventh pulse width signal PWM_7 is modulated as a low level signal and the eighth pulse width signal PWM_8 is modulated as a high level signal, the first switch in the fourth buck-boost module 100 is turned off and the second switch in the fourth buck-boost module 100 is turned on, so that the bidirectional DC / DC converter can work in the boost mode and also work in the buck mode, thereby realizing the bidirectional flow of current.

[0093] Meanwhile, there is a 90-degree phase difference between the first pulse width signal PWM_1 and the fifth pulse width signal PWM_5, between the second pulse width signal PWM_2 and the sixth pulse width signal PWM_6, between the third pulse width signal PWM_3 and the seventh pulse width signal PWM_7, and between the fourth pulse width signal PWM_4 and the eighth pulse width signal PWM_8, so that the four inductance current waveforms have a 90-degree phase difference, and the total current ripple can be reduced after the four inductance current waveforms are superimposed, thereby improving the performance and reliability of the bidirectional DC / DC converter.

[0094] In some embodiments, the first timer 300 is configured to trigger the control module 200 to output the first pulse width signal PWM_1, the second pulse width signal PWM_2, the third pulse width signal PWM_3, and the fourth pulse width signal PWM_4 respectively within a first counting period; and the second timer 400 is configured to trigger the control module 200 to output the fifth pulse width signal PWM_5, the sixth pulse width signal PWM_6, the seventh pulse width signal PWM_7, and the eighth pulse width signal PWM_8 respectively within a second counting period.

[0095] In the embodiment, the first counting period is equal to the second counting period. If the first target count value reaches a preset seventh count value a7, the second timer 400 starts counting within the second counting period, and the time difference between the seventh count value a7 and the fourth count value a4 is equal to one fourth of the first counting period. If the second target count value of the second timer 400 is greater than or equal to a preset eighth count value a8 and less than or equal to a preset ninth count value a9, the fifth pulse width signal PWM_5 is modulated as the first level signal, and the sixth pulse width signal PWM_6 is modulated as the second level signal. If the second target count value is greater than or equal to a preset tenth count value a10 and less than or equal to a preset eleventh count value a11, the fifth pulse width signal PWM_5 is modulated as the second level signal, and the sixth pulse width signal PWM_6 is modulated as the first level signal. If the second target count value is greater than or equal to a preset twelfth count value a12, the seventh pulse width signal PWM_7 is modulated as the first level signal, and the eighth pulse width signal PWM_8 is modulated as the second level signal, and the twelfth count value a12 is less than the eleventh count value a11. If the second target count value is greater than or equal to the seventh count value a7 and less than or equal to a preset thirteenth count value a13, the seventh pulse width signal PWM_7 is modulated as the second level signal, and the eighth pulse width signal PWM_8 is modulated as the first level signal.

[0096] The ninth count value a9 is smaller than the tenth count value a10, the twelfth count value a12 is smaller than the eleventh count value a11, the thirteenth count value a13 is smaller than the twelfth count value a12 and larger than the tenth count value a10, and the seventh count value a7 may be a quarter of the first count cycle or half of the second count cycle.

[0097] At the same time, the ninth count value a9 corresponds to a ninth time t9 and a tenth time t10 in the first counting cycle, and the tenth count value a10 corresponds to an eleventh time t11 and a twelfth time t12 in the first counting cycle; the ninth time t9 is less than the eleventh time t11, the eleventh time t11 is less than the twelfth time t12, and the twelfth time t12 is less than the tenth time t10; the twelfth count value a12 corresponds to a thirteenth time t13 and a fourteenth time t14 in the first counting cycle, and the thirteenth count value a13 corresponds to a fifteenth time t15 and a sixteenth time t16 in the first counting cycle; the thirteenth time t13 is greater than the fifteenth time t15 and less than the fourteenth time t14, and the fourteenth time t14 is less than the sixteenth time t16.

[0098] Furthermore, in some embodiments, Figure 8 As shown, the time difference between the rising edge of the first pulse width signal and the rising edge of the fifth pulse width signal is equal to one-quarter of the first counting cycle; the time difference between the falling edge of the first pulse width signal and the falling edge of the fifth pulse width signal is equal to one-quarter of the first counting cycle; the time difference between the rising edge of the second pulse width signal and the rising edge of the sixth pulse width signal is equal to one-quarter of the second counting cycle; the time difference between the falling edge of the second pulse width signal and the falling edge of the sixth pulse width signal is equal to one-quarter of the second counting cycle; the time difference between the rising edge of the third pulse width signal and the rising edge of the seventh pulse width signal is equal to one-quarter of the first counting cycle; the time difference between the falling edge of the third pulse width signal and the falling edge of the seventh pulse width signal is equal to one-quarter of the first counting cycle; the time difference between the rising edge of the fourth pulse width signal and the rising edge of the eighth pulse width signal is equal to one-quarter of the second counting cycle; and the time difference between the falling edge of the fourth pulse width signal and the falling edge of the eighth pulse width signal is equal to one-quarter of the second counting cycle.

[0099] In the embodiment, when the first target count value of the first timer 300 is less than or equal to the second count value a2, the first pulse width signal PWM_1 is modulated as a high level signal, and the second pulse width signal PWM_2 is modulated as a low level signal; when the first target count value of the first timer 300 is greater than or equal to the second count value a2, the first pulse width signal PWM_1 is modulated as a low level signal, and the second pulse width signal PWM_2 is modulated as a high level signal, thereby a set of complementary PWM waveforms can be outputted; when the first target count value of the first timer 300 is less than or equal to the fifth count value a5, the third pulse width signal PWM_3 is modulated as a high level signal, and the fourth pulse width signal PWM_4 is modulated as a low level signal; when the first target count value of the first timer 300 is greater than or equal to the fifth count value a5, the third pulse width signal PWM_3 is modulated as a low level signal, and the fourth pulse width signal PWM_4 is modulated as a high level signal, thereby a set of complementary PWM waveforms can also be outputted.

[0100] The sum of the second count value a2 and the fifth count value a5 is equal to one half of the first count period, and thus the time difference between the third pulse width signal PWM_3 and the first pulse width signal PWM_1 can be T / 2, which is converted into a phase difference of 180 degrees; when the first target count value of the first timer 300 is equal to the seventh count value a7, since the seventh count value a7 can be one fourth of the first count period or half of the second count period, the first timer 300 can trigger the second timer 400 to start counting.

[0101] When the second target count value of the second timer 400 is less than or equal to the ninth count value a9, the fifth pulse width signal PWM_5 is modulated as a high level signal, and the sixth pulse width signal PWM_6 is modulated as a low level signal; when the second target count value of the second timer 400 is greater than or equal to the ninth count value a9, the fifth pulse width signal PWM_5 is modulated as a low level signal, and the sixth pulse width signal PWM_6 is modulated as a high level signal, thereby a set of complementary PWM waveforms can be outputted; since the seventh count value a7 can be one fourth of the first count period or half of the second count period, the time difference between the fifth pulse width signal PWM_5 and the first pulse width signal PWM_1 is T / 4, which is converted into a phase difference of 90 degrees.

[0102] When the second target count value of the second timer 400 is less than or equal to the twelfth count value a12, the seventh pulse width signal PWM_7 is modulated as a high level signal, and the eighth pulse width signal PWM_8 is modulated as a low level signal; when the real-time count is greater than or equal to the twelfth count value a12, the seventh pulse width signal PWM_7 is modulated as a low level signal, and the eighth pulse width signal PWM_8 is modulated as a high level signal, thereby a set of complementary PWM waveforms can be outputted.

[0103] Wherein, the seventh count value a7 and the ninth count value a9 added together equals half of the second count period, the time difference between the seventh pulse width signal PWM_7 and the third pulse width signal PWM_3 is half of the second count period, which is converted into phase difference is 180 degrees.

[0104] In summary, there is 90 degrees phase difference between the first pulse width signal PWM_1 and the second pulse width signal PWM_2 and the fifth pulse width signal PWM_5 and the sixth pulse width signal PWM_6, there is 90 degrees phase difference between the third pulse width signal PWM_3 and the fourth pulse width signal PWM_4 and the seventh pulse width signal PWM_7 and the eighth pulse width signal PWM_8, there is 180 degrees phase difference between the first pulse width signal PWM_1 and the second pulse width signal PWM_2 and the third pulse width signal PWM_3 and the fourth pulse width signal PWM_4, there is 180 degrees phase difference between the fifth pulse width signal PWM_5 and the sixth pulse width signal PWM_6 and the seventh pulse width signal PWM_7 and the eighth pulse width signal PWM_8, so that the four groups of pulse width signals form the complementary PWM waveforms with staggered phase shift of 90 degrees.

[0105] In some embodiments, the second timer 400 counts up in the first half of the second count period and counts down in the second half of the second count period, so that the second timer 400 generates a triangular carrier wave with a first count period of T and an amplitude of T / 2.

[0106] In the present embodiment, the first timer 300 counts up in the first half of the first count period and counts down in the second half of the first count period, and the second timer 400 counts up in the first half of the second count period and counts down in the second half of the second count period, so that the first timer 300 and the second timer 400 can both generate a triangular carrier wave with a first count period of T and an amplitude of T / 2.

[0107] Further, the preset fifth, sixth, seventh and eighth pulse width signals are modulated starting from the seventh count value a7, including the following steps: if the second target count value of the second timer 400 is greater than or equal to the eighth count value a8 and less than or equal to a preset ninth count value a9, the fifth pulse width signal is modulated as a high level signal; if the second target count value of the second timer 400 is greater than or equal to the eighth count value a8 and less than or equal to a preset tenth count value a10, the sixth pulse width signal is modulated as a low level signal; wherein the tenth count value a10 is greater than the ninth count value a9; if the second target count value of the second timer 400 is greater than the ninth count value a9 and less than or equal to a preset eleventh count value a11, the fifth pulse width signal is modulated as a low level signal; if the second target count value of the second timer 400 is greater than the tenth count value a10 and less than or equal to the eleventh count value a11, the sixth pulse width signal is modulated as a high level signal; if the second target count value of the second timer 400 is greater than or equal to the eighth count value a8 and less than a preset twelfth count value a12, the preset seventh pulse width signal is modulated as a low level signal; if the second target count value of the second timer 400 is greater than or equal to the eighth count value a8 and less than a preset thirteenth count value a13, the preset eighth pulse width signal is modulated as a high level; wherein the twelfth count value a12 is greater than the thirteenth count value a13; if the second target count value of the second timer 400 is greater than the twelfth count value a12 and less than or equal to the eleventh count value a11, the seventh pulse width signal is modulated as a high level signal; if the second target count value of the second timer 400 is greater than the thirteenth count value a13 and less than or equal to the eleventh count value a11, the eighth pulse width signal is modulated as a low level signal.

[0108] Specifically, the modulation process of the four groups of pulse width signals generated by the present application can be:

[0109] Starting from 0, the first timer 300 generates a triangular carrier, adopts a center-symmetric counting method, and assumes that 1 ns is counted once, and the count value is T / 2, that is, it is first counted from 0 to T / 2, and then counted from T / 2 to 0, so that the quarter period time of the triangular carrier is T / 4, the half period time is T / 2, and the period time is T (ns). When the first target count value of the first timer 300 is less than the second count value a2, the first pulse width signal PWM_1 is modulated as a high level signal, and the second pulse width signal PWM_2 is modulated as a low level signal; when the first target count value of the first timer 300 is greater than or equal to the second count value a2, the first pulse width signal PWM_1 is modulated as a low level signal, and the second pulse width signal PWM_2 is modulated as a high level signal.

[0110] The sum of the second count value a2 and the fifth count value a5 is equal to one half of the first count period, so the time difference between the third pulse width signal PWM_3 and the first pulse width signal PWM_1 can be T / 2, which is converted into a phase difference of 180 degrees; when the first target count value of the first timer 300 is equal to the seventh count value a7, since the seventh count value a7 can be one fourth of the first count period or half of the second count period, the first timer 300 can trigger the second timer 400 to start counting.

[0111] When the second target count value of the second timer 400 is less than the ninth count value a9, the fifth pulse width signal PWM_5 is modulated as a high level signal and the sixth pulse width signal PWM_6 is modulated as a low level signal; when the second target count value of the second timer 400 is greater than or equal to the ninth count value a9, the fifth pulse width signal PWM_5 is modulated as a low level signal and the sixth pulse width signal PWM_6 is modulated as a high level signal.

[0112] When the first target count value of the first timer 300 is less than the fifth count value a5, the third pulse width signal PWM_3 is modulated as a high level signal and the fourth pulse width signal PWM_4 is modulated as a low level signal; when the first target count value of the first timer 300 is greater than or equal to the fifth count value a5, the third pulse width signal PWM_3 is modulated as a low level signal and the fourth pulse width signal PWM_4 is modulated as a high level signal.

[0113] When the second target count value of the second timer 400 is less than the twelfth count value a12, the seventh pulse width signal PWM_7 is modulated as a high level signal and the eighth pulse width signal PWM_8 is modulated as a low level signal; when the real-time count is greater than or equal to the twelfth count value a12, the seventh pulse width signal PWM_7 is modulated as a low level signal and the eighth pulse width signal PWM_8 is modulated as a high level signal.

[0114] In some embodiments, the second timer 400 counts down in the first half of the second count period and counts up in the second half of the second count period.

[0115] The above merely provides a specific implementation of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can easily think of various equivalent modifications or replacements within the technical range disclosed by the present application, and these modifications or replacements shall be encompassed within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A bidirectional DC / DC converter, characterized in that: include: a first input terminal, a second input terminal, a first output terminal, and a second output terminal; A bidirectional buck-boost circuit, comprising at least one buck-boost module, wherein the buck-boost module comprises a first switch and a second switch, wherein a first end of the first switch is electrically connected to the first input end, a second end of the first switch is electrically connected to the first output end, a first end of the second switch is electrically connected to the first output end, and a second end of the second switch is electrically connected to the second input end and the second output end, respectively; a control module, electrically connected to a control end of the first switch and a control end of the second switch; a first timer electrically connected to the control module, the first timer being configured to, within a preset first counting period, trigger the control module to output a first pulse width signal to the control end of the first switch; or / and, within the first counting period, to output a second pulse width signal to the control end of the second switch; In which, the first pulse width signal and the second pulse width signal are complementary, and the time difference between the rising edge of the first pulse width signal and the falling edge of the second pulse width signal is greater than a preset first time; or / and, the time difference between the falling edge of the first pulse width signal and the rising edge of the second pulse width signal is greater than a preset second time.

2. The bidirectional DC / DC converter according to claim 1, wherein: The first timer counts up in the first half of the first counting period and counts down in the second half of the first counting period; or, The first timer counts down in the first half of the first counting period, and counts up in the second half of the first counting period.

3. The bidirectional DC / DC converter according to claim 1, wherein: The bidirectional buck-boost circuit includes two buck-boost modules connected in parallel, the two buck-boost modules being a first buck-boost module and a second buck-boost module; The first timer is configured to, within the first counting period, trigger the control module to output the first pulse width signal to the control end of the first switch in the first buck-boost module, and to output a third pulse width signal to the control end of the first switch in the second buck-boost module; or / and, During the first counting period, the control module is triggered to output the second pulse width signal to the control end of the second switch in the first buck-boost module, and to output a fourth pulse width signal to the control end of the second switch in the second buck-boost module.

4. The bidirectional DC / DC converter according to claim 3, characterized in that: The time difference between the rising edge and / or the falling edge of the first pulse width signal and the third pulse width signal is equal to half of the first counting period; or / and, The time difference between the rising edge and / or the falling edge of the second pulse width signal and the fourth pulse width signal is equal to half of the first counting period.

5. The bidirectional DC / DC converter according to any one of claims 1 to 4, characterized in that: The bidirectional DC / DC converter further includes a second timer electrically connected to the control module, and the bidirectional buck-boost circuit includes four buck-boost modules connected in parallel, the four buck-boost modules being a first buck-boost module, a second buck-boost module, a third buck-boost module, and a fourth buck-boost module; The second timer is configured to trigger the control module to output a fifth pulse width signal to the first switch in the third buck-boost module and a seventh pulse width signal to the first switch in the fourth buck-boost module within a preset second counting period; or / and, In the second counting period, the control module is triggered to output a sixth pulse width signal to the second switch in the third buck-boost module and an eighth pulse width signal to the second switch in the fourth buck-boost module.

6. The bidirectional DC / DC converter according to claim 5, characterized in that: The second timer is electrically connected to the first timer, and the first timer is further configured to trigger the second timer to count within the second counting period.

7. The bidirectional DC / DC converter according to claim 5, characterized in that: The first counting period is equal to the second counting period.

8. The bidirectional DC / DC converter according to claim 7, characterized in that: The time difference between the rising edge and / or the falling edge of the first pulse width signal and the fifth pulse width signal is equal to one quarter of the first counting period; or / and, The time difference between the rising edge and / or the falling edge of the second pulse width signal and the sixth pulse width signal is equal to one quarter of the second counting period; or / and, The time difference between the rising edge or / and the falling edge of the third pulse width signal output by the control module and the seventh pulse width signal is equal to one quarter of the first counting period; or / and, The time difference between the rising edge and / or the falling edge of the fourth pulse width signal output by the control module and the eighth pulse width signal is equal to one quarter of the second counting period.

9. The bidirectional DC / DC converter according to claim 5, characterized in that: The second timer counts up in the first half of the second counting period and counts down in the second half of the second counting period; or, The second timer counts down in the first half of the second counting period, and counts up in the second half of the second counting period.

10. The bidirectional DC / DC converter according to any one of claims 1 to 4, characterized in that: At least one of the first switch and the second switch is a MOS transistor; or / and, The control module is a digital signal processor.

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