System for realizing high-speed internet access based on high-throughput tablet portable station
The high-throughput flat-panel portable station system solves the problems of large size and limited spectrum resources of traditional satellite communication terminal equipment, realizes portability and high-bandwidth Internet connection, and supports stable Internet access in various complex terrains.
Patent Information
- Application Number
- CN202422846291.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-21
- Publication Date
- 2025-10-17
- Estimated Expiration
- 2034-11-21
AI Technical Summary
Traditional satellite communication terminal equipment is large and heavy, making it difficult to carry. Spectrum resources are limited, resulting in restricted bandwidth and capacity expansion, making it impossible to provide stable, high-bandwidth Internet access services in the absence of mobile phone signals and terrestrial networks.
It adopts a system based on a high-throughput tablet portable station, including an antenna control unit, a microprocessor, a BD positioning module, an antenna attitude calculation unit, etc. Through modular design and battery power supply, it supports automatic satellite pointing and automatic tracking, and combines a modem and WiFi module to achieve high-speed Internet access.
It realizes a highly integrated device that is easy to carry, supports high-bandwidth Internet connection without mains power, and has the OpenAMIP protocol to shorten the time to join the network.
Smart Images
Figure CN223452049U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to satellite communication field, concretely relates to a kind of high flux flat panel portable station based on realization high-speed internet system. BACKGROUND
[0002] With the high-speed development of satellite communication technology and more and more extensive application in various fields, new requirements are put forward for satellite communication equipment and application to meet the application of different occasions. The traditional satellite communication terminal equipment is large in size and heavy in weight, which is not convenient to carry and use. Moreover, the frequency spectrum resources used by satellite communication are limited. With the continuous increase of satellite communication business, the competition for frequency spectrum resources is becoming increasingly fierce. In some frequency bands, spectrum congestion has occurred, which limits the bandwidth and capacity expansion of satellite communication systems. SUMMARY
[0003] The technical problem to be solved by the utility model is how to provide a system capable of realizing stable and high-bandwidth internet surfing service in the case of no mobile phone signal and ground network for various complex terrains.
[0004] To solve the above technical problem, the utility model adopts the technical scheme of a high-speed internet system based on high flux flat panel portable station, characterized by comprising an antenna control unit, the antenna control unit comprises a microprocessor, a BD positioning module and an antenna attitude solution unit, an output end of the BD positioning module is connected with an input end of the microprocessor, the BD positioning module is used to provide longitude and latitude information, an output end of the antenna attitude solution unit is connected with an input end of the microprocessor, the antenna control unit is connected with a motor through an output end of the microprocessor for driving the motor, the microprocessor is electrically connected with a bidirectional communication Modem, an output end of the Modem is connected with an input end of a BUC, an output end of the BUC is connected with an antenna, an output end of the antenna is connected with a feed source, an input end of an LNB is connected with the feed source, an output end is connected with the input end of a beacon machine and a Modem, an output end of the beacon machine is connected with an input end of the microprocessor, an output end of the microprocessor is connected with the motor, a power management module is connected with a lithium battery to control the lithium battery, the lithium battery is connected with a DC-DC module, the microprocessor is powered through an output end of the DC-DC module, an output port of the microprocessor is connected with an input port of the lithium battery, an output port of the microprocessor is connected with an input port of an OLED screen and a key, the microprocessor is bidirectionally connected with a WiFi module and an external storage unit, the WiFi module is bidirectionally connected with a monitoring system.
[0005] The beneficial effects produced by the above technical solutions are: the highly integrated and modularized equipment is more convenient to carry, has a battery power supply function, supports application without commercial power supply, has a short network access time, the product has an OpenAMIP protocol, can read and adjust antenna related parameters through a modem Web interface, supports ground private network communication and satellite high bandwidth communication. BRIEF DESCRIPTION OF DRAWINGS
[0006] The utility model will be further explained in detail in combination with the drawings and specific embodiments.
[0007] Figure 1 It is a high flux satellite flat portable station principle diagram provided by the utility model;
[0008] Figure 2 It is a principle diagram of the BD positioning module in the system of the embodiment of the utility model;
[0009] Figure 3 It is a principle diagram of the antenna attitude solution unit in the system of the embodiment of the utility model;
[0010] Figure 4 It is a principle diagram of the power management circuit in the system of the embodiment of the utility model Figure 1 ;
[0011] Figure 5 It is a principle diagram of the power management circuit in the system of the embodiment of the utility model Figure 2 ;
[0012] Figure 6 It is a principle diagram of the power management circuit in the system of the embodiment of the utility model Figure 3 ;
[0013] Figure 7 It is a principle diagram of the power management circuit in the system of the embodiment of the utility model Figure 4 ;
[0014] Figure 8 It is a principle diagram of the power management circuit in the system of the embodiment of the utility model Figure 5 ;
[0015] Figure 9 It is a principle diagram of the power management circuit in the system of the embodiment of the utility model Figure 6 . DETAILED DESCRIPTION
[0016] With reference to the drawings of the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, all the other embodiments obtained by those skilled in the art without creative labor fall within the scope of the present application.
[0017] With reference to Figure 1 The high-speed internet system based on high-flux panel portable station comprises an antenna control unit, the antenna control unit comprises a microprocessor, a BD positioning module and an antenna attitude solving unit, an output end of the BD positioning module is connected with an input end of the microprocessor, and the longitude and latitude provided by the Beidou and the longitude information of the satellite are transmitted to the microprocessor, the information of the attitude sensor is transmitted to the microprocessor through the output end of the antenna attitude solving unit after being processed, the information after being solved is transmitted to the microprocessor, the pitch and polarization required for the antenna to align with the satellite are calculated after coordinate conversion and solving, one output end of the microprocessor is connected with a motor through a 485 bus, and the motor is controlled to drive the antenna to move, one input end of the microprocessor is connected with an output end of a beacon machine, the satellite signal strength is received in real time, and the angle value of the highest level is recorded, and finally the satellite is aligned, and the automatic satellite alignment and automatic tracking are completed.
[0018] One output end of the microprocessor is connected with an input end of a Modem, the Modem modulates the signal transmitted by the microprocessor into an L frequency band, the Modem is a high-flux satellite modem, the Modem sends the network access signal, completes the network access after the approval of a gateway station, the Modem modulates and outputs the L frequency band signal, and after power amplification by a BUC, the signal is sent to the satellite by the high-flux panel antenna, transmitted to the gateway station after satellite relay, and the internet service is realized. The microprocessor is bidirectionally connected with a WiFi module and an external storage module, a user can connect a network cable or a device WiFi to connect the internet through an interface. Two output ends of the microprocessor are connected with an OLED screen and a key respectively, the user can view the satellite signal strength in real time through the OLED display screen, view the connection state of each module and related information through the interface operation of the key, and control the related basic module unit. The WiFi module is bidirectionally connected with a monitoring system, and the user can also control the monitoring system state and the related module unit after connecting the WiFi.
[0019] With reference to Figure 2The BD positioning module includes a GNSS IC (global navigation satellite system integrated circuit), an input end of the GNSS IC is connected with output ends of a SAW (surface acoustic wave), a TCXO (temperature compensated crystal oscillator), a Battery (power supply) and a RTC Crystal (real-time clock) respectively, an input end of the SAW is connected with an output end of an LNA (low noise amplifier), and an input end of the LNA is connected with an antenna; and the BD positioning module is bidirectionally connected with the microprocessor through a UART interface.
[0020] The antenna attitude solving unit refers to Figure 3 The sensor register is connected with an interrupt status register, a FIFO, a factory debugger, a configuration register, a main I2C serial interface, a digital motion processor, an input port, a frame synchronization signal interface, an I2C and SPI serial interface; the I2C and SPI serial interface is connected with a / CS interface, an AD0 interface, an SCL interface, an SDA interface and a serial interface bypass multiplexer; the main I2C serial interface is connected with the serial interface bypass multiplexer, and the serial interface bypass multiplexer is connected with AUX_CL and AUX_DA interfaces.
[0021] The antenna attitude solving unit refers to Figure 4 , 5, 6, 7, 8, 9, the power management module includes 3 SI7611DN field effect tube, 1 BQ24630RGET circuit management chip, 3 IPC100N4S5-5R5 field effect tube, 1 LTC4359IMS8 ideal diode controller, 1 LM5069 positive voltage hot plug controller, 1 LM5122 synchronous boost controller, 1 lithium battery;The drain electrode of U1 is divided into two ways, one way is connected with the output of adapter, one way is connected with resistance R6, the other end of R6 is connected with one end of capacitor C7, the other end of C7 is grounded;The source electrode of U1 is divided into two ways, one way is connected with resistance R1 and the source electrode of U2 respectively, the other way is connected with resistance R7;The other end of R1 is connected with the VCC port of U5;The other end of R7 is divided into three ways, one way is connected with the gate electrode of U1, one way is connected with one end of R11, one way is connected with capacitor C6 and U2 respectively;The other end of C6 is connected with the source electrode of U2;The other end of R11 is connected with the ACDRV port of U5;The drain electrode of U2 is divided into three ways, one way is connected with RAC1, one way is connected with capacitor C4, one way is connected with C1 and the ACP port of U5 respectively;The other end of C1 is grounded;The other end of RAC1 is divided into two ways, one way is connected with the ACN port of U5, one way is connected with the other end of C4;The end of C4 connected with RAC1 is connected with capacitor C3, the drain electrode of U3 and resistance R5 respectively;The other end of C3 is grounded;The other end of R5 is connected with resistance R8, capacitor C5, capacitor C2, the source electrode of U4 and SYS_VCC interface respectively;The other end of R8 is divided into two ways, one way is connected with resistance R9, one way is connected with the gate electrode of U4 and the other end of C5 respectively;The other end of R9 is connected with the BATDRV port of U5;The source electrode of U3 is connected with the gate electrode of U3, HIDRV port of U5, PH port of U5, capacitor C9, the drain electrode of U6 and inductor L1 respectively;The other end of C9 is connected with the BTST port of U5 and the negative electrode of voltage regulator diode BAT54 respectively;The positive electrode of voltage regulator diode BAT54 is connected with the REGN port of U5 and one end of capacitor C15 respectively;The other end of C15 is grounded;The source electrode of U6 is grounded, and the gate electrode is connected with the LODRV of U5;The other end of L1 is divided into three ways, one way is connected with RSR1, one way is connected with one end of capacitor C10, one way is connected with the SRP port of U5 and capacitor C16 respectively;The other end of C16 is grounded;C10 is connected with the SRN port of U5;The other end of RSR1 is connected with the SRN port of U5, resistance R10, capacitor C11, capacitor C12, the 1 port of lithium battery P2, resistance R15, capacitor Cff1 respectively;The other end of R10 is connected with the drain electrode of U4;The other end of capacitor C11 and C12 is grounded;The other end of R15, the other end of Cff1, the VFB port of U5 and resistance R17 are in communication with each other; the other end of R17 is grounded;
[0022] The VCC port of U5 is connected with capacitor C8; the other end of C8 is grounded; the CE port of U5 is connected with R12; the other end of R12 is connected with the VREF port of U5 and resistance R13 respectively; the other end of R13 is connected with the 1 end of sliding rheostat NTC, resistance R16 and resistance R14 respectively; the other end of R14 is connected with C14 and the TS port of U5 respectively; the other end of NTC, R16 and C14 is grounded; the TTC port of U5 is connected with one end of capacitor CTTC1; the other end of CTTC1 is grounded; the EP port and GND port of U5 are connected with each other and grounded; the STAT1 port of U5 is divided into two paths, one path is connected with external input, and the other path is connected with the negative electrode of D3; the STAT2 port of U5 is divided into two paths, one path is connected with external input, and the other path is connected with the negative electrode of D1; the PG port of U5 is divided into two paths, one path is connected with external input, and the other path is connected with the negative electrode of D2; the positive electrode of D3 is connected with resistance R2; the positive electrode of D1 is connected with resistance R3; the positive electrode of D2 is connected with resistance R4; the other end of R2, R3 and R4 is connected with the VREF port of U5; the VREF port of U5 is connected with capacitor C13; the other end of C13 is grounded;
[0023] The ACSET port of U5 is connected with resistance RACSET_1 and RACSET_2 respectively; the other end of RACSET_1 is connected with the VREF port of U5; the other end of RACSET_2 is connected with resistance RACSET_3; the other end of RACSET_3 is grounded; the ISET1 port of U5 is connected with resistance RISET1 and resistance RISET3 respectively; the other end of RISET1 is connected with the VREF port of U5; the other end of RISET3 is connected with resistance RISET4; the other end of RISET4 is grounded; the ISET2 port of U5 is connected with resistance RISET2 and resistance RACSET1 respectively; the other end of RISET2 is connected with the VREF port of U5; the other end of RACSET1 is connected with resistance RACSET2; the other end of RACSET2 is grounded;
[0024] The 1 pin of the lithium battery P2 is connected with the resistor R27, the 2 pin is connected with the 3 pin and grounded; the GATE pin of the U9 is connected with the negative pole of the BZT52C12V-WH diode and the gate of the U7 respectively; the positive pole of the BZT52C12V-WH diode, the source of the U7, the SOURSE port and the IN port of the U9 are connected with the other end of the R27 and the 4 pin of the P2; the 3 drains of the U7 are connected with the out pin of the U9, the capacitor C38 and the BAT_FD1 interface respectively; the other end of the C38 is connected with the resistor R30 and the VSS pin of the U9 respectively; the other end of the R30 is grounded;
[0025] The SEN pin of the U10 is connected with the RSN52, the drain of the field effect tube Q1 and the negative pole of the parasitic diode of the Q1 respectively; the gate of the Q1 is connected with the GATE pin of the U10; the source of the Q1 is connected with the OUT pin of the U10, the negative pole of the voltage stabilizing diode D5, the capacitor C40 and the SYS_VCC interface respectively; the positive pole of the D5 is grounded; the other end of the C40 is grounded; the VIN pin of the U10 is connected with the RSN52, the resistor R32, the resistor R33, the resistor R34, the voltage stabilizing diode D6, the capacitor C41 and the interface BAT_FD1; the other end of the R32 is connected with the resistor R35, the UVLO pin of the U10 and the resistor R39 respectively; the other end of the R39 is connected with the resistor R40; the other end of the R30 is connected with the resistor R41; the other end of the R41 is connected with the resistor R42; the other end of the R42 is grounded; the other end of the R33 is connected with the other end of the R35 and the resistor R37 respectively; the other end of the R34 is connected with the resistor R36 and the resistor R38 respectively; the other end of the R36 is connected with the OVLO pin of the U10; the TIMER pin of the U10 is connected with one end of the capacitor CTIMER1; the PWR pin of the U10 is connected with the resistor RPWR1; the other ends of the C41, the D6, the R38, the R37, the CTIMER1 and the RPWR1 are connected with each other and grounded;
[0026] The OPT pin of the U8 is grounded; the CSN pin of the U8 is connected with the resistor R20 and the capacitor C31 respectively; the other end of the C31 is connected with the resistor R21, the CSP pin of the U8 respectively; the other end of the R21 is connected with the resistor RSNS1, the capacitor C18, the capacitor C19, the capacitor C20, the capacitor C21, the resistor R24, the resistor R23, the SYS_VCC interface respectively; the other end of the R20 is connected with the other end of the RSNS1 and the inductor L2 respectively; the other end of the C18, the other end of the C19, the other end of the C20, the other end of the C21 are connected with each other and grounded; the other end of the resistor R24 is connected with the capacitor C34 and the VIN pin of the U8 respectively; the other end of the C34 is grounded; the other end of the R23 is connected with the capacitor C33, the resistor R26 and the UVLO pin of the U8 respectively; the other end of the C33 and the other end of the R26 are grounded; the SS pin of the U8 is connected with the capacitor C35; the other end of the C35 is grounded; the SYNCIN / RT pin of the U8 is connected with the resistor R28; the other end of the R28 is grounded; the AGND pin of the U8 is grounded; the FB pin of the U8 is connected with the capacitor C37, the resistor R31 and the resistor R25 respectively; the other end of the R31 is connected with the capacitor C39; the other end of the C39 and the other end of the C37 are connected with each other and the COMP pin of the U8; the SLOPE pin of the U8 is connected with the resistor R29; the RES pin of the U8 is connected with the capacitor C36; the other end of the R29 and the other end of the C36 are connected and grounded; the BST pin of the U8 is connected with the voltage stabilizing diode D4 and the capacitor C30 respectively; the other end of the D4 is connected with the VCC pin of the U8 and the capacitor C32 respectively; the other end of the C32 is connected with the PGND pin of the U8 and grounded; the other end of the C30 is connected with the SW pin of the U8, the source electrode of the field effect transistor Q2 and the positive electrode of the parasitic diode of the Q2 respectively; the HO pin of the U8 is connected with the gate electrode of the field effect transistor Q2; the LO pin of the U8 is connected with the gate electrode of the field effect transistor 3; the other end of the L2 is connected with the source electrode of the field effect transistor Q2, the positive electrode of the parasitic diode of the Q2, the drain electrode of the field effect transistor Q3, the negative electrode of the parasitic diode of the Q3 and the resistor R18 respectively; the source electrode of the field effect transistor Q3 and the positive electrode of the parasitic diode of the Q3 are connected and grounded; the other end of the R18 is connected with the capacitor C17; the other end of the C17 is connected with the drain electrode of the field effect transistor Q2, the negative electrode of the parasitic diode of the Q2, the resistor R19, the capacitor C25, the capacitor C22, the capacitor C23, the capacitor C24, the positive electrode of the capacitor C26, the positive electrode of the capacitor C27, the positive electrode of the capacitor C28, the capacitor C29 and the ports 1 and 2 of the switch P1 respectively; the other end of the R19 is connected with the resistor R22; the other end of the R22 is connected with the R25 and the FB interface of the U8; the other end of the R25 is grounded;The other end of C25, the other end of C22, the other end of C23, the other end of C24, the negative electrode of C26, the negative electrode of C27, the negative electrode of C28, the other end of C29 are connected with each other and grounded; the 3, 4 ports of P1 are connected with input voltage.
Claims
1. A high-speed Internet access system based on a high-throughput tablet portable station, characterized in that: The antenna control unit includes an antenna control unit, which includes a microprocessor, a BD positioning module, and an antenna attitude solution unit. The output end of the BD positioning module is connected to an input end of the microprocessor, and the BD positioning module is used to provide longitude and latitude information. The output end of the antenna attitude solution unit is connected to an input end of the microprocessor. The antenna control unit is connected to a motor through an output end of the microprocessor to drive the motor. The microprocessor is electrically connected to a high-throughput satellite modem for two-way communication. The output end of the high-throughput satellite modem is connected to the input end of an up-conversion power amplifier BUC. The output end of the up-conversion power amplifier BUC is connected to the antenna The output section of the antenna is connected to the feed source, the input end of the low-signal frequency reduction amplifier LNB is connected to the feed source, the output end is connected to the input end of the beacon machine and the high-throughput satellite modem Modem, the output end of the beacon machine is connected to the input end of the microprocessor, the output end of the microprocessor is connected to the motor, the power management module is connected to the lithium battery to control the lithium battery, the lithium battery is connected to the DC-DC module, and the microprocessor is powered by the output end of the DC-DC module, the output port of the microprocessor is connected to the input port of the lithium battery, the output port of the microprocessor is connected to the input port of the OLED screen and the button, the microprocessor is bidirectionally connected to the WiFi module and the external storage unit, and the WiFi module is bidirectionally connected to the monitoring system.
2. The high-speed Internet access system based on a high-throughput tablet portable station according to claim 1, characterized in that: The output terminals of the microprocessor are connected to the motors through the 485 bus.
3. The high-speed Internet access system based on a high-throughput tablet portable station according to claim 1, characterized in that: The BD positioning module includes a global navigation satellite system integrated circuit GNSS IC module, whose input end is respectively connected to the output ends of a surface acoustic wave (SAW) module, a temperature compensated crystal oscillator (TCXO) module, a power supply (Battery) module, and a real-time clock (RTC) Crystal module. The input end of the SAW is connected to the output end of a low-noise microwave amplifier (LNA), and the input end of the low-noise microwave amplifier (LNA) is connected to an antenna. The BD positioning module is bidirectionally connected to the microprocessor via a UART interface.
4. The high-speed Internet access system based on a high-throughput tablet portable station according to claim 1, characterized in that: The antenna attitude calculation unit includes six self-testers, which are respectively connected to an input end of the X-axis accelerometer, Y-axis accelerometer, and X-axis sensor, an input end of the X-axis accelerometer, Y-axis accelerometer, and Z-axis sensor, and an ADC converter. The ADC converter is connected to a signal conditioner. The output end of the signal conditioner is connected to a sensor register. The sensor register is connected to an interrupt status register, a FIFO, a factory debugger, a configuration register, a main I2C serial interface, a digital motion processor, an input port, a frame synchronization signal interface, and I2C and SPI serial interfaces. The I2C and SPI serial interfaces are connected to a / CS interface, an AD0 interface, an SCL interface, an SDA interface, and a serial interface bypass multiplexer. The main I2C serial interface is connected to the serial interface bypass multiplexer, and the serial interface bypass multiplexer is connected to the AUX_CL and AUX_DA interfaces.
5. The high-speed Internet access system based on a high-throughput tablet portable station according to claim 1, characterized in that: It includes 3 SI7611DN field effect transistors, 1 BQ24630RGET circuit management chip, 3 IPC100N4S5-5R5 field effect transistors, 1 LTC4359IMS8 ideal diode controller, 1 LM5069 positive voltage hot-swap controller, 1 LM5122 synchronous boost controller, and 1 lithium battery; the drain of U1 is divided into two paths, one is connected to the output of the adapter, and the other is connected to the resistor R6, the other end of R6 is connected to one end of the capacitor C7, and the other end of C7 is grounded; the source of U1 is divided into two paths, one of which is connected to the source of resistors R1 and U2 respectively, and the other is connected to resistor R7; the other end of R1 is connected to the VCC port of U5; the other end of R7 It is divided into three paths, one is connected to the gate of U1, one is connected to one end of R11, and one is connected to capacitor C6 and U2 respectively; the other end of C6 is connected to the source of U2; the other end of R11 is connected to the ACDRV port of U5; the drain of U2 is divided into three paths, one is connected to RAC1, one is connected to capacitor C4, and one is connected to C1 and the ACP port of U5 respectively; the other end of C1 is grounded; the other end of RAC1 is divided into two paths, one is connected to the ACN port of U5, and one is connected to the other end of C4; the end of C4 connected to RAC1 is connected to capacitor C3, the drain of U3, and resistor R5 respectively; the other end of C3 is grounded; the other end of R5 is connected to resistors R8, The capacitor C5, the capacitor C2, the source of the U4, and the SYS_VCC interface are connected; the other end of the R8 is divided into two paths, one is connected to the resistor R9, and the other is respectively connected to the gate of the U4 and the other end of the C5; the other end of the R9 is connected to the BATDRV port of U5; the source of the U3 is respectively connected to the gate of U3, the HIDRV port of U5, the PH port of U5, the capacitor C9, the drain of the U6, and the inductor L1; the other end of the C9 is respectively connected to the BTST port of U5 and the negative electrode of the voltage-stabilizing diode BAT54; the positive electrode of the voltage-stabilizing diode BAT54 is respectively connected to the REGN port of U5 and one end of the capacitor C15; the other end of the C15 is grounded; the source of the U6 The electrode is grounded, and the gate is connected to the LODRV of U5; the other end of the L1 is divided into three paths, one path is connected to RSR1, one path is connected to one end of the capacitor C10, and one path is respectively connected to the SRP port of U5 and the capacitor C16; the other end of the C16 is grounded; the C10 is connected to the SRN port of U5; the other end of the RSR1 is respectively connected to the SRN port of U5, the resistor R10, the capacitor C11, the capacitor C12, the 1 port of the lithium battery P2, the resistor R15, and the capacitor Cff1; the other end of the R10 is connected to the drain of the U4; the other ends of the capacitors C11 and C12 are grounded; the other end of the R15, the other end of the Cff1, the VFB port of the U5, and the resistor R17 are connected to each other;The other end of R17 is grounded; The VCC port of U5 is connected to capacitor C8; the other end of C8 is grounded; the CE port of U5 is connected to R12; the other end of R12 is respectively connected to the VREF port of U5 and resistor R13; the other end of R13 is respectively connected to the 1 end of the sliding rheostat NTC, resistor R16, and resistor R14; the other end of the resistor R14 is respectively connected to C14 and the TS port of U5; the other ends of NTC, R16, and C14 are grounded; the TTC port of U5 is connected to one end of capacitor CTTC1; the other end of CTTC1 is grounded; the EP port and GND port of U5 are connected to each other. connected and grounded; the STAT1 port of U5 is divided into two paths, one is connected to the external input, and the other is connected to the negative electrode of D3; the STAT2 port of U5 is divided into two paths, one is connected to the external input, and the other is connected to the negative electrode of D1; the PG port of U5 is divided into two paths, one is connected to the external input, and the other is connected to the negative electrode of D2; the positive electrode of D3 is connected to the resistor R2; the positive electrode of D1 is connected to the resistor R3; the positive electrode of D2 is connected to the resistor R4; the other ends of R2, R3, and R4 are connected to the VREF port of U5; the VREF port of U5 is connected to the capacitor C13; the other end of C13 is grounded; The ACSET port of U5 is connected to resistors RACSET_1 and RACSET_2 respectively; the other end of RACSET_1 is connected to the VREF port of U5; the other end of RACSET_2 is connected to resistor RACSET_3; the other end of RACSET_3 is grounded; the ISET1 port of U5 is connected to resistors RISET1 and RISET3 respectively; the other end of RISET1 is connected to the VREF port of U5; the other end of RISET3 is connected to resistor RISET4; The other end of the RISET4 is grounded; the ISET2 port of the U5 is connected to the resistor RISET2 and the resistor RACSET1 respectively; the other end of the RISET2 is connected to the VREF port of the U5; the other end of the RACSET1 is connected to the resistor RACSET2; the other end of the resistor RACSET2 is grounded; Pin 1 of the lithium battery P2 is connected to the resistor R27, and pin 2 is connected to pin 3 and grounded; the GATE pin of U9 is respectively connected to the cathode of the BZT52C12V-WH diode and the gate of U7; the anode of the BZT52C12V-WH diode, the source of U7, the SOURSE port and IN port of U9 are interconnected with the other end of R27 and pin 4 of P2; the three drains of U7 are respectively connected to the out pin of U9, capacitor C38, and BAT_FD1 interface; the other end of C38 is respectively connected to the resistor R30 and the VSS pin of U9; the other end of R30 is grounded; The SEN pin of U10 is respectively connected to RSNS2, the drain of the field effect tube Q1, and the negative electrode of the parasitic diode of Q1; the gate of Q1 is connected to the GATE pin of U10; the source of Q1 is respectively connected to the OUT pin of U10, the negative electrode of the voltage-stabilizing diode D5, the capacitor C40, and the SYS_VCC interface; the positive electrode of D5 is grounded; the other end of C40 is grounded; the VIN pin of U10 is connected to RSN52, the resistor R32, the resistor R33, the resistor R34, the voltage-stabilizing diode D6, the capacitor C41, and the interface BAT_FD1; the other end of R32 is divided into three paths, respectively connected to the resistor R35, the UVLO pin of U10, and the resistor R39 The other end of R39 is connected to the resistor R40; the other end of R30 is connected to the resistor R41; the other end of R41 is connected to the resistor R42; the other end of R42 is grounded; the other end of R33 is respectively connected to the other end of R35 and the resistor R37; the other end of R34 is respectively connected to the resistor R36 and the resistor R38; the other end of R36 is connected to the OVLO pin of U10; the TIMER pin of U10 is connected to one end of the capacitor CTIMER1; the PWR pin of U10 is connected to the resistor RPWR1; the other ends of C41, D6, R38, R37, CTIMER1, and RPWR1 are connected to each other and grounded; The OPT pin of U8 is grounded; the CSN pin of U8 is connected to the resistor R20 and the capacitor C31 respectively; the other end of C31 is connected to the resistor R21 and the CSP pin of U8 respectively; the other end of R21 is connected to the resistor RSNS1, the capacitor C18, the capacitor C19, the capacitor C20, the capacitor C21, the resistor R24, the resistor R23 and the SYS_VCC interface respectively; the R20 is connected to the other end of RSNS1 and the inductor L2 respectively; the other end of C18, the other end of C19, the other end of C20 and the other end of C21 are connected to each other and grounded; the other end of the resistor R24 is connected to the capacitor C34 and the VIN pin of U8 respectively; the The other end is grounded; the other end of R23 is respectively connected to capacitor C33, resistor R26, and UVLO pin of U8; the other end of C33 and the other end of R26 are grounded; the SS pin of U8 is connected to capacitor C35; the other end of C35 is grounded; the SYNCIN / RT pin of U8 is connected to resistor R28; the other end of R28 is grounded; the AGND pin of U8 is grounded; the FB pin of U8 is respectively connected to capacitor C37, resistor R31, and resistor R25; the other end of R31 is connected to capacitor C39; the other end of C39 and the other end of C37 are connected to the COMP pin of U8; the SLOPE pin of U8 is connected to resistor R 29; the RES pin of U8 is connected to the capacitor C36; the other end of R29 is connected to the other end of C36 and grounded; the BST pin of U8 is respectively connected to the voltage stabilizing diode D4 and the capacitor C30; the other end of D4 is respectively connected to the VCC pin of U8 and the capacitor C32; the other end of C32 is connected to the PGND pin of U8 and grounded; the other end of C30 is respectively connected to the SW pin of U8, the source of the field effect transistor Q2, and the positive electrode of the parasitic diode of Q2; the HO pin of U8 is connected to the gate of the field effect transistor Q2; the LO pin of U8 is connected to the gate of the field effect transistor 3; the other end of L2 is respectively connected to the source of the field effect transistor Q2, the parasitic diode of Q2 The positive electrode of the MOSFET Q2, the drain of the MOSFET Q3, the negative electrode of the parasitic diode of Q3, and the resistor R18 are connected; the source of the MOSFET Q3 is connected to the positive electrode of the parasitic diode of Q3 and is grounded; the other end of R18 is connected to the capacitor C17; the other end of C17 is respectively connected to the drain of the MOSFET Q2, the negative electrode of the parasitic diode of Q2, the resistor R19, the capacitor C25, the capacitor C22, the capacitor C23, the capacitor C24, the positive electrode of the capacitor C26, the positive electrode of the capacitor C27, the positive electrode of the capacitor C28, the capacitor C29, and the ports 1 and 2 of the switch P1; the other end of R19 is connected to the resistor R22; the other end of R22 is connected to R25 and the FB interface of U8; the other end of R25 is grounded;The other end of C25, the other end of C22, the other end of C23, the other end of C24, the negative electrode of C26, the negative electrode of C27, the negative electrode of C28, and the other end of C29 are connected to each other and grounded; the 3 and 4 ports of P1 are connected to the input voltage.