Semiconductor device

Abstract

The utility model provides a semiconductor device, and in the semiconductor device, a body region and a drift region are located on the surface of a substrate; the source injection region and the body injection region are positioned in the body region; the gate oxide layer spanning the surfaces of the body region and the drift region comprises a first part and a second part with different thicknesses; a first polysilicon gate and a second polysilicon gate are respectively formed on a first part and a second part of a gate oxide layer, and due to the arrangement of two thicknesses of the gate oxide layer, a body region and a drift region in the semiconductor device can form two body diodes with different threshold voltages, the turn-on voltage of a body diode formed below the gate oxide layer with the smaller thickness is smaller, equivalently, a super-barrier diode with the ultralow turn-on voltage is introduced into a field effect transistor of a semiconductor device, and the semiconductor device can realize integration of the super-barrier diode and a conventional MOS (Metal Oxide Semiconductor) device by utilizing an existing double-gate manufacturing process. The process structure is simple.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor device. BACKGROUND

[0002] In the development of rectifier diodes, although PN junction diodes can work at a higher voltage and have a lower reverse bias leakage current, the forward voltage drop VF is relatively large, the reverse recovery time is relatively long, the switching speed is slow, and the frequency response is not good. In order to effectively reduce the forward voltage drop and shorten the reverse recovery time, a device that forms a Schottky barrier by rectifying contact between metal and N-type semiconductor to realize rectification characteristics is called a Schottky barrier diode (SBD). The Schottky barrier of the device is much lower than the PN junction barrier, and the current mainly depends on the flow of majority carrier electrons in the N-type semiconductor, so it can effectively reduce the forward voltage drop VF and shorten the reverse recovery time. However, the reverse bias leakage current is relatively high, and the withstand voltage is relatively low.

[0003] In order to obtain lower leakage and higher withstand voltage at a lower forward voltage drop, a new type of super barrier rectifier (SBR) is developed, which is also referred to as a super barrier diode in this paper. The super barrier diode can be integrated in parallel with a MOS transistor to form a rectifier device. The metal-oxide-semiconductor (MOS) device is used as a structural unit, and the channel of the MOS is used as the barrier of the SBR device. By using the body effect of the MOS to reduce the threshold voltage of the channel opening, the opening voltage when the device is in reverse (source electrode to drain electrode conduction current) is reduced, so that it obtains a forward voltage drop close to that of the Schottky barrier diode and a relatively lower reverse bias leakage current. The N-type epitaxial layer is used as a drift region to bear most of the withstand voltage, so that it obtains a higher forward (channel closed, drain electrode to source electrode) blocking withstand voltage capability, and the high temperature reliability is much better than that of the Schottky diode. However, how to integrate the MOS transistor and the Schottky barrier diode to obtain better results is the direction of efforts of various manufacturers. CONTENT OF THE UTILITY MODEL

[0004] In order to solve the above technical problems, the present application provides a semiconductor device, which aims to integrate the super barrier diode and the conventional MOS device by using the existing double-gate process, so that the integrated device can simultaneously consider the performance of the MOS device itself and the characteristics of low SBR opening voltage and low reverse recovery charge.

[0005] According to a first aspect of the present application, a semiconductor device is provided, characterized in that it comprises:

[0006] a body region and a drift region located on the surface of the substrate;

[0007] a source implant region and a body implant region located in the body region;

[0008] a gate oxide layer across surfaces of the body region and the drift region;

[0009] a first polysilicon gate and a second polysilicon gate located above the gate oxide layer;

[0010] wherein the gate oxide layer under the first polysilicon gate has a first thickness, and the gate oxide layer under the second polysilicon gate has a second thickness, the first thickness being greater than the second thickness.

[0011] Optionally, the first polysilicon gate and the second polysilicon gate are spaced apart above the gate oxide layer.

[0012] Optionally, there is an isolation dielectric layer between the first polysilicon gate and the second polysilicon gate.

[0013] Optionally, the first polysilicon gate and the second polysilicon gate are spaced apart in a channel width direction of the semiconductor device.

[0014] Optionally, the second polysilicon gate, the source implant region, and the body implant region are electrically connected.

[0015] Optionally, the first polysilicon gate and the second polysilicon gate are electrically connected.

[0016] Optionally, the first polysilicon gate and the second polysilicon gate are integrally formed.

[0017] Optionally, the first polysilicon gate and the second polysilicon gate are sequentially arranged in a channel length direction of the semiconductor device.

[0018] Optionally, in a direction from the body region to the drift region, the second polysilicon gate is located to the left of the first polysilicon gate.

[0019] Optionally, an interface between the first polysilicon gate and the second polysilicon gate is planar, or the first polysilicon gate and the second polysilicon gate have an intersection.

[0020] Optionally, the source implant region and the drift region have a first doping type; the body region and the body implant region have a second doping type.

[0021] Optionally, the number of the first polysilicon gates is greater than or equal to 1.

[0022] The beneficial effects of the present application include at least:

[0023] In the semiconductor device, the gate oxide layer arranged between the body region and the drift region is arranged to include a first portion and a second portion with different thicknesses, so that the body region and the drift region in the semiconductor device can form two parasitic diodes with different turn-on voltages based on the two thicknesses of the gate oxide layer, wherein the parasitic diode formed below the gate oxide layer with a thicker thickness corresponds to a body diode of a field effect transistor (with a larger turn-on voltage), and the parasitic diode formed below the gate oxide layer with a thinner thickness corresponds to a super barrier diode (with a smaller turn-on voltage), thereby realizing the introduction of a super barrier diode with a super low turn-on voltage in the field effect transistor of the semiconductor device. Compared with the prior art, in the embodiment of the present application, the body region and the drift region simultaneously serve as the body diode of the field effect transistor and the anode and cathode of the super barrier diode, and only the thickness of the gate oxide layer needs to be set accordingly, so that the super barrier diode and the conventional MOS device can be integrated by using the existing double-gate process, without the need to additionally manufacture the anode and cathode of the super barrier diode, and the process structure is simple.

[0024] In a further preferred embodiment, the extension directions of the first and second polysilicon gates are parallel to the extension direction of the source implantation region, that is, the two portions of the gate oxide layer with different thicknesses are continuously realized at the same cross-sectional position, thereby avoiding the local strong electric field of the field effect transistor in the blocking state, ensuring the reliability of the portion of the gate oxide layer with a thinner thickness, and not reducing the blocking performance of the field effect transistor.

[0025] It should be noted that the general description above and the detailed description below are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 shows a sectional view of a semiconductor device and an equivalent circuit diagram thereof;

[0027] Figure 2 shows a structural schematic diagram of a semiconductor device and an equivalent circuit diagram thereof according to an embodiment of the present application;

[0028] Figure 3 shows a top view of a semiconductor device according to a first embodiment of the present application;

[0029] Figure 4 shows Figure 3 a sectional view of the semiconductor device at a cross line A1;

[0030] Figure 5 shows Figure 3 a sectional view of the semiconductor device at a cross line A2;

[0031] Figure 6 shows Figure 3A cross-sectional view of the semiconductor device at the line A3;

[0032] Figure 7 A plan view of a semiconductor device according to a second embodiment of the present application is shown;

[0033] Figure 8 A plan view of a semiconductor device according to a second embodiment of the present application is shown; Figure 7 A cross-sectional view of the semiconductor device at the line B1;

[0034] Figure 9 A plan view of a semiconductor device according to a third embodiment of the present application is shown;

[0035] Figure 10 A plan view of a semiconductor device according to a third embodiment of the present application is shown; Figure 9 A cross-sectional view of the semiconductor device at the line C1;

[0036] Figure 11 A plan view of a semiconductor device according to a third embodiment of the present application is shown; Figure 9 A cross-sectional view of the semiconductor device at the line C2. DETAILED DESCRIPTION

[0037] For the purposes of the present application, the following terms shall have the meanings indicated below:

[0038] In this specification, the reference to "one embodiment" or "some embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. The appearances of the phrase "in one embodiment" or "in some embodiments" in various places in the specification are not necessarily all referring to the same embodiment, although it can. Furthermore, the terms "comprises," "comprising," "includes," "including," "has," "having" and the like are intended to be open-ended terms that do not exclude additional, unrecited elements or methods. It is also to be understood that the term "or" as used herein is intended to mean "and / or," unless explicitly stated otherwise.

[0039] In the description of the application, the terms "example" and "exemplary" are used to mean serving as an example, instance, or illustration. Any implementation described as an "example" or "exemplary" is not necessarily to be construed as preferred or advantageous over other implementations.

[0040] In the drawings, the size and relative sizes of layers and regions shown in the drawings can be exaggerated for clarity, and the same reference numerals are used throughout the drawings to designate the same elements. In the description of the present application, it is necessary to explain that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, in order to clearly describe the technical solutions of the embodiments of the present application, the terms "first", "second", etc. are used to distinguish the same items or similar items with basically the same function and action. Those skilled in the art can understand that the terms "first", "second", etc. do not limit the quantity and execution order, and the terms "first", "second", etc. also do not necessarily mean different.

[0041] In addition, the same reference numerals in the drawings represent the same or similar structures, so repeated description thereof will be omitted, that is, each part of the present specification is described in a combination of parallel and progressive manners, and each part mainly explains the difference from other parts, and the same or similar parts between each part can be referred to each other. The words expressing position and direction described in the present application are described with the drawings as an example, but changes can also be made as needed, and the changes made are included in the protection scope of the present application. The drawings of the present application are only used to show the relative positional relationship and do not represent the true proportion.

[0042] Figure 1 A sectional view of a semiconductor device and an equivalent circuit diagram thereof are shown, wherein Figure 1 (a) shows a sectional view of the semiconductor device, Figure 1 (b) shows an equivalent circuit diagram of the semiconductor device, the semiconductor chip comprising a substrate 101, an electrically isolating layer (BL) 102 formed in the substrate 101, an auxiliary depletion layer (FL) 103 located above the electrically isolating layer 102, a body region 104 and a drift region 105 located at the surface of the substrate 101, a source region 107 and a body contact region 106 located in the body region 104, a drain region 108 located in the drift region 105, a gate oxide layer 109 and a polysilicon gate 110 arranged across the body region 104 and the drift region 105.

[0043] Taking the semiconductor device as an example of an NMOSFET, Figure 1 (a) and Figure 1(b) shows, the source region 107, the drain region 108 and the polysilicon gate 110 of the NMOSFET are respectively connected to the source S, the drain D and the gate G of the NMOSFET, and the body region 104 and the drift region 105 form a body diode. When the drain of the NMOSFET is pulled down relative to the source, the body diode formed by the body region 104 and the drift region 105 will gradually conduct, but due to the presence of the gate, the channel potential barrier height of the body region 104 will decrease with the increase of the drain-gate voltage difference, thereby providing an exponential voltage-dependent channel current between the body region 104 and the drift region 105, which is similar to the current-voltage characteristic of a diode. This performance makes the channel region exhibit the characteristics of a super barrier diode, and since the channel current is a single electron current, i.e. a majority carrier, the injection of bipolar carriers in the conventional body diode can be greatly suppressed, thereby achieving better reverse recovery capability and freewheeling capability.

[0044] The theory shows that the lower the threshold voltage of the conventional MOS (such as NMOSFETT) device, the smaller the opening voltage (Vf) of the super barrier diode, and when the NMOSFET is reversely turned on (corresponding to the forward conduction stage of the body diode), the proportion of the channel current is larger, i.e. the current flowing from the source to the drain is converted from a bipolar current to a unipolar majority carrier current, which can greatly reduce the injection of minority carriers and reduce the reverse recovery. Moreover, the smaller the opening voltage of the super barrier diode, the smaller the corresponding forward conduction loss P=Vf*I, and theoretically, if the opening voltage of the super barrier diode is small enough, it can completely suppress the bipolar conduction of the body diode when it is fully turned on, thereby achieving the effect of a Schottky diode. However, if the threshold voltage of the MOSFET is too low, it will cause overdrive, which is not conducive to the design of the driving circuit, and complex signal interference can easily cause the MOSFET to be mistakenly turned on / off. Most importantly, a too low threshold voltage will significantly increase the leakage current of the device.

[0045] Figure 2 A structure diagram of a semiconductor device and an equivalent circuit diagram thereof provided by an embodiment of the present application are shown, wherein, Figure 2 (a) shows a cross-sectional view of the semiconductor device, Figure 2 (b) shows an equivalent circuit diagram of the semiconductor device, which can be manufactured by a double-gate process, thereby realizing the integration of the super barrier diode and the conventional MOS device, so that the integrated device can simultaneously have the performance of the MOS device itself and the characteristics of the low opening voltage and small reverse recovery charge of the SBR.

[0046] In Figure 2(a) In the illustrated example, the semiconductor device includes: a substrate 201, an electrically isolating layer (BL) 202 formed in the substrate 201, an auxiliary depletion layer (FL) 203 located above the electrically isolating layer 202, a body region (BODY region) 204 and a drift region (DRIFT region) 205 located at a first surface of the substrate 201, a source implant region 207 and a body implant region 206 located in the body region 204, a drain implant region 208 located in the drift region 205, a gate oxide layer 209 disposed across the surfaces of the body region 204 and the drift region 205, and a first polysilicon gate 210 and a second polysilicon gate 211 located above the gate oxide layer 209.

[0047] The source implant region 207, the drain implant region 208, and the drift region 205 have a first doping type, the body region 204, the body implant region 206, and the auxiliary depletion layer 203 have a second doping type, and the electrically isolating layer 202 can be of the first doping type or the second doping type. The first doping type is one of N-type doping and P-type doping, and the second doping type is the other of N-type doping and P-type doping. For example, when the semiconductor device is an N-type field effect transistor (i.e., NMOSFET), the doping type or ion implant type of the source implant region 207, the drain implant region 208, and the drift region 205 is N-type doping, the doping type or ion implant type of the body region 204, the body implant region 206, and the auxiliary depletion layer 203 is P-type doping, and the electrically isolating layer 202 can be of N-type doping or P-type doping.

[0048] The first surface of the substrate 201 is, for example, an upper surface thereof. Specifically, the substrate 201 can include, but is not limited to, a silicon substrate, a gallium nitride substrate, a silicon carbide substrate, a diamond substrate, a gallium oxide substrate, or a silicon germanium substrate, etc.

[0049] In Figure 2 (a) In the illustrated example, the electrically isolating layer 202 is specifically formed below the body region 204 and the drift region 205, and the auxiliary depletion layer 203 is specifically formed above the electrically isolating layer 202 and below the body region 204 and the drift region 205. Of course, in some other embodiments, the electrically isolating layer 202 and / or the auxiliary depletion layer 203 can be omitted.

[0050] Optionally, in some embodiments, the body region 204 and the drift region 205 are spaced apart by a certain distance, and in some other embodiments, the body region 204 and the drift region 205 are in contact.

[0051] For reference Figures 4 to 6 The gate oxide layer 209 includes a first portion having a first thickness (denoted as T1) and a second portion having a second thickness (denoted as T2), and the first thickness T1 is greater than the second thickness T2. The gate oxide layer 209 is, for example, integrally formed.

[0052] The thickness ratio (i.e. T1 :T2) of the first and second portions of the gate oxide layer 209 is not strictly limited in the present application, and can be arbitrarily allocated according to the freewheeling capability requirement in specific applications.

[0053] In a specific implementation, the gate oxide layer 209 under the first polysilicon gate 210 is configured to have a first thickness T1, and the gate oxide layer 209 under the second polysilicon gate 211 is configured to have a second thickness T2, so that the channel region under the gate oxide layer 209 can have two different threshold voltages at the same time (wherein the threshold voltage corresponding to the channel region of the first polysilicon gate 210 is greater than the threshold voltage corresponding to the channel region of the second polysilicon gate 211), realizing the integration of field effect transistors (such as MOSFET) and super barrier diodes in the semiconductor device.

[0054] In the present embodiment, the number of the first polysilicon gates 210 in the semiconductor device is greater than or equal to 1.

[0055] Reference Figure 3 and Figure 6 In some embodiments, the first polysilicon gate 204 and the second polysilicon gate 205 are spaced apart above the gate oxide layer 209. Further, the first polysilicon gate 204 and the second polysilicon gate 205 have an isolation dielectric layer 212 therebetween. In this way, the first polysilicon gate 204 and the second polysilicon gate 205 can be respectively applied with different potentials, for example, when the first polysilicon gate 204 is applied with a gate potential, the second polysilicon gate 205 can be electrically connected with the source implant region 207 and the body implant region 206, so as to be applied with the same potential as the source implant region 207 and the body implant region 206. Of course, the second polysilicon gate 205 can also be connected with the first polysilicon gate 204, so as to be applied with the same potential as the first polysilicon gate 204, at which time, in addition to being able to constitute a super barrier diode, the region between the body region 204 and the drift region 205 corresponding to the region under the second polysilicon gate 205 can also provide a part of the channel current.

[0056] In these embodiments, the first polysilicon gate 204 and the second polysilicon gate 205 are spaced apart in the channel width direction of the semiconductor device, that is, the extension direction of the first polysilicon gate 204 and the second polysilicon gate 205 is perpendicular to the extension direction of the source implant region 207. In this way, based on the different thicknesses of the gate oxide layer under the first polysilicon gate 204 and the second polysilicon gate 205 in the semiconductor device, two parasitic diodes connected in parallel can be formed between the body region 204 and the drift region 205 at the same time, to respectively serve as the body diode of the field effect transistor and the super barrier diode.

[0057] It can be understood that in the embodiments, the gate oxide layer 209 with the first thickness T1 is used to meet the requirement of threshold voltage of the field effect transistor, and the gate oxide layer 209 with the second thickness T2 can achieve a smaller threshold voltage under the same implantation condition of the body region 204, thereby achieving a super barrier diode with a smaller on-voltage. By adjusting the thickness T2 of the second part of the gate oxide layer 209, the on-voltage of the super barrier diode can be flexibly adjusted without affecting the characteristics of the field effect transistor.

[0058] In combination Figure 2 (a) and Figure 2 (b), the source implantation region 207 of the semiconductor device corresponds to the source S of the field effect transistor, the drain implantation region 208 of the semiconductor device corresponds to the drain D of the field effect transistor, the body implantation region 206 of the semiconductor device corresponds to the body B of the field effect transistor, the first polysilicon gate 210 of the semiconductor device corresponds to the gate G of the field effect transistor, and the body region 204 and the drift region 205 of the semiconductor device respectively constitute the anode and the cathode of the body diode of the field effect transistor, and also respectively constitute the anode and the cathode of the super barrier diode, and the second polysilicon gate 211 of the semiconductor device corresponds to the gate of the super barrier diode. It can be understood that the body region and the drift region simultaneously serve as the anode and the cathode of the body diode of the field effect transistor and the super barrier diode, and therefore, by appropriately setting the thickness of the gate oxide layer, the super barrier diode can be integrated with the conventional MOS device by using the existing double-gate process without the need to additionally manufacture the anode and the cathode of the super barrier diode, and the process structure is simple.

[0059] Referring to Figures 7 to 11 In some other embodiments, the first polysilicon gate 210 and the second polysilicon gate 211 are sequentially distributed in the channel length direction of the semiconductor device, that is, the extension direction of the first polysilicon gate 210 and the second polysilicon gate 211 is parallel to the extension direction of the source implantation region 207. In specific implementation, in the direction from the body region 204 to the drift region 205, the second polysilicon gate 211 is located on the left side of the first polysilicon gate 210. The embodiments correspond to the case where the gate oxide layer and the field oxide layer (not shown) exist simultaneously in the semiconductor device, and at this time, the first polysilicon gate 210 and the second polysilicon gate 211 are integrally formed. In this way, the thicker part and the thinner part of the gate oxide layer 209 can be continuously implemented at the same cross-sectional position, as shown in FIGS. 2 and 3, and thus the local strong electric field of the field effect transistor in the blocking state in the semiconductor device is avoided, and the blocking performance of the field effect transistor can be ensured without reducing the reliability of the thinner part of the gate oxide layer 209. Figure 8 and Figure 10 In this way, the local strong electric field of the field effect transistor in the blocking state in the semiconductor device is avoided, and the blocking performance of the field effect transistor can be ensured without reducing the reliability of the thinner part of the gate oxide layer 209.

[0060] In this article, the extension direction of each region refers to the length direction of the region in the semiconductor device, for example, in the direction from the body region 204 to the drift region 205.Figure 3 In the embodiment shown in FIG. 2, the extension direction of the first polysilicon gate 204 and the second polysilicon gate 205 is the same as the extension direction of the section line A1, the extension direction of the source injection region 207 is the same as the extension direction of the section line A3, the channel length direction of the semiconductor device is the same as the extension direction of the section line A1, and the channel width direction of the semiconductor device is the same as the extension direction of the section line A3. Alternatively, in the embodiment shown in FIG. 3, the extension direction of the first polysilicon gate 204 and the second polysilicon gate 205 is perpendicular to the extension direction of the section line B1, the extension direction of the source injection region 207 is perpendicular to the extension direction of the section line B1, the channel length direction of the semiconductor device is the same as the extension direction of the section line B1, and the channel width direction of the semiconductor device is perpendicular to the extension direction of the section line B1. Alternatively, in the embodiment shown in FIG. 4, the extension direction of the first polysilicon gate 204 and the second polysilicon gate 205 is perpendicular to the extension direction of the section line C1, the extension direction of the source injection region 207 is perpendicular to the extension direction of the section line C1, the channel length direction of the semiconductor device is the same as the extension direction of the section line C1, and the channel width direction of the semiconductor device is perpendicular to the extension direction of the section line C1. Figure 7 In the embodiment shown in FIG. 2, the extension direction of the first polysilicon gate 204 and the second polysilicon gate 205 is the same as the extension direction of the section line A1, the extension direction of the source injection region 207 is the same as the extension direction of the section line A3, the channel length direction of the semiconductor device is the same as the extension direction of the section line A1, and the channel width direction of the semiconductor device is the same as the extension direction of the section line A3. Alternatively, in the embodiment shown in FIG. 3, the extension direction of the first polysilicon gate 204 and the second polysilicon gate 205 is perpendicular to the extension direction of the section line B1, the extension direction of the source injection region 207 is perpendicular to the extension direction of the section line B1, the channel length direction of the semiconductor device is the same as the extension direction of the section line B1, and the channel width direction of the semiconductor device is perpendicular to the extension direction of the section line B1. Alternatively, in the embodiment shown in FIG. 4, the extension direction of the first polysilicon gate 204 and the second polysilicon gate 205 is perpendicular to the extension direction of the section line C1, the extension direction of the source injection region 207 is perpendicular to the extension direction of the section line C1, the channel length direction of the semiconductor device is the same as the extension direction of the section line C1, and the channel width direction of the semiconductor device is perpendicular to the extension direction of the section line C1. Figure 9 In the embodiment shown in FIG. 2, the extension direction of the first polysilicon gate 204 and the second polysilicon gate 205 is the same as the extension direction of the section line A1, the extension direction of the source injection region 207 is the same as the extension direction of the section line A3, the channel length direction of the semiconductor device is the same as the extension direction of the section line A1, and the channel width direction of the semiconductor device is the same as the extension direction of the section line A3. Alternatively, in the embodiment shown in FIG. 3, the extension direction of the first polysilicon gate 204 and the second polysilicon gate 205 is perpendicular to the extension direction of the section line B1, the extension direction of the source injection region 207 is perpendicular to the extension direction of the section line B1, the channel length direction of the semiconductor device is the same as the extension direction of the section line B1, and the channel width direction of the semiconductor device is perpendicular to the extension direction of the section line B1. Alternatively, in the embodiment shown in FIG. 4, the extension direction of the first polysilicon gate 204 and the second polysilicon gate 205 is perpendicular to the extension direction of the section line C1, the extension direction of the source injection region 207 is perpendicular to the extension direction of the section line C1, the channel length direction of the semiconductor device is the same as the extension direction of the section line C1, and the channel width direction of the semiconductor device is perpendicular to the extension direction of the section line C1.

[0061] Optionally, in the embodiments shown in FIG. 2, FIG. 3 and FIG. 4, the interface between the first polysilicon gate 204 and the second polysilicon gate 205 is a plane, and the process manufacturing flow is simple. Figure 7 Figure 8 In the embodiments shown in FIG. 2, FIG. 3 and FIG. 4, the interface between the first polysilicon gate 204 and the second polysilicon gate 205 is a plane, and the process manufacturing flow is simple. Figure 9 Figure 10 In the embodiments shown in FIG. 2, FIG. 3 and FIG. 4, the interface between the first polysilicon gate 204 and the second polysilicon gate 205 is a plane, and the process manufacturing flow is simple. Figure 11 It can be understood that the semiconductor device provided by the embodiments of the present application can naturally integrate the super barrier diode in the field effect transistor, so that all parasitic parameters of the device can be minimized, and any additional pin is not required.

[0062] The present application does not increase any process complexity, does not increase the number of masks in the process, does not need to change the process menu, and the process structure is simple for the dual gate BCD process platform.

[0063] It should be noted that,

[0064] In the embodiments shown in FIG. 2, FIG. 3 and FIG. 4, the interface between the first polysilicon gate 204 and the second polysilicon gate 205 is a plane, and the process manufacturing flow is simple. Figures 2-8 In the embodiments shown in FIG. 2, FIG. 3 and FIG. 4, the interface between the first polysilicon gate 204 and the second polysilicon gate 205 is a plane, and the process manufacturing flow is simple.

[0065] ​​Finally, it should be noted that the above-mentioned embodiments are merely intended for the purpose of illustration, and are not intended to limit the embodiments. Based on the above descriptions, those skilled in the art can further make other variations and changes of different forms. Here, it is not necessary or possible to enumerate all the embodiments. The obvious variations and changes derived therefrom are still within the scope of the present application.

Claims

1. A semiconductor device, characterized by, include: a body region and a drift region located on the substrate surface; a source injection region and a body injection region located in the body region; A gate oxide layer is provided across the surface of the body region and the drift region; a first polysilicon gate and a second polysilicon gate, located above the gate oxide layer; The gate oxide layer under the first polysilicon gate has a first thickness, the gate oxide layer under the second polysilicon gate has a second thickness, and the first thickness is greater than the second thickness.

2. The semiconductor device of claim 1, wherein, The first polysilicon gate and the second polysilicon gate are spaced apart and distributed above the gate oxide layer.

3. The semiconductor device of claim 2, wherein, An isolation dielectric layer is provided between the first polysilicon gate and the second polysilicon gate.

4. The semiconductor device of claim 2, wherein, The first polysilicon gate and the second polysilicon gate are spaced apart from each other in a channel width direction of the semiconductor device.

5. The semiconductor device of claim 2, wherein, The second polysilicon gate, the source injection region and the body injection region are electrically connected.

6. The semiconductor device of claim 2, wherein, The first polysilicon gate and the second polysilicon gate are electrically connected.

7. The semiconductor device of claim 1, wherein, The first polysilicon gate and the second polysilicon gate are integrally formed.

8. The semiconductor device of claim 7, wherein, The first polysilicon gate and the second polysilicon gate are sequentially distributed in a channel length direction of the semiconductor device.

9. The semiconductor device of claim 8, wherein, Along a direction from the body region to the drift region, the second polysilicon gate is located on the left side of the first polysilicon gate.

10. The semiconductor device of claim 8, wherein, The interface between the first polysilicon gate and the second polysilicon gate is a plane, or the first polysilicon gate and the second polysilicon gate have an intersection.

11. The semiconductor device of claim 1, wherein, The source injection region and the drift region have a first doping type; The body region and the body injection region have a second doping type.

12. The semiconductor device of claim 2, wherein, The number of the first polysilicon gates is greater than or equal to one.

Images