Intelligent monitoring management device for monitoring electric disconnecting switch of overhead line system

The intelligent monitoring and management device solves the interoperability and communication delay problems of the overhead contact line electric disconnector monitoring system, realizes direct access and efficient communication with the DL/T 860 standard system, and improves the real-time performance and reliability of information exchange.

CN223502634UActive Publication Date: 2025-10-31SICHUAN HUIYOU ELECTRICAL CO LTD
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Patent Information

Application Number
CN202422984639.X
Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
Filing Date
2024-12-04
Publication Date
2025-10-31
Estimated Expiration
2034-12-04

AI Technical Summary

Technical Problem

The existing monitoring system for electric disconnect switches of the overhead contact line has poor interoperability, cannot be directly connected to the digital substation system, and suffers from communication delays and unreliability.

Method used

The intelligent monitoring and management device, composed of an ARM processing module, signal decoder, isolation driver, and relay module, is directly connected to the DL/T 860 standard power automation system through LAN1 and LAN2 network isolation transformers, achieving plug-and-play and efficient communication.

Benefits of technology

It improves the real-time performance and reliability of information exchange, enhances the interoperability of devices from different manufacturers, adapts to the future development of communication technologies, and simplifies the configuration process.

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Patent Text Reader

Abstract

The utility model discloses an intelligent monitoring management device for monitoring an electric isolating switch of a contact network, which belongs to the technical field of monitoring of the electric isolating switch of the contact network and comprises an ARM (advanced RISC machines) processing module, a signal decoding module, an isolation driving module and a relay module, the buffer driving module, the photoelectric isolation module and the current-limiting filtering module are sequentially connected with the ARM processing module, the RS485 isolation driving module and the Hall current sensor are sequentially connected with the ARM processing module, and the optical transceiver module and the IRIG-B or PPS input are sequentially connected with the ARM processing module. The relay module, the current-limiting filtering module and the Hall current sensor are all connected with the electric isolating switch of the overhead line system; the ARM processing module is in network connection with the process layer through an LAN1 network isolation transformer and is in network connection with the station control layer through an LAN2 network isolation transformer. The utility model has the advantages of good interoperability and plug and play.
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Description

Technical Field

[0001] This invention belongs to the field of overhead contact line electric disconnector monitoring technology, specifically relating to an intelligent monitoring and management device for monitoring overhead contact line electric disconnectors. Background Technology

[0002] Contact line disconnect switches are crucial equipment for electric traction power supply in electrified railways. Their main functions include fault isolation, segmented operation, and changing operating modes. Numerous contact line disconnect switches exist in hub stations and are widely distributed, making their monitoring extremely important. Currently, the main monitoring method for electric contact line disconnect switches in electrified railways is as follows: a monitoring unit, primarily composed of monitoring devices, is directly connected to the disconnect switch operating mechanism via cables to realize the opening / closing operation and position status monitoring of the disconnect switch. Simultaneously, the monitoring unit is connected to a communication management unit via optical / cable to form a local network. The monitoring unit receives commands from the remote control system forwarded by the communication management unit, analyzes and processes the command messages accordingly, and simultaneously uploads relevant status information of the switch operating mechanism collected by the monitoring unit to the remote control system via the communication management unit.

[0003] However, with the rapid development of electronic and communication technologies and the continuous promotion and application of digital substations based on the DL / T 860 standard, the original monitoring devices can no longer be directly connected to the substation integrated automation system, and the interoperability is poor. Even with the same MODBUS protocol, there are differences between different manufacturers. The communication for information exchange needs to be forwarded through the communication unit, which reduces the real-time performance and reliability. At the same time, the communication unit and the monitoring device use a master-slave communication method, which may result in a delay of several seconds or longer in the transmission of remote signaling signals in extreme cases. Utility Model Content

[0004] To address the aforementioned shortcomings in the existing technology, this utility model provides an intelligent monitoring and management device for monitoring electric disconnect switches in overhead contact lines, which solves the problems of poor interoperability among different manufacturers, the inability of the original monitoring device to be directly connected to the existing digital substation system, and data transmission delay.

[0005] To achieve the above-mentioned utility model objectives, the technical solution adopted by this utility model is as follows: an intelligent monitoring and management device for monitoring electric disconnect switches of contact networks, comprising: an ARM processing module, a signal decoding module, an isolation driving module and a relay module connected in sequence to the ARM processing module, a buffer driving module, an opto-isolation module and a current limiting filter module connected in sequence to the ARM processing module, an RS485 isolation driving module and a Hall current sensor connected in sequence to the ARM processing module, and an optical transceiver module and an IRIG-B or PPS input connected in sequence to the ARM processing module;

[0006] The relay module, current limiting filter module, and Hall current sensor are all connected to the contact network electric disconnect switch; the ARM processing module is connected to the process layer network through the LAN1 network isolation transformer, and the ARM processing module is connected to the station control layer network through the LAN2 network isolation transformer.

[0007] The beneficial effects of this utility model are as follows: The device of this utility model adopts a unified standard in accordance with DL / T 860 requirements, from system equipment model creation, model data types, data attributes, and information exchange methods. It has good interoperability with devices and systems from different manufacturers that use the same DL / T 860 standard. Furthermore, through the wiring terminals, it achieves plug-and-play functionality, reducing the configuration process and facilitating maintenance. Using LAN1 and LAN2 network isolation transformers for network communication reduces intermediate information exchange links, improves the real-time performance and reliability of information response, and eliminates the need for a protocol converter. It can directly connect to DL / T 860 standard power automation systems, adapting to the rapidly developing communication technology applications of the future.

[0008] Furthermore: the ARM processing module includes: chip MU1A and chip MU1B;

[0009] The D1, D2, D3, D4, D5, D6, D7, and D8 pins of the MU1B chip are all connected to the buffer driver module.

[0010] The D15 pin of the MU1B chip is connected to one end of the resistor R147, the D16 pin of the MU1B chip is connected to one end of the resistor R148, and the other ends of the resistors R147 and R148 are both connected to the optical transceiver module.

[0011] The F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12 and F13 pins of the MU1B chip are all connected to the signal decoding module.

[0012] The A7, A8, A9, and A10 pins of the MU1A chip are all connected to the RS485 isolation driver module.

[0013] The A1, A2, A4, and A5 pins of the MU1A chip are all connected to the LAN1 network isolation transformer, and the C1, C2, C4, and C5 pins of the MU1A chip are all connected to the LAN2 network isolation transformer.

[0014] Furthermore: the buffer driver module includes a bus transceiver chip U8;

[0015] Pins 1 and 20 of the bus transceiver chip U8 are both connected to the VC3 power supply. Pins 19 and 10 of the bus transceiver chip U8 are both grounded. Pin 11 of the bus transceiver chip U8 is connected to pin D8 of the MU1B chip. Pin 12 of the bus transceiver chip U8 is connected to pin D7 of the MU1B chip. Pin 13 of the bus transceiver chip U8 is connected to pin D6 of the MU1B chip. Pin 14 of the bus transceiver chip U8 is connected to pin D5 of the MU1B chip. Pin 15 of the bus transceiver chip U8 is connected to pin D4 of the chip MU1B; pin 16 of the bus transceiver chip U8 is connected to pin D3 of the chip MU1B; pin 17 of the bus transceiver chip U8 is connected to pin D2 of the chip MU1B; and pin 18 of the bus transceiver chip U8 is connected to pin D1 of the chip MU1B. Pins 2, 3, 4, 5, 6, 7, 8, and 9 of the bus transceiver chip U8 are all connected to the opto-isolation module.

[0016] Furthermore: the opto-isolation module and the current limiting filter module include eight optocoupler circuits with the same circuit structure, and the eight optocoupler circuits are respectively connected to pins 1, 2, 3, 4, 5, 6, 7 and 8 of the terminal block; the first optocoupler circuit among the eight optocoupler circuits includes optocoupler U21;

[0017] The fourth pin of the optocoupler U21 is connected to one end of capacitor C60, resistor R114, and the second pin of bus transceiver chip U8. The other end of resistor R114 is connected to power supply VC3. The other end of capacitor C60 is connected to the third pin of optocoupler U21 and grounded. The second pin of optocoupler U21 is connected to one end of resistor R96 and one end of capacitor C42 and grounded. The first pin of optocoupler U21 is connected to the other end of resistor R96 and the positive terminal of Zener diode DW1. The negative terminal of Zener diode DW1 is connected to one end of resistor R78. The other end of resistor R78 is connected to the other end of capacitor C42 and one end of resistor R60. The other end of resistor R60 is connected to one end of ferrite bead LC1. The other end of ferrite bead LC1 is connected to the first pin of terminal J4.

[0018] The terminal block J4 is connected to the auxiliary contact of the electric disconnect switch.

[0019] Furthermore: the optical transceiver module includes an optical transceiver chip LD1;

[0020] Pins 1 and 9 of the optical transceiver chip LD1 are grounded. Pin 2 of the optical transceiver chip LD1 is connected to the other end of resistor R147, the other end of resistor R148, and one end of resistor R28, respectively. Pin 8 of the optical transceiver chip LD1 is connected to one end of resistor R27. The other end of resistor R27 is connected to the other end of resistor R28, one end of resistor R70, one end of capacitor C10, one end of power inductor EL2, and the VC3 power supply, respectively. The other end of resistor R70 is connected to the positive terminal of LED SD. The negative terminal of LED SD is connected to the optical transceiver chip. Pin 4 of the optical transceiver chip LD1 is connected to the positive terminal of electrolytic capacitor E4 and the other end of power inductor EL2. The negative terminal of electrolytic capacitor E4 is connected to the other end of capacitor C10, the negative terminal of capacitor E5, and one end of capacitor C11, and grounded. The positive terminal of electrolytic capacitor E5 is connected to pin 6 of the optical transceiver chip LD1 and one end of power inductor EL3. The other end of power inductor EL3 is connected to the other end of capacitor C11 and the VC3 power supply. The optical transceiver chip LD1 receives IRIG-B or PPS input.

[0021] Furthermore: the signal decoding module includes signal decoding chip U15, signal decoding chip U16, and signal decoding chip U17A;

[0022] Pin 1 of the signal decoding chip U15 is connected to pin F1 of chip MU1B; pin 2 of the signal decoding chip U15 is connected to pin F2 of chip MU1B; pin 3 of the signal decoding chip U15 is connected to pin F3 of chip MU1B; pin 6 of the signal decoding chip U15 is connected to pin F4 of chip MU1B; pins 4 and 5 of the signal decoding chip U15 are both connected to pin F5 of chip MU1B; pin 8 of the signal decoding chip U15 is grounded; pin 16 of the signal decoding chip U15 is connected to the VC3 power supply; and pins 9 and 12 of the signal decoding chip U15 are both connected to the isolation driver module.

[0023] Pin 1 of the signal decoding chip U16 is connected to pin F6 of chip MU1B; pin 2 of the signal decoding chip U16 is connected to pin F7 of chip MU1B; pin 3 of the signal decoding chip U16 is connected to pin F8 of chip MU1B; pin 6 of the signal decoding chip U16 is connected to pin F9 of chip MU1B; pins 4 and 5 of the signal decoding chip U16 are both connected to pin F10 of chip MU1B; pin 8 of the signal decoding chip U16 is grounded; pin 16 of the signal decoding chip U16 is connected to the VC3 power supply; and pins 9 and 12 of the signal decoding chip U16 are both connected to the isolation driver module.

[0024] Pin 2 of the signal decoding chip U17A is connected to pin F11 of chip MU1B, pin 3 of the signal decoding chip U17A is connected to pin F12 of chip MU1B, pin 1 of the signal decoding chip U17A is connected to pin F13 of chip MU1B, pin 8 of the signal decoding chip U17A is grounded, pin 16 of the signal decoding chip U17A is connected to the VC3 power supply, and pin 5 of the signal decoding chip U17A is connected to the isolation driver module.

[0025] Furthermore: the isolation drive module includes solid-state relay chip U5, solid-state relay chip U6, and solid-state relay chip U7;

[0026] Pin 1 and pin 3 of the solid-state relay chip U5 are both connected to the VC3 power supply. Pin 2 of the solid-state relay chip U5 is connected to pin 5 of the signal decoding chip U17A. Pin 6 of the solid-state relay chip U5 is grounded. Pin 7 of the solid-state relay chip U5 is connected to the solid-state relay module.

[0027] Pins 1 and 3 of the solid-state relay chip U6 are both connected to the VC3 power supply. Pin 2 of the solid-state relay chip U6 is connected to pin 12 of the signal decoding chip U15. Pin 4 of the solid-state relay chip U6 is connected to pin 9 of the signal decoding chip U15. Pins 6 and 8 of the solid-state relay chip U6 are both grounded. Pins 5 and 7 of the solid-state relay chip U6 are both connected to the solid-state relay module.

[0028] Pins 1 and 3 of the solid-state relay chip U7 are both connected to the VC3 power supply. Pin 2 of the solid-state relay chip U7 is connected to pin 12 of the signal decoding chip U16. Pin 4 of the solid-state relay chip U7 is connected to pin 9 of the signal decoding chip U16. Pins 6 and 8 of the solid-state relay chip U7 are both grounded. Pins 5 and 7 of the solid-state relay chip U7 are both connected to the solid-state relay module.

[0029] Furthermore: the relay module includes relay JR1, relay JR2, relay JR3, relay JR4 and relay JR5;

[0030] The first pin of relay JR1 is connected to the positive terminal of diode D1 and the seventh pin of solid-state relay chip U5. The second pin of relay JR1 is connected to the negative terminal of diode D1, the sixth pin of relay JR1, and the +24V power supply. The eighth pin of relay JR1 is connected to the negative terminals of diodes D13, D12, D11, and D10, the second pin of relay JR2, the second pin of relay JR3, the second pin of relay JR4, and the second pin of relay JR5.

[0031] The first pin of the relay JR2 is connected to the positive terminal of the diode D13 and the seventh pin of the solid-state relay chip U6, the sixth pin of the relay JR2 is connected to the first pin of the terminal J5, and the eighth pin of the relay JR2 is connected to the second pin of the terminal J5.

[0032] The first pin of the relay JR3 is connected to the positive terminal of the diode D12 and the fifth pin of the solid-state relay chip U6, the sixth pin of the relay JR3 is connected to the third pin of the terminal J5, and the eighth pin of the relay JR3 is connected to the fourth pin of the terminal J5.

[0033] The first pin of relay JR4 is connected to the positive terminal of diode D11 and the seventh pin of solid-state relay chip U7, the sixth pin of relay JR4 is connected to the fifth pin of terminal J5, and the eighth pin of relay JR4 is connected to the sixth pin of terminal J5.

[0034] The first pin of relay JR5 is connected to the positive terminal of diode D10 and the fifth pin of solid-state relay chip U7, the sixth pin of relay JR5 is connected to the seventh pin of terminal J5, and the eighth pin of relay JR4 is connected to the eighth pin of terminal J5.

[0035] The terminal J5 is connected to the operating circuit of the electric disconnecting switch of the overhead contact line.

[0036] Furthermore: the RS485 isolation driver module includes an isolation transceiver chip MU3, an isolation transceiver chip MU4, and an OR gate U11;

[0037] The first pin of the isolated transceiver chip MU3 is connected to the VC3 power supply. The second pin of the isolated transceiver chip MU3 is grounded. The fifth pin of the isolated transceiver chip MU3 is connected to one end of resistor R145, one end of resistor R141, and the second pin of terminal J3. The sixth pin of the isolated transceiver chip MU3 is connected to one end of resistor R142, the second pin of T3, and the first pin of terminal J3. The other end of resistor R145 is connected to the first pin of T3. The other end of resistor R141 is connected to the seventh pin of the isolated transceiver chip MU3 and the third pin of terminal J3. The other end of resistor R142 is connected to the eighth pin of the isolated transceiver chip MU3. The eleventh pin of the isolated transceiver chip MU3 is connected to the fourth and fifth pins of OR gate U11. The twelfth pin of the isolated transceiver chip MU3 is connected to the third pin of OR gate U11.

[0038] The first pin of the isolated transceiver chip MU4 is connected to the VC3 power supply. The second pin of the isolated transceiver chip MU4 is grounded. The fifth pin of the isolated transceiver chip MU4 is connected to one end of resistor R146, one end of resistor R143, and the fifth pin of terminal J3. The sixth pin of the isolated transceiver chip MU4 is connected to one end of resistor R144, the second pin of T4, and the fourth pin of terminal J3. The other end of resistor R146 is connected to the first pin of T4. The other end of resistor R143 is connected to the seventh pin of the isolated transceiver chip MU4 and the sixth pin of terminal J3. The other end of resistor R144 is connected to the eighth pin of the isolated transceiver chip MU4. The eleventh pin of the isolated transceiver chip MU4 is connected to the ninth and tenth pins of OR gate U11. The eleventh pin of the isolated transceiver chip MU4 is connected to the eleventh pin of OR gate U11.

[0039] The first and second pins of the OR gate U11 are both connected to the A8 pin of the MU1A chip, the sixth pin of the OR gate U11 is connected to the A7 pin of the MU1A chip, the 12th and 13th pins of the OR gate U11 are both connected to the A10 pin of the MU1A chip, and the eighth pin of the OR gate U11 is connected to the A9 pin of the MU1A chip.

[0040] The terminal J3 is plugged into the Hall current sensor, which is connected to the motor of the electric disconnect switch of the contact network.

[0041] Furthermore: the LAN1 network isolation transformer and the LAN2 network isolation transformer have the same circuit structure. The LAN1 network isolation transformer includes a transformer B1, a circuit protection chip TVA3, and an information socket connector J6; the LAN2 network isolation transformer includes a transformer B2, a circuit protection chip TVA4, and an information socket connector J7.

[0042] The first pin of transformer B1 is connected to the A2 pin of chip MU1A and the first pin of circuit protection chip TVA3. The second pin of transformer B1 is connected to one end of capacitor C19. The third pin of transformer B1 is connected to the A1 pin of chip MU1A and the third pin of circuit protection chip TVA3. The second pin of circuit protection chip TVA3 is grounded. The sixth pin of transformer B1 is connected to the A5 pin of chip MU1A and the fourth pin of circuit protection chip TVA3. The seventh pin of transformer B1 is connected to one end of capacitor C20. The other end of capacitor C20 is connected to the other end of capacitor C19 and grounded. The eighth pin of transformer B1 is connected to the A4 pin of chip MU1A and the sixth pin of circuit protection chip TVA3. The ninth pin of transformer B1... The pin is connected to pin 6 of the information socket connector J6. The 10th pin of the transformer B1 is connected to one end of the resistor R51. The 11th pin of the transformer B1 is connected to pin 3 of the information socket connector J6. The 14th pin of the transformer B1 is connected to pin 2 of the information socket connector J6. The 15th pin of the transformer B1 is connected to one end of the resistor R50. The 16th pin of the transformer B1 is connected to pin 1 of the information socket connector J6. The 4th and 5th pins of the information socket connector J6 are both connected to one end of the resistor R52. The 7th and 8th pins of the information socket connector J6 are both connected to one end of the resistor R53. The other ends of the resistors R50, R51, R52, and R53 are all connected to one end of the capacitor C38. The other end of the capacitor C38 is grounded and connected to the FG2 port.

[0043] The information socket connector J6 is connected to the process layer network;

[0044] The first pin of transformer B2 is connected to the C2 pin of chip MU1A and the first pin of circuit protection chip TVA4. The second pin of transformer B2 is connected to one end of capacitor C21. The third pin of transformer B2 is connected to the C1 pin of chip MU1A and the third pin of circuit protection chip TVA4. The second pin of circuit protection chip TVA4 is grounded. The sixth pin of transformer B2 is connected to the C5 pin of chip MU1A and the fourth pin of circuit protection chip TVA4. The seventh pin of transformer B2 is connected to one end of capacitor C22. The other end of capacitor C22 is connected to the other end of capacitor C21 and grounded. The eighth pin of transformer B2 is connected to the C4 pin of chip MU1A and the sixth pin of circuit protection chip TVA4. Pin 9 is connected to pin 6 of information socket connector J7; pin 10 of transformer B2 is connected to one end of resistor R55; pin 11 of transformer B2 is connected to pin 3 of information socket connector J7; pin 14 of transformer B2 is connected to pin 2 of information socket connector J7; pin 15 of transformer B2 is connected to one end of resistor R54; pin 16 of transformer B2 is connected to pin 1 of information socket connector J7; pins 4 and 5 of information socket connector J7 are both connected to one end of resistor R56; pins 7 and 8 of information socket connector J7 are both connected to one end of resistor R57; the other ends of resistors R54, R55, R56, and R57 are all connected to one end of capacitor C39; the other end of capacitor C39 is connected to port FG2.

[0045] The information socket connector J7 is connected to the station control layer network. Attached Figure Description

[0046] Figure 1 This is an intelligent monitoring and management device for monitoring electric disconnect switches in overhead contact lines;

[0047] Figure 2 This is a schematic diagram of the MU1B chip in the ARM processing module circuit.

[0048] Figure 3 This is a schematic diagram of the MU1A chip in the ARM processing module circuit.

[0049] Figure 4 This is the circuit schematic of the buffer drive module;

[0050] Figure 5 The circuit schematics are for the opto-isolation module and the current-limiting filter module.

[0051] Figure 6 This is a schematic diagram of an optical transceiver module;

[0052] Figure 7 The circuit schematics are for the signal decoding module, the isolation drive module, and the relay module.

[0053] Figure 8 The circuit schematic of the RS485 isolation driver module;

[0054] Figure 9 The circuit diagrams for LAN1 network isolation transformer and LAN2 network isolation transformer are shown.

[0055] The components include: 1. Electric disconnect switch for overhead contact line; 2. Relay; 3. Isolation drive; 4. Signal decoder; 5. ARM processor module; 6. Current limiting filter; 7. Opto-isolation; 8. Buffer drive; 9. Hall current sensor; 10. RS485 isolation drive; 11. IRIG-B or PPS input; 12. Optical transceiver module; 13. LAN1 network isolation transformer; 14. Process layer network; 15. LAN2 network isolation transformer; 16. Station control layer network. Detailed Implementation

[0056] The specific embodiments of this utility model are described below to enable those skilled in the art to understand this utility model. However, it should be understood that this utility model is not limited to the scope of the specific embodiments. For those skilled in the art, as long as various changes are within the spirit and scope of this utility model as defined and determined by the appended claims, these changes are obvious. All utility model creations utilizing the concept of this utility model are within the scope of protection.

[0057] like Figure 1 As shown, an intelligent monitoring and management device for monitoring electric disconnect switches in overhead contact lines includes: an ARM processing module 5, a signal decoding module 4, an isolation drive module 3, and a relay module 2 connected in sequence to the ARM processing module 5, a buffer drive module 8, an opto-isolation module 7, and a current limiting filter module 6 connected in sequence to the ARM processing module 5, an RS485 isolation drive module 10 and a Hall current sensor 9 connected in sequence to the ARM processing module 5, and an optical transceiver module 12 and an IRIG-B or PPS input 11 connected in sequence to the ARM processing module 5.

[0058] Relay module 2, current limiting filter module 6, and Hall current sensor 9 are all connected to the contact network electric disconnect switch 1; ARM processing module 5 is connected to process layer network 14 through LAN1 network isolation transformer 13, and ARM processing module 5 is connected to station control layer network 16 through LAN2 network isolation transformer 15.

[0059] like Figure 2The diagram shown is a schematic of the MU1B chip in the ARM processing module circuit. Figure 3 The diagram shown is a schematic of the MU1A chip in the ARM processing module circuit; the ARM processing module 5 includes: chip MU1A and chip MU1B;

[0060] The D1, D2, D3, D4, D5, D6, D7 and D8 pins of the MU1B chip are all connected to the buffer driver module 8.

[0061] The D15 pin of chip MU1B is connected to one end of resistor R147, the D16 pin of chip MU1B is connected to one end of resistor R148, and the other ends of resistor R147 and resistor R148 are both connected to optical transceiver module 12.

[0062] The F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12 and F13 pins of the MU1B chip are all connected to the signal decoding module 4.

[0063] Pins A7, A8, A9, and A10 of chip MU1A are all connected to RS485 isolation driver module 10;

[0064] The A1, A2, A4 and A5 pins of chip MU1A are all connected to LAN1 network isolation transformer 13, and the C1, C2, C4 and C5 pins of chip MU1A are all connected to LAN2 network isolation transformer 15.

[0065] like Figure 4 The diagram shown is a schematic of the buffer drive module circuit. The buffer drive module 8 includes a bus transceiver chip U8.

[0066] Pins 1 and 20 of the bus transceiver chip U8 are both connected to the VC3 power supply. Pins 19 and 10 of the bus transceiver chip U8 are both grounded. Pin 11 of the bus transceiver chip U8 is connected to pin D8 of the MU1B chip. Pin 12 of the bus transceiver chip U8 is connected to pin D7 of the MU1B chip. Pin 13 of the bus transceiver chip U8 is connected to pin D6 of the MU1B chip. Pin 14 of the bus transceiver chip U8 is connected to pin D5 of the MU1B chip. Pin 15 of chip U8 is connected to pin D4 of chip MU1B; pin 16 of bus transceiver chip U8 is connected to pin D3 of chip MU1B; pin 17 of bus transceiver chip U8 is connected to pin D2 of chip MU1B; pin 18 of bus transceiver chip U8 is connected to pin D1 of chip MU1B; pins 2, 3, 4, 5, 6, 7, 8, and 9 of bus transceiver chip U8 are all connected to opto-isolation module 7.

[0067] like Figure 5 The diagram shows the circuit schematics of the opto-isolation module and the current-limiting filter module. The opto-isolation module 7 and the current-limiting filter module 6 each include eight optocoupler circuits with identical circuit structures. These eight optocoupler circuits are connected to pins 1, 2, 3, 4, 5, 6, 7, and 8 of the terminal block, respectively. The opto-isolation module 7 and the current-limiting filter module 6 include optocouplers U21, U22, U23, U24, U25, U26, U27, and U28.

[0068] Pin 4 of optocoupler U21 is connected to one end of capacitor C60, resistor R114, and pin 2 of bus transceiver chip U8. The other end of resistor R114 is connected to power supply VC3. The other end of capacitor C60 is connected to pin 3 of optocoupler U21 and grounded. Pin 2 of optocoupler U21 is connected to one end of resistor R96 and one end of capacitor C42 and grounded. Pin 1 of optocoupler U21 is connected to the other end of resistor R96 and the positive terminal of Zener diode DW1. The negative terminal of Zener diode DW1 is connected to one end of resistor R78. The other end of resistor R78 is connected to the other end of capacitor C42 and one end of resistor R60. The other end of resistor R60 is connected to one end of ferrite bead LC1. The other end of ferrite bead LC1 is connected to pin 1 of terminal J4.

[0069] Pin 4 of optocoupler U22 is connected to one end of capacitor C61, resistor R115, and pin 3 of bus transceiver chip U8. The other end of resistor R115 is connected to power supply VC3. The other end of capacitor C61 is connected to pin 3 of optocoupler U22 and grounded. Pin 2 of optocoupler U22 is connected to one end of resistor R97 and one end of capacitor C43 and grounded. Pin 1 of optocoupler U22 is connected to the other end of resistor R97 and the positive terminal of Zener diode DW2. The negative terminal of Zener diode DW2 is connected to one end of resistor R79. The other end of resistor R79 is connected to the other end of capacitor C43 and one end of resistor R61. The other end of resistor R61 is connected to one end of ferrite bead LC2. The other end of ferrite bead LC2 is connected to pin 2 of terminal J4.

[0070] Pin 4 of optocoupler U23 is connected to one end of capacitor C62, resistor R116, and pin 4 of bus transceiver chip U8. The other end of resistor R116 is connected to power supply VC3. The other end of capacitor C62 is connected to pin 3 of optocoupler U23 and grounded. Pin 2 of optocoupler U23 is connected to one end of resistor R98 and one end of capacitor C44 and grounded. Pin 1 of optocoupler U23 is connected to the other end of resistor R98 and the positive terminal of Zener diode DW3. The negative terminal of Zener diode DW3 is connected to one end of resistor R80. The other end of resistor R80 is connected to the other end of capacitor C44 and one end of resistor R62. The other end of resistor R62 is connected to one end of ferrite bead LC3. The other end of ferrite bead LC3 is connected to pin 3 of terminal J4.

[0071] Pin 4 of optocoupler U24 is connected to one end of capacitor C63, resistor R117, and pin 5 of bus transceiver chip U8. The other end of resistor R117 is connected to power supply VC3. The other end of capacitor C63 is connected to pin 3 of optocoupler U24 and grounded. Pin 2 of optocoupler U24 is connected to one end of resistor R99 and one end of capacitor C45 and grounded. Pin 1 of optocoupler U24 is connected to the other end of resistor R99 and the positive terminal of Zener diode DW4. The negative terminal of Zener diode DW4 is connected to one end of resistor R81. The other end of resistor R81 is connected to the other end of capacitor C45 and one end of resistor R63. The other end of resistor R63 is connected to one end of ferrite bead LC4. The other end of ferrite bead LC4 is connected to pin 4 of terminal J4.

[0072] Pin 4 of optocoupler U25 is connected to one end of capacitor C64, resistor R118, and pin 6 of bus transceiver chip U8. The other end of resistor R118 is connected to power supply VC3. The other end of capacitor C64 is connected to pin 3 of optocoupler U25 and grounded. Pin 2 of optocoupler U25 is connected to one end of resistor R100 and one end of capacitor C46 and grounded. Pin 1 of optocoupler U25 is connected to the other end of resistor R100 and the positive terminal of Zener diode DW5. The negative terminal of Zener diode DW5 is connected to one end of resistor R82. The other end of resistor R82 is connected to the other end of capacitor C46 and one end of resistor R64. The other end of resistor R64 is connected to one end of ferrite bead LC5. The other end of ferrite bead LC5 is connected to pin 5 of terminal J4.

[0073] Pin 4 of optocoupler U26 is connected to one end of capacitor C65, resistor R119, and pin 7 of bus transceiver chip U8. The other end of resistor R119 is connected to power supply VC3. The other end of capacitor C65 is connected to pin 3 of optocoupler U26 and grounded. Pin 2 of optocoupler U26 is connected to one end of resistor R101 and one end of capacitor C47 and grounded. Pin 1 of optocoupler U26 is connected to the other end of resistor R101 and the positive terminal of Zener diode DW6. The negative terminal of Zener diode DW6 is connected to one end of resistor R83. The other end of resistor R83 is connected to the other end of capacitor C47 and one end of resistor R65. The other end of resistor R65 is connected to one end of ferrite bead LC6. The other end of ferrite bead LC6 is connected to pin 6 of terminal block J4.

[0074] Pin 4 of optocoupler U27 is connected to one end of capacitor C66, resistor R120, and pin 8 of bus transceiver chip U8. The other end of resistor R120 is connected to power supply VC3. The other end of capacitor C66 is connected to pin 3 of optocoupler U27 and grounded. Pin 2 of optocoupler U27 is connected to one end of resistor R102 and one end of capacitor C48 and grounded. Pin 1 of optocoupler U27 is connected to the other end of resistor R102 and the positive terminal of Zener diode DW7. The negative terminal of Zener diode DW7 is connected to one end of resistor R84. The other end of resistor R84 is connected to the other end of capacitor C48 and one end of resistor R66. The other end of resistor R66 is connected to one end of ferrite bead LC7. The other end of ferrite bead LC7 is connected to pin 7 of terminal J4.

[0075] Pin 4 of optocoupler U28 is connected to one end of capacitor C67, resistor R121, and pin 9 of bus transceiver chip U8. The other end of resistor R121 is connected to power supply VC3. The other end of capacitor C67 is connected to pin 3 of optocoupler U28 and grounded. Pin 2 of optocoupler U28 is connected to one end of resistor R103 and one end of capacitor C49 and grounded. Pin 1 of optocoupler U28 is connected to the other end of resistor R103 and the positive terminal of Zener diode DW8. The negative terminal of Zener diode DW8 is connected to one end of resistor R85. The other end of resistor R85 is connected to the other end of capacitor C49 and one end of resistor R67. The other end of resistor R67 is connected to one end of ferrite bead LC8. The other end of ferrite bead LC8 is connected to pin 8 of terminal J4.

[0076] Terminal J4 is connected to the auxiliary contact of the electric disconnect switch 1.

[0077] like Figure 6 The diagram shown is a schematic of an optical transceiver module 12, which includes an optical transceiver chip LD1.

[0078] Pins 1 and 9 of the optical transceiver chip LD1 are grounded. Pin 2 of the optical transceiver chip LD1 is connected to the other ends of resistors R147, R148, and R28, respectively. Pin 8 of the optical transceiver chip LD1 is connected to one end of resistor R27. The other end of resistor R27 is connected to the other end of resistor R28, one end of resistor R70, one end of capacitor C10, one end of power inductor EL2, and the VC3 power supply, respectively. The other end of resistor R70 is connected to the positive terminal of LED SD. The negative terminal of LED SD is connected to the optical transceiver chip LD1. Pin 4 of D1 is connected to pin 5 of the optical transceiver chip LD1, which is connected to the positive terminal of electrolytic capacitor E4 and the other end of power inductor EL2. The negative terminal of electrolytic capacitor E4 is connected to the other end of capacitor C10, the negative terminal of capacitor E5, and one end of capacitor C11, and grounded. The positive terminal of electrolytic capacitor E5 is connected to pin 6 of the optical transceiver chip LD1 and one end of power inductor EL3. The other end of power inductor EL3 is connected to the other end of capacitor C11 and the VC3 power supply. The optical transceiver chip LD1 receives IRIG-B or PPS input 11.

[0079] like Figure 7 The diagram shown is a circuit schematic of the signal decoding module, the isolation drive module, and the relay module.

[0080] Among them, the signal decoding module 4 includes signal decoding chip U15, signal decoding chip U16 and signal decoding chip U17A;

[0081] Pin 1 of signal decoding chip U15 is connected to pin F1 of chip MU1B; pin 2 of signal decoding chip U15 is connected to pin F2 of chip MU1B; pin 3 of signal decoding chip U15 is connected to pin F3 of chip MU1B; pin 6 of signal decoding chip U15 is connected to pin F4 of chip MU1B; pins 4 and 5 of signal decoding chip U15 are both connected to pin F5 of chip MU1B; pin 8 of signal decoding chip U15 is grounded; pin 16 of signal decoding chip U15 is connected to power supply VC3; pins 9 and 12 of signal decoding chip U15 are both connected to isolation driver module 3.

[0082] Pin 1 of signal decoding chip U16 is connected to pin F6 of chip MU1B; pin 2 of signal decoding chip U16 is connected to pin F7 of chip MU1B; pin 3 of signal decoding chip U16 is connected to pin F8 of chip MU1B; pin 6 of signal decoding chip U16 is connected to pin F9 of chip MU1B; pins 4 and 5 of signal decoding chip U16 are both connected to pin F10 of chip MU1B; pin 8 of signal decoding chip U16 is grounded; pin 16 of signal decoding chip U16 is connected to power supply VC3; pins 9 and 12 of signal decoding chip U16 are both connected to isolation driver module 3.

[0083] Pin 2 of the signal decoding chip U17A is connected to pin F11 of the chip MU1B; pin 3 of the signal decoding chip U17A is connected to pin F12 of the chip MU1B; pin 1 of the signal decoding chip U17A is connected to pin F13 of the chip MU1B; pin 8 of the signal decoding chip U17A is grounded; pin 16 of the signal decoding chip U17A is connected to the VC3 power supply; and pin 5 of the signal decoding chip U17A is connected to the isolation driver module 3.

[0084] The isolation driver module 3 includes solid-state relay chip U5, solid-state relay chip U6, and solid-state relay bus transceiver chip U8;

[0085] Pins 1 and 3 of solid-state relay chip U5 are both connected to the VC3 power supply. Pin 2 of solid-state relay chip U5 is connected to pin 5 of signal decoding chip U17A. Pin 6 of solid-state relay chip U5 is grounded. Pin 7 of solid-state relay chip U5 is connected to solid-state relay module 2.

[0086] Pins 1 and 3 of solid-state relay chip U6 are both connected to the VC3 power supply. Pin 2 of solid-state relay chip U6 is connected to pin 12 of signal decoding chip U15. Pin 4 of solid-state relay chip U6 is connected to pin 9 of signal decoding chip U15. Pins 6 and 8 of solid-state relay chip U6 are both grounded. Pins 5 and 7 of solid-state relay chip U6 are both connected to solid-state relay module 2.

[0087] Pins 1 and 3 of the solid-state relay bus transceiver chip U8 are both connected to the VC3 power supply. Pin 2 of the solid-state relay bus transceiver chip U8 is connected to pin 12 of the signal decoding chip U16. Pin 4 of the solid-state relay bus transceiver chip U8 is connected to pin 9 of the signal decoding chip U16. Pins 6 and 8 of the solid-state relay bus transceiver chip U8 are both grounded. Pins 5 and 7 of the solid-state relay bus transceiver chip U8 are both connected to the solid-state relay module 2.

[0088] Relay module 2 includes relays JR1, JR2, JR3, JR4, and JR5;

[0089] Pin 1 of relay JR1 is connected to the positive terminal of diode D1 and pin 7 of solid-state relay chip U5. Pin 2 of relay JR1 is connected to the negative terminal of diode D1, pin 6 of relay JR1, and +24V power supply. Pin 8 of relay JR1 is connected to the negative terminals of diodes D13, D12, D11, and D10, pin 2 of relays JR2, JR3, JR4, and JR5.

[0090] Pin 1 of relay JR2 is connected to the positive terminal of diode D13 and pin 7 of solid-state relay chip U6, pin 6 of relay JR2 is connected to pin 1 of terminal J5, and pin 8 of relay JR2 is connected to pin 2 of terminal J5.

[0091] Pin 1 of relay JR3 is connected to the positive terminal of diode D12 and pin 5 of solid-state relay chip U6, pin 6 of relay JR3 is connected to pin 3 of terminal J5, and pin 8 of relay JR3 is connected to pin 4 of terminal J5.

[0092] Pin 1 of relay JR4 is connected to the positive terminal of diode D11 and pin 7 of solid-state relay chip U7, pin 6 of relay JR4 is connected to pin 5 of terminal J5, and pin 8 of relay JR4 is connected to pin 6 of terminal J5.

[0093] Pin 1 of relay JR5 is connected to the positive terminal of diode D10 and pin 5 of solid-state relay chip U7, pin 6 of relay JR5 is connected to pin 7 of terminal J5, and pin 8 of relay JR4 is connected to pin 8 of terminal J5.

[0094] Terminal J5 is connected to the operating circuit of the opening and closing motor of the electric disconnecting switch 1 of the contact network.

[0095] like Figure 8 The diagram shown is a circuit schematic of an RS485 isolation driver module. The RS485 isolation driver module 10 includes an isolation transceiver chip MU3, an isolation transceiver chip MU4, and an OR gate U11.

[0096] Pin 1 of the isolated transceiver chip MU3 is connected to the VC3 power supply. Pin 2 of the isolated transceiver chip MU3 is grounded. Pin 5 of the isolated transceiver chip MU3 is connected to one end of resistor R145, one end of resistor R141, and pin 2 of terminal J3. Pin 6 of the isolated transceiver chip MU3 is connected to one end of resistor R142, pin 2 of T3, and pin 1 of terminal J3. The other end of resistor R145 is connected to pin 1 of T3. The other end of resistor R141 is connected to pin 7 of the isolated transceiver chip MU3 and pin 3 of terminal J3. The other end of resistor R142 is connected to pin 8 of the isolated transceiver chip MU3. Pin 11 of the isolated transceiver chip MU3 is connected to pins 4 and 5 of OR gate U11. Pin 12 of the isolated transceiver chip MU3 is connected to pin 3 of OR gate U11.

[0097] Pin 1 of the isolated transceiver chip MU4 is connected to the VC3 power supply. Pin 2 of the isolated transceiver chip MU4 is grounded. Pin 5 of the isolated transceiver chip MU4 is connected to one end of resistor R146, one end of resistor R143, and pin 5 of terminal J3. Pin 6 of the isolated transceiver chip MU4 is connected to one end of resistor R144, pin 2 of T4, and pin 4 of terminal J3. The other end of resistor R146 is connected to pin 1 of T4. The other end of resistor R143 is connected to pin 7 of the isolated transceiver chip MU4 and pin 6 of terminal J3. The other end of resistor R144 is connected to pin 8 of the isolated transceiver chip MU4. Pin 11 of the isolated transceiver chip MU4 is connected to pins 9 and 10 of OR gate U11. Pin 12 of the isolated transceiver chip MU4 is connected to pin 11 of OR gate U11.

[0098] The first and second pins of OR gate U11 are both connected to the A8 pin of chip MU1A, the sixth pin of OR gate U11 is connected to the A7 pin of chip MU1A, the 12th and 13th pins of OR gate U11 are both connected to the A10 pin of chip MU1A, and the eighth pin of OR gate U11 is connected to the A9 pin of chip MU1A.

[0099] Terminal J3 is plugged into Hall current sensor 9, and Hall current sensor 9 is connected to the motor of contact network electric disconnect switch 1.

[0100] like Figure 9 The diagram shows the circuit schematics of LAN1 network isolation transformer and LAN2 network isolation transformer. LAN1 network isolation transformer 13 includes transformer B1, circuit protection chip TVA3 and information socket connector J6; LAN2 network isolation transformer 15 includes transformer B2, circuit protection chip TVA4 and information socket connector J7.

[0101] Pin 1 of transformer B1 is connected to pin A2 of chip MU1A and pin 1 of circuit protection chip TVA3. Pin 2 of transformer B1 is connected to one end of capacitor C19. Pin 3 of transformer B1 is connected to pin A1 of chip MU1A and pin 3 of circuit protection chip TVA3. Pin 2 of circuit protection chip TVA3 is grounded. Pin 6 of transformer B1 is connected to pin A5 of chip MU1A and pin 4 of circuit protection chip TVA3. Pin 7 of transformer B1 is connected to one end of capacitor C20. The other end of capacitor C20 is connected to the other end of capacitor C19 and grounded. Pin 8 of transformer B1 is connected to pin A4 of chip MU1A and pin 6 of circuit protection chip TVA3. Pin 9 of transformer B1 is connected to the information socket. Pin 6 of connector J6 is connected to the following: pin 10 of transformer B1 is connected to one end of resistor R51; pin 11 of transformer B1 is connected to pin 3 of information socket connector J6; pin 14 of transformer B1 is connected to pin 2 of information socket connector J6; pin 15 of transformer B1 is connected to one end of resistor R50; pin 16 of transformer B1 is connected to pin 1 of information socket connector J6; pins 4 and 5 of information socket connector J6 are both connected to one end of resistor R52; pins 7 and 8 of information socket connector J6 are both connected to one end of resistor R53; the other ends of resistors R50, R51, R52, and R53 are all connected to one end of capacitor C38; the other end of capacitor C38 is grounded and connected to port FG2.

[0102] Information socket connector J6 is connected to process layer network 14;

[0103] Pin 1 of transformer B2 is connected to pin C2 of chip MU1A and pin 1 of circuit protection chip TVA4. Pin 2 of transformer B2 is connected to one end of capacitor C21. Pin 3 of transformer B2 is connected to pin C1 of chip MU1A and pin 3 of circuit protection chip TVA4. Pin 2 of circuit protection chip TVA4 is grounded. Pin 6 of transformer B2 is connected to pin C5 of chip MU1A and pin 4 of circuit protection chip TVA4. Pin 7 of transformer B2 is connected to one end of capacitor C22. The other end of capacitor C22 is connected to the other end of capacitor C21 and grounded. Pin 8 of transformer B2 is connected to pin C4 of chip MU1A and pin 6 of circuit protection chip TVA4. Pin 9 of transformer B2 is connected to pin 6 of information socket connector J7. Pin connections: Pin 10 of transformer B2 is connected to one end of resistor R55; pin 11 of transformer B2 is connected to pin 3 of information socket connector J7; pin 14 of transformer B2 is connected to pin 2 of information socket connector J7; pin 15 of transformer B2 is connected to one end of resistor R54; pin 16 of transformer B2 is connected to pin 1 of information socket connector J7; pins 4 and 5 of information socket connector J7 are both connected to one end of resistor R56; pins 7 and 8 of information socket connector J7 are both connected to one end of resistor R57; the other ends of resistors R54, R55, R56, and R57 are all connected to one end of capacitor C39; the other end of capacitor C39 is connected to port FG2; port FG2 is for connecting to the chassis network identifier.

[0104] The information socket connector J7 is connected to the station control layer network 16.

[0105] The working principle of the circuit of this utility model is explained below:

[0106] This utility model device receives switch opening and closing information in the DL / T 860 standard message format from a remote power dispatcher via the station control network 16. After transmitting the information to the ARM processor module 5, the device performs validity checks on the received information and performs relevant processing. Then, it operates the processor's GPIO port according to the logic relationship of the output decoding. After passing through the signal decoding module 4, the isolation drive module 3, and the relay module 2, it operates the motor working circuit related to the opening and closing of the electric disconnect switch.

[0107] During the operation of the electric disconnect switch, Hall current sensor 9 detects the operating current of the disconnect switch motor and transmits it to the RS485 interface of the ARM processor module after passing through the RS485 isolation drive module 10. After receiving the current value, the ARM processor module 5 compares it with the set current setting value; when an abnormal operating current value is found, an alarm signal is issued or the motor operation is directly interrupted to avoid damage to the disconnect switch motor.

[0108] Under normal circumstances, after the electric disconnector switch is in the open or closed position, the input interface of the disconnector switch auxiliary contact signal access device is input to the GPIO port of the ARM processor module 5 after passing through the current limiting filter module 6, the opto-isolation module 7, and the buffer drive module 8. The ARM processor module 5 processes the signal accordingly and transmits it to the station control layer network 16 through the LAN2 network isolation transformer 15 in the DL / T 860 standard message format. It can also transmit it to the process layer network 14 through the LAN1 network isolation transformer 13, and publish the relevant information of this utility model device in the GOOSE message format. This enables fast and reliable information sharing between different devices from different manufacturers, and also allows the acquisition of information from other devices, such as the circuit breaker's interlocking signal, the temperature and humidity information of the environmental monitoring device, and the voltage and current information of the system power monitoring device.

[0109] The beneficial effects of this utility model are as follows: The device conforms to the DL / T 860 standard in terms of system equipment model creation, model data types, data attributes, and information exchange methods, ensuring good interoperability with devices and systems from different manufacturers that use the same DL / T 860 standard. Furthermore, the device achieves plug-and-play functionality through wiring terminals, reducing configuration and facilitating maintenance. Using LAN1 and LAN2 network isolation transformers for network communication reduces intermediate information exchange links, improves real-time information response and reliability, and eliminates the need for a protocol converter, enabling direct access to DL / T 860 standard power automation systems, thus adapting to the rapidly evolving communication technology applications of the future.

Claims

1. An intelligent monitoring and management device for monitoring electric disconnect switches in overhead contact lines, characterized in that, include: ARM processing module (5), signal decoding module (4), isolation drive module (3) and relay module (2) connected in sequence to the ARM processing module (5), buffer drive module (8), opto-isolation module (7) and current limiting filter module (6) connected in sequence to the ARM processing module (5), RS485 isolation drive module (10) and Hall current sensor (9) connected in sequence to the ARM processing module (5), and optical transceiver module (12) and IRIG-B or PPS input (11) connected in sequence to the ARM processing module (5); The relay module (2), the current limiting filter module (6), and the Hall current sensor (9) are all connected to the contact network electric disconnect switch (1); the ARM processing module (5) is connected to the process layer network (14) through the LAN1 network isolation transformer (13), and the ARM processing module (5) is connected to the station control layer network (16) through the LAN2 network isolation transformer (15).

2. The intelligent monitoring and management device for monitoring electric disconnect switches of overhead contact lines according to claim 1, characterized in that, The ARM processing module (5) includes: chip MU1A and chip MU1B; The D1, D2, D3, D4, D5, D6, D7 and D8 pins of the MU1B chip are all connected to the buffer driver module (8). The D15 pin of the chip MU1B is connected to one end of the resistor R147, the D16 pin of the chip MU1B is connected to one end of the resistor R148, and the other end of the resistor R147 and the other end of the resistor R148 are both connected to the optical transceiver module (12). The F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12 and F13 pins of the MU1B chip are all connected to the signal decoding module (4). The A7, A8, A9 and A10 pins of the MU1A chip are all connected to the RS485 isolation driver module (10); The A1, A2, A4 and A5 pins of the chip MU1A are all connected to the LAN1 network isolation transformer (13), and the C1, C2, C4 and C5 pins of the chip MU1A are all connected to the LAN2 network isolation transformer (15).

3. The intelligent monitoring and management device for monitoring electric disconnect switches of overhead contact lines according to claim 2, characterized in that, The buffer driver module (8) includes a bus transceiver chip U8; Pins 1 and 20 of the bus transceiver chip U8 are both connected to the VC3 power supply. Pins 19 and 10 of the bus transceiver chip U8 are both grounded. Pin 11 of the bus transceiver chip U8 is connected to pin D8 of the MU1B chip. Pin 12 of the bus transceiver chip U8 is connected to pin D7 of the MU1B chip. Pin 13 of the bus transceiver chip U8 is connected to pin D6 of the MU1B chip. Pin 14 of the bus transceiver chip U8 is connected to pin D5 of the MU1B chip. Pin 15 of transceiver chip U8 is connected to pin D4 of chip MU1B, pin 16 of bus transceiver chip U8 is connected to pin D3 of chip MU1B, pin 17 of bus transceiver chip U8 is connected to pin D2 of chip MU1B, pin 18 of bus transceiver chip U8 is connected to pin D1 of chip MU1B; pins 2, 3, 4, 5, 6, 7, 8 and 9 of bus transceiver chip U8 are all connected to opto-isolation module (7).

4. The intelligent monitoring and management device for monitoring electric disconnect switches of overhead contact lines according to claim 3, characterized in that, The opto-isolation module (7) and the current limiting filter module (6) include eight optocoupler circuits with the same circuit structure. The eight optocoupler circuits are respectively connected to the first, second, third, fourth, fifth, sixth, seventh and eighth pins of the terminal block. The first optocoupler circuit among the eight optocoupler circuits includes optocoupler U21. The fourth pin of the optocoupler U21 is connected to one end of capacitor C60, resistor R114, and the second pin of bus transceiver chip U8. The other end of resistor R114 is connected to power supply VC3. The other end of capacitor C60 is connected to the third pin of optocoupler U21 and grounded. The second pin of optocoupler U21 is connected to one end of resistor R96 and one end of capacitor C42 and grounded. The first pin of optocoupler U21 is connected to the other end of resistor R96 and the positive terminal of Zener diode DW1. The negative terminal of Zener diode DW1 is connected to one end of resistor R78. The other end of resistor R78 is connected to the other end of capacitor C42 and one end of resistor R60. The other end of resistor R60 is connected to one end of ferrite bead LC1. The other end of ferrite bead LC1 is connected to the first pin of terminal J4. The terminal J4 is connected to the auxiliary contact of the electric disconnect switch (1).

5. The intelligent monitoring and management device for monitoring electric disconnect switches of overhead contact lines according to claim 2, characterized in that, The optical transceiver module (12) includes an optical transceiver chip LD1; Pins 1 and 9 of the optical transceiver chip LD1 are grounded. Pin 2 of the optical transceiver chip LD1 is connected to the other end of resistor R147, the other end of resistor R148, and one end of resistor R28, respectively. Pin 8 of the optical transceiver chip LD1 is connected to one end of resistor R27. The other end of resistor R27 is connected to the other end of resistor R28, one end of resistor R70, one end of capacitor C10, one end of power inductor EL2, and the VC3 power supply, respectively. The other end of resistor R70 is connected to the positive terminal of LED SD. The negative terminal of SD is connected to pin 4 of the optical transceiver chip LD1. Pin 5 of the optical transceiver chip LD1 is connected to the positive terminal of electrolytic capacitor E4 and the other end of power inductor EL2. The negative terminal of electrolytic capacitor E4 is connected to the other end of capacitor C10, the negative terminal of electrical capacitor E5, and one end of capacitor C11, and grounded. The positive terminal of electrolytic capacitor E5 is connected to pin 6 of the optical transceiver chip LD1 and one end of power inductor EL3. The other end of power inductor EL3 is connected to the other end of capacitor C11 and the VC3 power supply. The optical transceiver chip LD1 receives IRIG-B or PPS input (11).

6. The intelligent monitoring and management device for monitoring electric disconnect switches of overhead contact lines according to claim 2, characterized in that, The signal decoding module (4) includes signal decoding chip U15, signal decoding chip U16 and signal decoding chip U17A; The first pin of the signal decoding chip U15 is connected to the F1 pin of the chip MU1B, the second pin of the signal decoding chip U15 is connected to the F2 pin of the chip MU1B, the third pin of the signal decoding chip U15 is connected to the F3 pin of the chip MU1B, the sixth pin of the signal decoding chip U15 is connected to the F4 pin of the chip MU1B, the fourth and fifth pins of the signal decoding chip U15 are both connected to the F5 pin of the chip MU1B, the eighth pin of the signal decoding chip U15 is grounded, the sixth pin of the signal decoding chip U15 is connected to the VC3 power supply, and the ninth and twelfth pins of the signal decoding chip U15 are both connected to the isolation drive module (3). The first pin of the signal decoding chip U16 is connected to the F6 pin of the chip MU1B, the second pin of the signal decoding chip U16 is connected to the F7 pin of the chip MU1B, the third pin of the signal decoding chip U16 is connected to the F8 pin of the chip MU1B, the sixth pin of the signal decoding chip U16 is connected to the F9 pin of the chip MU1B, the fourth and fifth pins of the signal decoding chip U16 are both connected to the F10 pin of the chip MU1B, the eighth pin of the signal decoding chip U16 is grounded, the sixth pin of the signal decoding chip U16 is connected to the VC3 power supply, and the ninth and twelfth pins of the signal decoding chip U16 are both connected to the isolation drive module (3). The second pin of the signal decoding chip U17A is connected to the F11 pin of the chip MU1B, the third pin of the signal decoding chip U17A is connected to the F12 pin of the chip MU1B, the first pin of the signal decoding chip U17A is connected to the F13 pin of the chip MU1B, the eighth pin of the signal decoding chip U17A is grounded, the 16th pin of the signal decoding chip U17A is connected to the VC3 power supply, and the fifth pin of the signal decoding chip U17A is connected to the isolation drive module (3).

7. The intelligent monitoring and management device for monitoring electric disconnect switches of overhead contact lines according to claim 6, characterized in that, The isolation drive module (3) includes solid-state relay chip U5, solid-state relay chip U6 and solid-state relay chip U7; The first and third pins of the solid-state relay chip U5 are both connected to the VC3 power supply, the second pin of the solid-state relay chip U5 is connected to the fifth pin of the signal decoding chip U17A, the sixth pin of the solid-state relay chip U5 is grounded, and the seventh pin of the solid-state relay chip U5 is connected to the solid-state relay module (2). The first and third pins of the solid-state relay chip U6 are both connected to the VC3 power supply. The second pin of the solid-state relay chip U6 is connected to the 12th pin of the signal decoding chip U15. The fourth pin of the solid-state relay chip U6 is connected to the 9th pin of the signal decoding chip U15. The sixth and eighth pins of the solid-state relay chip U6 are both grounded. The fifth and seventh pins of the solid-state relay chip U6 are both connected to the solid-state relay module (2). The first and third pins of the solid-state relay chip U7 are both connected to the VC3 power supply. The second pin of the solid-state relay chip U7 is connected to the 12th pin of the signal decoding chip U16. The fourth pin of the solid-state relay chip U7 is connected to the 9th pin of the signal decoding chip U16. The sixth and eighth pins of the solid-state relay chip U7 are both grounded. The fifth and seventh pins of the solid-state relay chip U7 are both connected to the solid-state relay module (2).

8. The intelligent monitoring and management device for monitoring electric disconnect switches of overhead contact lines according to claim 7, characterized in that, The relay module (2) includes relays JR1, JR2, JR3, JR4 and JR5; The first pin of relay JR1 is connected to the positive terminal of diode D1 and the seventh pin of solid-state relay chip U5. The second pin of relay JR1 is connected to the negative terminal of diode D1, the sixth pin of relay JR1, and the +24V power supply. The eighth pin of relay JR1 is connected to the negative terminals of diodes D13, D12, D11, and D10, the second pin of relay JR2, the second pin of relay JR3, the second pin of relay JR4, and the second pin of relay JR5. The first pin of the relay JR2 is connected to the positive terminal of the diode D13 and the seventh pin of the solid-state relay chip U6, the sixth pin of the relay JR2 is connected to the first pin of the terminal J5, and the eighth pin of the relay JR2 is connected to the second pin of the terminal J5. The first pin of the relay JR3 is connected to the positive terminal of the diode D12 and the fifth pin of the solid-state relay chip U6, the sixth pin of the relay JR3 is connected to the third pin of the terminal J5, and the eighth pin of the relay JR3 is connected to the fourth pin of the terminal J5. The first pin of relay JR4 is connected to the positive terminal of diode D11 and the seventh pin of solid-state relay chip U7, the sixth pin of relay JR4 is connected to the fifth pin of terminal J5, and the eighth pin of relay JR4 is connected to the sixth pin of terminal J5. The first pin of relay JR5 is connected to the positive terminal of diode D10 and the fifth pin of solid-state relay chip U7, the sixth pin of relay JR5 is connected to the seventh pin of terminal J5, and the eighth pin of relay JR4 is connected to the eighth pin of terminal J5. The terminal J5 is connected to the operating circuit of the opening and closing motor of the electric disconnecting switch (1) of the contact network.

9. The intelligent monitoring and management device for monitoring electric disconnect switches of overhead contact lines according to claim 7, characterized in that, The RS485 isolation driver module (10) includes an isolation transceiver chip MU3, an isolation transceiver chip MU4, and an OR gate U11; The first pin of the isolated transceiver chip MU3 is connected to the VC3 power supply. The second pin of the isolated transceiver chip MU3 is grounded. The fifth pin of the isolated transceiver chip MU3 is connected to one end of resistor R145, one end of resistor R141, and the second pin of terminal J3. The sixth pin of the isolated transceiver chip MU3 is connected to one end of resistor R142, the second pin of T3, and the first pin of terminal J3. The other end of resistor R145 is connected to the first pin of T3. The other end of resistor R141 is connected to the seventh pin of the isolated transceiver chip MU3 and the third pin of terminal J3. The other end of resistor R142 is connected to the eighth pin of the isolated transceiver chip MU3. The eleventh pin of the isolated transceiver chip MU3 is connected to the fourth and fifth pins of OR gate U11. The twelfth pin of the isolated transceiver chip MU3 is connected to the third pin of OR gate U11. The first pin of the isolated transceiver chip MU4 is connected to the VC3 power supply. The second pin of the isolated transceiver chip MU4 is grounded. The fifth pin of the isolated transceiver chip MU4 is connected to one end of resistor R146, one end of resistor R143, and the fifth pin of terminal J3. The sixth pin of the isolated transceiver chip MU4 is connected to one end of resistor R144, the second pin of T4, and the fourth pin of terminal J3. The other end of resistor R146 is connected to the first pin of T4. The other end of resistor R143 is connected to the seventh pin of the isolated transceiver chip MU4 and the sixth pin of terminal J3. The other end of resistor R144 is connected to the eighth pin of the isolated transceiver chip MU4. The eleventh pin of the isolated transceiver chip MU4 is connected to the ninth and tenth pins of OR gate U11. The eleventh pin of the isolated transceiver chip MU4 is connected to the eleventh pin of OR gate U11. The first and second pins of the OR gate U11 are both connected to the A8 pin of the MU1A chip, the sixth pin of the OR gate U11 is connected to the A7 pin of the MU1A chip, the 12th and 13th pins of the OR gate U11 are both connected to the A10 pin of the MU1A chip, and the eighth pin of the OR gate U11 is connected to the A9 pin of the MU1A chip. The terminal J3 is plugged into the Hall current sensor (9), and the Hall current sensor (9) is connected to the motor of the contact network electric disconnect switch (1).

10. The intelligent monitoring and management device for monitoring electric disconnect switches of overhead contact lines according to claim 2, characterized in that, The LAN1 network isolation transformer (13) and the LAN2 network isolation transformer (15) have the same circuit structure. The LAN1 network isolation transformer (13) includes a transformer B1, a circuit protection chip TVA3, and an information socket connector J6. The LAN2 network isolation transformer (15) includes a transformer B2, a circuit protection chip TVA4, and an information socket connector J7. The first pin of transformer B1 is connected to the A2 pin of chip MU1A and the first pin of circuit protection chip TVA3. The second pin of transformer B1 is connected to one end of capacitor C19. The third pin of transformer B1 is connected to the A1 pin of chip MU1A and the third pin of circuit protection chip TVA3. The second pin of circuit protection chip TVA3 is grounded. The sixth pin of transformer B1 is connected to the A5 pin of chip MU1A and the fourth pin of circuit protection chip TVA3. The seventh pin of transformer B1 is connected to one end of capacitor C20. The other end of capacitor C20 is connected to the other end of capacitor C19 and grounded. The eighth pin of transformer B1 is connected to the A4 pin of chip MU1A and the sixth pin of circuit protection chip TVA3. The ninth pin of transformer B1... The pin is connected to pin 6 of the information socket connector J6. The 10th pin of the transformer B1 is connected to one end of the resistor R51. The 11th pin of the transformer B1 is connected to pin 3 of the information socket connector J6. The 14th pin of the transformer B1 is connected to pin 2 of the information socket connector J6. The 15th pin of the transformer B1 is connected to one end of the resistor R50. The 16th pin of the transformer B1 is connected to pin 1 of the information socket connector J6. The 4th and 5th pins of the information socket connector J6 are both connected to one end of the resistor R52. The 7th and 8th pins of the information socket connector J6 are both connected to one end of the resistor R53. The other ends of the resistors R50, R51, R52, and R53 are all connected to one end of the capacitor C38. The other end of the capacitor C38 is grounded and connected to the FG2 port. The information socket connector J6 is connected to the process layer network (14); The first pin of transformer B2 is connected to the C2 pin of chip MU1A and the first pin of circuit protection chip TVA4. The second pin of transformer B2 is connected to one end of capacitor C21. The third pin of transformer B2 is connected to the C1 pin of chip MU1A and the third pin of circuit protection chip TVA4. The second pin of circuit protection chip TVA4 is grounded. The sixth pin of transformer B2 is connected to the C5 pin of chip MU1A and the fourth pin of circuit protection chip TVA4. The seventh pin of transformer B2 is connected to one end of capacitor C22. The other end of capacitor C22 is connected to the other end of capacitor C21 and grounded. The eighth pin of transformer B2 is connected to the C4 pin of chip MU1A and the sixth pin of circuit protection chip TVA4. Pin 9 is connected to pin 6 of information socket connector J7; pin 10 of transformer B2 is connected to one end of resistor R55; pin 11 of transformer B2 is connected to pin 3 of information socket connector J7; pin 14 of transformer B2 is connected to pin 2 of information socket connector J7; pin 15 of transformer B2 is connected to one end of resistor R54; pin 16 of transformer B2 is connected to pin 1 of information socket connector J7; pins 4 and 5 of information socket connector J7 are both connected to one end of resistor R56; pins 7 and 8 of information socket connector J7 are both connected to one end of resistor R57; the other ends of resistors R54, R55, R56, and R57 are all connected to one end of capacitor C39; the other end of capacitor C39 is connected to port FG2. The information socket connector J7 is connected to the station control layer network (16).