Semiconductor device

Abstract

A semiconductor device includes a substrate, a fin structure, an etch control layer, a shallow trench isolation region, a gate dielectric layer, a gate conductive layer, and an isolation structure. The fin structure is disposed on the substrate, and the fin structure includes a fin portion and an oxide layer. An etch control layer is disposed on the substrate and on a plurality of sidewalls of the fin portion. A shallow trench isolation region is disposed on the etch control layer. The gate dielectric layer is disposed on the oxide layer and on the shallow trench isolation region. The gate conductive layer is disposed on the gate dielectric layer. An isolation structure extends through the gate conductive layer, the gate dielectric layer, and the etch control layer, and the isolation structure has a bottom surface in the shallow trench isolation region or in the etch control layer.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] As semiconductor technology advances, the demand for higher storage capacity, faster processing systems, higher performance, and lower costs continues to increase. To meet these demands, the semiconductor industry continues to shrink the dimensions of semiconductor devices such as metal oxide semiconductor field-effect transistors (MOSFETs), including planar MOSFETs and fin field-effect transistors (finFETs). Such shrinkage increases the complexity of semiconductor manufacturing processes. Utility Model Content

[0003] One of the challenges in forming the isolation structure is controlling the etch depth of the isolation trench during the cut-metal-gate (CMG) process. Etching of the substrate during the CMG process can damage the substrate, thereby reducing the performance and reliability of the finFET.

[0004] According to some embodiments disclosed herein, a semiconductor device includes a substrate, a fin structure, an etch control layer, a shallow trench isolation region, a gate dielectric layer, a gate conductive layer, and an isolation structure. The fin structure is disposed on the substrate and includes fin portions and an oxide layer. The etch control layer is disposed on the substrate and on multiple sidewalls of the fin portions. The shallow trench isolation region is disposed on the etch control layer. The gate dielectric layer is disposed on the oxide layer and on the shallow trench isolation region. The gate conductive layer is disposed on the gate dielectric layer. The isolation structure extends through the gate conductive layer, the gate dielectric layer, and the etch control layer, and the isolation structure has a bottom surface located in the shallow trench isolation region or in the etch control layer.

[0005] According to some embodiments of this disclosure, a semiconductor device includes a substrate, a fin structure, a shallow trench isolation region, an etch control layer, a gate dielectric layer, a gate conductive layer, and an isolation structure. The fin structure is disposed on the substrate. The shallow trench isolation region is disposed on the fin structure and on the substrate. The etch control layer is disposed on the shallow trench isolation region, wherein a top portion of the fin structure is exposed from the shallow trench isolation region and the etch control layer. The gate dielectric layer is disposed on the top portion of the fin structure. The gate conductive layer is disposed on the gate dielectric layer. The isolation structure extends through the gate conductive layer, the gate dielectric layer, and the shallow trench isolation region, and the isolation structure has a bottom surface located in the shallow trench isolation region or in the etch control layer.

[0006] According to some embodiments disclosed herein, a semiconductor device includes a substrate, a shallow trench isolation region, an etch control layer, first and second fin structures, a first gate structure and a second gate structure, and an isolation structure. The shallow trench isolation region is disposed on the substrate. The etch control layer is disposed on the shallow trench isolation region. The first and second fin structures are disposed on the substrate. The first gate structure and the second gate structure are respectively disposed on the first fin structure and the second fin structure and on the etch control layer. The isolation structure is disposed between the first gate structure and the second gate structure and in the etch control layer, wherein the isolation structure has a bottom surface located in the shallow trench isolation region or in the etch control layer.

[0007] This disclosure provides an example semiconductor device having an etch control layer between the substrate and the gate structure, which can improve the performance and reliability of finFETs. Attached Figure Description

[0008] The state disclosed herein is best understood when studied in conjunction with the accompanying figures, as described in the following detailed description.

[0009] Figure 1A The figure shows an isometric view of a semiconductor device with an isolation structure according to some embodiments;

[0010] Figure 1B The figure shows a top view of a semiconductor device with an isolation structure according to some embodiments;

[0011] Figures 2A to 2C The figure shows a cross-sectional view of a semiconductor device with an isolation structure according to some embodiments;

[0012] Figures 3A to 3C The figure shows a cross-sectional view of another semiconductor device having an isolation structure according to some embodiments;

[0013] Figures 4A to 4C The figure shows a cross-sectional view of another semiconductor device having an isolation structure according to some embodiments;

[0014] Figure 5 This is a flowchart of a method for manufacturing a semiconductor device having an isolation structure according to some embodiments;

[0015] Figures 6 to 11 , Figures 12A to 14A , Figures 12B to 14B ,and Figures 12C to 14C The illustration shows cross-sectional views of a semiconductor device with an isolation structure at various stages of its manufacturing process, according to some embodiments.

[0016] Figure 15 This is a flowchart of a method for manufacturing another semiconductor device having an isolation structure according to some embodiments;

[0017] Figures 16 to 19, Figures 20A to 22A , Figures 20B to 22B ,and Figures 20C to 22C The illustration shows a cross-sectional view of another semiconductor device with an isolation structure at various stages of its manufacturing process, according to some embodiments.

[0018] Illustrative embodiments will now be described with reference to the accompanying drawings. In the drawings, similar reference numerals generally denote the same, functionally similar, and / or structurally similar elements.

[0019] [Symbol Explanation]

[0020] 100: Semiconductor devices

[0021] 101A~101B: Memory Device Area

[0022] 102N:NFET

[0023] 102P:PFET

[0024] 104:Substrate

[0025] 104t: Top surface

[0026] 106N: Fin structure

[0027] 106P: Fin structure

[0028] 106P1: Fin base

[0029] 106P2: Fin top

[0030] 109: Isolation Structure

[0031] 110N: S / D area

[0032] 110P: S / D Zone

[0033] 112A~112F: Gate structure

[0034] 112b: Bottom surface

[0035] 112BC: Gate structure

[0036] 112EF: Gate structure

[0037] 114: Gate spacer

[0038] 116:ESL

[0039] 118: ILD layer

[0040] 120: STI area

[0041] 120t: Top surface

[0042] 122A~122B: Isolation Structure

[0043] 122As: Bottom surface

[0044] 122Bs: Bottom surface

[0045] 212A: IL layer

[0046] 212B: High-k gate dielectric layer

[0047] 212C: Conductive layer

[0048] 224: Etching Control Layer

[0049] 224t: Top surface

[0050] 324: Etching control layer

[0051] 324t: Top surface

[0052] 424: Etching Control Layer

[0053] 424s: Top surface

[0054] 424t: Top surface

[0055] 500: Methods

[0056] 505~525: Operation

[0057] 626: Hard mask layer

[0058] 720: Dielectric layer

[0059] 1024: Dielectric layer

[0060] 1322A~1322B: Isolation trenches

[0061] 1322As: Bottom surface

[0062] 1322Bs: Bottom surface

[0063] 1500: Method

[0064] 1505~1520: Operation

[0065] 1624: Dielectric layer

[0066] 1720: Dielectric layer

[0067] 2122A~2122B: Isolation trenches

[0068] 2122As: Bottom surface

[0069] 2122Bs: Bottom surface

[0070] GL1~GL2: Gate length

[0071] GP1~GP2: Gate pitch

[0072] AA: Line

[0073] BB: Line

[0074] CC: Line

[0075] X: axis

[0076] Y: axis

[0077] Z: Axis Detailed Implementation

[0078] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. As used herein, the formation of a first feature over a second feature means that the first and second features are formed in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate any relationship between the various embodiments and / or configurations discussed.

[0079] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and the like are used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein can be interpreted similarly accordingly.

[0080] It should be noted that references to "an embodiment," "an example embodiment," "exemplary embodiment," "illustrative," etc., in the specification indicate that the described embodiment may include specific features, structures, or characteristics, but each embodiment may not necessarily include specific features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0081] It should be understood that the idioms or terms used in this document are for descriptive rather than restrictive purposes, and that the terms or idioms used in this specification shall be interpreted by those skilled in the art based on the teachings herein.

[0082] In some embodiments, the terms “about” and “substantially” may indicate a given number of values ​​that vary within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of that value). These values ​​are merely examples and not intended to be limiting. The terms “about” and “substantially” may refer to a percentage of a value as interpreted by one skilled in the art in accordance with the teachings herein.

[0083] The fin structures disclosed herein can be patterned using any suitable method. For example, one or more optical lithography processes (including dual or multiple patterning processes) can be used to pattern the fin structures. Dual or multiple patterning processes can combine optical lithography with self-alignment processes, thereby allowing the production of patterns with, for example, smaller pitches than that achievable using a single direct optical lithography process. For example, a sacrificial layer is formed over a substrate and patterned using an optical lithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin structure.

[0084] In a semiconductor device with multiple finFETs, the gate structure can be formed as an extension over the fin structure of the multiple finFETs. After the gate structure is formed, a patterning process can be performed to "cut" one or more of the gate structures into shorter gate structures. The patterning process removes redundant gate portions of one or more gate structures to form one or more isolation trenches (also known as "metal cuts") between the finFETs and separate the gate structures into shorter segments. This process is called cut-metal-gate (CMG) processing. Subsequently, the isolation trenches can be filled with a dielectric material such as silicon nitride (SiN) to form an isolation structure that electrically isolates the separated gate structures.

[0085] One of the challenges in forming the isolation structure is controlling the etching depth of the isolation trenches during the CMG process. During the CMG process, the isolation trenches can extend vertically into the FinFET substrate. Etching of the substrate during the CMG process can damage the substrate, thereby reducing the performance and reliability of the FinFET. Furthermore, the dielectric layer deposited in the isolation trenches to form the isolation structure can induce charged carriers into the substrate. These charged carriers can create current leakage paths between the p-wells and n-wells of adjacent FinFETs via the substrate, further degrading FinFET performance.

[0086] To address the aforementioned challenges, this disclosure provides an example semiconductor device (e.g., a finFET) having an etch control layer between a substrate and a gate structure, and an example method for manufacturing the semiconductor device. During the formation of the isolation structure in a CMG process, the etch control layer prevents isolation trenches from extending into the substrate via shallow trench isolation (STI) regions. In some embodiments, the etch control layer may be directly disposed on the STI region, and the bottom surface of the isolation structure may be disposed in the etch control layer or in the STI region. In some embodiments, the etch control layer may be directly disposed on the substrate, and the bottom surface of the isolation structure may be disposed in the etch control layer. In some embodiments, the etch control layer may have an etch selectivity lower than that of the gate structure to reduce the etch rate of the CMG process after etching the gate structure. Reducing the etch rate after etching the gate structure allows for more precise control over the etch depth of the isolation trenches in the etch control layer and / or the STI region compared to semiconductor devices without an etch control layer.

[0087] According to some embodiments, reference Figure 1A , Figure 1B , Figures 2A to 2C , Figures 3A to 3C ,and Figures 4A to 4C A semiconductor device 100 having an NFET 102N and a PFET 102P in a memory device region 101A and a logic device region 101B is described. Figure 1A The figure shows an isometric view of a semiconductor device 100 according to some embodiments. Figure 1B The figure shows a top view of a semiconductor device 100 according to some embodiments. Figure 2A , Figure 3A ,and Figure 4A Along the semiconductor device 100 shown in the figure Figure 1A and Figure 1B Different cross-sectional views of line AA. Figure 2B , Figure 3B ,and Figure 4B Along the semiconductor device 100 shown in the figure Figure 1A and Figure 1B Different cross-sectional views of line BB. Figure 2C , Figure 3C ,and Figure 4C Along the semiconductor device 100 shown in the figure Figure 1A and Figure 1B Different cross-sectional views of line CC. Figures 2A to 2C , Figures 3A to 3C ,and Figures 4A to 4C The figure shows a cross-sectional view of a semiconductor device 100 with additional structures, for simplicity. Figure 1A and Figure 1BThese additional structures are not shown in the text. Unless otherwise mentioned, Figure 1A , Figure 1B , Figures 2A to 2C , Figures 3A to 3C ,and Figures 4A to 4C The descriptions of elements that have the same reference numerals and / or letters are applicable to each other.

[0088] refer to Figure 1A , Figure 1B ,and Figures 2A to 2C The semiconductor device 100 may include: (i) a substrate 104; (ii) fin structures 106N and 106P disposed on the substrate 104. Figure 1B and Figure 2A (iii) The source / drain (S / D) regions 110N and 110P respectively disposed on the fin structures 106N and 106P (invisible in the middle); Figure 2A and Figure 2B (iv) Gate structure 112A disposed on fin structures 106N and 106P (not visible in the middle); Figure 2B and Figure 2C (v) Gate structure 112B disposed on fin structure 106N (not visible in the middle); Figure 2A and Figure 2C (visible in the middle); (vi) gate structure 112C disposed on fin structure 106P (in Figure 2A and Figure 2C (not visible in the middle); (vii) gate structure 112D disposed on fin structures 106N and 106P (in Figure 2B and Figure 2C (not visible in the middle); (viii) gate structure 112E disposed on fin structure 106N (in the middle) Figures 2A to 2C (not visible in the middle); (ix) gate structure 112F disposed on fin structure 106P (in Figures 2A to 2C (not visible in the middle); (x) gate spacer 114 disposed on gate structures 112A to 112F; (xi) ESL116 disposed on S / D regions 110N and 110P (in the middle) Figure 1B Not shown in Figure 2B (not visible in the middle); (xii) ILD layer 118 set on ESL 116 (in Figure 1B Not shown in Figure 2B (xiii) STI region 120 disposed on substrate 104 (invisible in the middle); Figure 1B (not shown); (xiv) isolation structure 122A disposed between gate structures 112B and 112C; (xv) isolation structure 122B disposed between gate structures 112D and 112E (in Figure 2B and Figure 2C (not visible in the middle); and (xvi) the etch control layer 224 directly disposed on the STI area 120 (in the middle). Figure 1A and Figure 1B (Not shown in the image).

[0089] Unless otherwise mentioned, the descriptions of gate structures 112A-112F apply to each other. S / D regions 110N and 110P may refer individually or collectively to the source or drain, depending on the context. In some embodiments, fin structure 106N may form an NFET 102N together with elements and portions of elements disposed on fin structure 106N of semiconductor device 100. Similarly, in some embodiments, fin structure 106P may form a PFET 102P together with elements and portions of elements disposed on fin structure 106P of semiconductor device 100. In some embodiments, NFET 102N and PFET 102P in memory device region 101A may be a memory device or a portion of a memory device. In some embodiments, NFET 102N and PFET 102P in logic device region 101B may be a logic device or a portion of a logic device. In some embodiments, semiconductor device 100 may further include isolation structure 109 (e.g., Figure 1A As shown in the diagram, it extends along the X-axis and into the substrate 104 to cut fin structures 106N and 106P, and electrically isolates portions of fin structures 106N and 106P in the memory device region 101A from these portions in the logic device region 101B. The isolation structure 109 may include dielectric materials such as silicon oxide (SiO2) and SiN.

[0090] In some embodiments, substrate 104 may be a semiconductor material, such as silicon, germanium (Ge), silicon-germanium (SiGe), silicon-on-insulator (SOI) structures, and combinations thereof. Furthermore, substrate 104 may be doped with p-type dopant (e.g., boron, indium, aluminum, or gallium) or n-type dopant (e.g., phosphorus or arsenic).

[0091] In some embodiments, fin structure 106N may include a material similar to substrate 104. In some embodiments, each of fin structures 106P may include a fin base 106P1 and a fin top 106P2. In some embodiments, fin base 106P1 may include a material similar to substrate 104, and fin top 106P2 may include SiGe. Fin structures 106N and 106P may have elongated sides extending along the X-axis.

[0092] In some embodiments, the S / D region 110N may include an epitaxially grown semiconductor material, such as Si, and an n-type dopant, such as phosphorus and other suitable n-type dopant. In some embodiments, the S / D region 110P may include an epitaxially grown semiconductor material, such as Si and SiGe, and a p-type dopant, such as boron and other suitable p-type dopant.

[0093] In some embodiments, each of the gate structures 112A to 112F may include: (i) an interfacial oxide (IL) layer 212A; (ii) a high-k gate dielectric layer 212B directly disposed on the IL layer 212A; and (iii) a conductive layer 212C directly disposed on the high-k gate dielectric layer 212B. In some embodiments, the IL layer 212A may include SiO2, silicon germanium oxide (SiGeO2), etc. x ), or germanium oxide (GeO) x The IL layer 212A of gate structures 112A and 112D can be directly disposed on both fin structures 106N and 106P. The IL layer 212A of gate structures 112B and 112E can be directly disposed on fin structure 106N, and the IL layer 212A of gate structures 112C and 112F can be directly disposed on fin structure 106P.

[0094] In some embodiments, the high-k gate dielectric layer 212B may include a high-k dielectric material, such as hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), aluminum zirconium oxide (ZrAlO), zirconium silicate (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zinc oxide (ZnO), hafnium zinc oxide (HfZnO), and yttrium oxide (Y2O3). In some embodiments, the conductive layer 212C may be a multilayer structure. For simplicity, the different layers of the conductive layer 212C are not shown. In some embodiments, the conductive layer 212C may include a work function metal (WFM) layer disposed on the high-k gate dielectric layer 212B and a gate metal filling layer disposed on the WFM layer. In some embodiments, the WFM layer may comprise a substantially Al-free (e.g., Al-free) Ti-based or Ta-based nitride or alloy, such as titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium-gold (Ti-Au) alloy, titanium-copper (Ti-Cu) alloy, tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum-gold (Ta-Au) alloy, and tantalum copper (Ta-Cu). In some embodiments, the WFM layer may comprise titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), Al-doped Ti, Al-doped TiN, Al-doped Ta, Al-doped TaN, or other suitable Al-based materials. In some embodiments, the gate metal fill layer may comprise a suitable conductive material, such as tungsten (W), titanium (Ti), silver (Ag), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), aluminum (Al), iridium (Ir), nickel (Ni), metal alloys, and combinations thereof.

[0095] In some embodiments, gate structures 112A, 112B, and 112C in memory device region 101A may have a gate pitch GP1 and a gate length GL1. In some embodiments, gate structures 112D, 112E, and 112F in logic device region 101B may have a gate pitch GP2 and a gate length GL2. In some embodiments, the gate pitch GP1 and gate length GL1 may be smaller than the gate pitch GP2 and gate length GL2, respectively. As a result, compared to logic device region 101B, memory device region 101A may have a higher density device region, with a larger number of gate structures and a larger number of finFETs per unit device region. The gate pitch is defined as the distance along the X-axis between adjacent gate structures having equal gate lengths and the gate length of one of the adjacent gate structures (e.g., Figure 1AThe sum of GL1 to GL2 shown. Gate structures 112A to 112F can be electrically isolated from each other by gate spacer 114, ESL 116, and ILD layer 118. In some embodiments, gate spacer 114, ESL 116, and ILD layer 118 may include insulating materials such as SiO2, SiN, silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and SiGeO. x .

[0096] In some embodiments, the STI region 120 can electrically isolate the fin structures 106N and 106P from each other. In some embodiments, the STI region 120 may include an insulating material, such as SiO2, SiN, SiON, SiOC, SiCN, and SiOCN. In some embodiments, portions of the gate structures 112A to 112F that are not directly disposed on the fin structures 106N or 106P may be disposed on the STI region 120.

[0097] In some embodiments, gate structures 112B and 112C, except for gate spacer 114, ESL 116, and ILD layer 118, can be electrically isolated from each other by isolation structure 122A, and gate structures 112E and 112F can be electrically isolated from each other by isolation structure 122B to provide independently controlled gate structures. Isolation structures 122A and 122B can be formed simultaneously with different dielectric constants in a CMG process (described in detail below), thereby cutting long gate structures (e.g., along the Y-axis) into shorter gate structures, such as gate structures 112B, 112C, 112E, and 112F. In some embodiments, isolation structures 122A and 122B may include insulating materials such as SiO2, SiN, SiON, SiOC, SiCN, and SiOCN.

[0098] In some embodiments, the isolation structure 122A in the memory device region 101A may have a width W1 smaller than the width W2 of the isolation structure 122B in the logic device region 101B. Since the gate length GL1 in the memory device region 101A is smaller than the gate length GL2 in the logic device region 101B, the width W1 may be smaller than the width W2. Widths W1 and W2 correspond to gate lengths GL1 and GL2, because the isolation structures 122A and 122B are formed by removing redundant gate portions between gate structures 112B and 112C and between gate structures 112E and 112F, as described in detail below. In some embodiments, the width W1 may be about 20 nm to about 30 nm, and the width W2 may be about 30 nm to about 40 nm. In some embodiments, the isolation structures 122A and 122B may have a rectangular cross-sectional profile along the XZ plane (e.g., ...). Figure 2AAs shown in the figure), and may have a trapezoidal cross-sectional profile along the YZ plane (as shown in the figure). Figure 2B and Figure 2C (as shown in the diagram). In some embodiments, the isolation structures 122A and 122B may have vertical sidewalls along the YZ plane (e.g., as shown in the diagram). Figure 2A As shown in the figure), and may have inclined sidewalls along the XZ plane (such as Figure 2B and Figure 2C (as shown in the image).

[0099] In some embodiments, the bottom surfaces 122As and 122Bs of the isolation structures 122A and 122B may have substantially planar cross-sectional profiles, which may be due to etch profile control performed by etch control layers (such as etch control layers 224, 324, and 424) during the formation of the isolation structures 122A and 122B in the CMG process, as described in detail below. In some embodiments, the depth profiles of the isolation structures 122A and 122B may depend on the location and / or thickness of etch control layers, such as etch control layers 224, 324, and 424 in the semiconductor device 100, as referenced below. Figures 2A to 2C , Figures 3A to 3C ,and Figures 4A to 4C Detailed description. Unless otherwise mentioned, the following discussion of etch control layers 224, 324, and 424 applies to each other.

[0100] refer to Figures 2A to 2CIn some embodiments, the etch control layer 224 can be used to prevent the isolation structures 122A and 122B from extending into the substrate 104, thereby preventing the formation of a current leakage path between the NFET 102N and the PFET 102P via the substrate 104. In some embodiments, the etch control layer 224 may: (i) be directly disposed on the STI region 120; (ii) be directly disposed below the portion of the gate structures 112A-112F that is not directly disposed on the fin structures 106N or 106P; (iii) be disposed around the portion of the fin structures 106N and 106P that is below the gate structures 112A-112F; and (iv) be directly disposed below the portion of the ESL 116 that is not directly disposed on the S / D regions 110N and 110P and on the gate structures 112A-112F. Etching control layer 224 can be used to control the distance by which portions of isolation structures 122A and 122B extend below the bottom surface 112b of gate structures 112A-112F. In some embodiments, etching control layer 224 having a thickness T1 of about 5 nm to about 20 nm can adequately control: (i) the depth profile of isolation structure 122A to extend a distance D1 below the top surface 120t of STI region 120 and maintain a distance D2 of at least about 10 nm (e.g., about 10 nm to about 50 nm) between bottom surface 122As and top surface 104t of substrate 104; and (ii) the depth profile of isolation structure 122B to extend a distance D3 below the top surface 120t of STI region 120 and maintain a distance D4 of at least about 10 nm (e.g., about 10 nm to about 50 nm) between bottom surface 122Bs and top surface 104t of substrate 104. In some embodiments, distance D3 may be greater than distance D1. Preventing the isolation structures 122A and 122B from extending into the substrate 104 and maintaining distances D2 and D4 prevents charged carriers from being induced into the substrate 104, thereby preventing the formation of a current leakage path between the NFET 102N and the PFET 102P via the substrate 104.

[0101] refer to Figures 3A to 3CIn some embodiments, instead of etch control layer 224, etch control layer 324 can be used to prevent isolation structures 122A and 122B from extending into substrate 104. In some embodiments, etch control layer 324 having a thickness T2 of about 20 nm to about 50 nm can adequately control: (i) the depth profile of isolation structure 122A to extend a distance D5 below the top surface 324t of etch control layer 324; and (ii) the depth profile of isolation structure 122B to extend a distance D6 below the top surface 324t of etch control layer 324. In some embodiments, distance D6 may be greater than distance D5. In some embodiments, etch control layer 324 can be used to control the depth profile of isolation structures 122A and 122B such that the bottom surfaces 122As and 122Bs of isolation structures 122A and 122B can be directly disposed on the top surface 120t (not shown) of the STI region. Therefore, by using an etch control layer 324 that is thicker than the etch control layer 224, the portions of the isolation structures 122A and 122B below the bottom surface 112b of the gate structures 112A to 112F can be confined within the etch control layer 324 and do not extend into the STI region.

[0102] refer to Figures 4A to 4C In some embodiments, instead of etch control layers 224 or 324, etch control layer 424 can be used to prevent isolation structures 122A and 122B from extending into substrate 104. In some embodiments, etch control layer 424 may: (i) be disposed directly on substrate 104; (ii) be disposed directly below STI region 120; (iii) be disposed directly on the sidewalls of fin structures 106N and 106P not covered by S / D regions 110N and 110P and gate structures 112A to 112F; and (iv) be disposed directly on the sidewalls of S / D regions 110N and 110P not covered by ESL 116. In some embodiments, an etch control layer 424 having a thickness T3 of about 5 nm to about 50 nm can adequately control: (i) the depth profile of the isolation structure 122A to extend a distance D7 below the top surface 424t of the etch control layer 424; and (ii) the depth profile of the isolation structure 122B to extend a distance D8 below the top surface 424t of the etch control layer 424. In some embodiments, the distance D8 may be greater than the distance D7. In some embodiments, the etch control layer 424 can be used to control the depth profiles of the isolation structures 122A and 122B such that the bottom surfaces 122As and 122Bs of the isolation structures 122A and 122B can be directly disposed on the top surface 424t (not shown) of the etch control layer 424.

[0103] Figure 5 Manufacturing according to some embodiments having Figures 2A to 2CThe flowchart illustrates an example method 500 of the semiconductor device 100 shown in the cross-sectional view. For illustrative purposes, reference will be made to... Figures 6 to 11 , Figures 12A to 12C , Figures 13A to 13C ,and Figures 14A to 14C The example manufacturing process for manufacturing semiconductor device 100 shown is described below. Figure 5 The operation shown is illustrated. Figures 6 to 11 It is along the various stages of manufacturing of the semiconductor device 100 according to some embodiments. Figure 1A and Figure 1B A cross-sectional view of line BB. Figures 12A to 14A It is along the various stages of manufacturing of the semiconductor device 100 according to some embodiments. Figure 1A and Figure 1B The cross-sectional view of line AA. Figures 12B to 14B It is along the various stages of manufacturing of the semiconductor device 100 according to some embodiments. Figure 1A and Figure 1B A cross-sectional view of line BB. Figures 12C to 14C It is along the various stages of manufacturing of the semiconductor device 100 according to some embodiments. Figure 1A and Figure 1B A cross-sectional view of line CC. Operations may be performed in different orders, or not at all, depending on the specific application. It should be noted that method 500 may not produce a complete semiconductor device 100. Therefore, it should be understood that additional processes may be provided before, during, and after method 500, and some other processes may only be briefly described herein. Unless otherwise mentioned, Figure 1A , Figure 1B , Figures 2A to 2C , Figures 6 to 11 , Figures 12A to 12C , Figures 13A to 13C ,and Figures 14A to 14C The descriptions of elements that have the same reference numerals and / or letters are applicable to each other.

[0104] refer to Figure 5 In operation 505, a fin structure is formed on the substrate. For example, such as... Figure 6 As shown, fin structures 106N and 106P are formed on substrate 104. In some embodiments, the fin structure 106N can be formed by etching substrate 104. In some embodiments, the fin structure 106P can be formed by the following steps: (i) etching (not shown) a portion of substrate 104 on the n-well; (ii) depositing a SiGe layer (not shown) on the etched portion of substrate 104; and (iii) etching the SiGe layer and substrate 104 to form the fin structure 106P, as shown. Figure 6 As shown in the figure. In some embodiments, a hard masking layer 626 may be formed on the fin structures 106N and 106P.

[0105] refer to Figure 5 In operation 510, an STI region is formed on the substrate. For example, as shown in reference... Figures 7 to 9 The STI region 120 is formed on the substrate 104. In some embodiments, the formation of the STI region 120 may include the following sequential operations: (i) in Figure 6 A dielectric layer 720 is deposited on the structure, such as Figure 7 As shown; (ii) Perform a chemical mechanical polishing (CMP) process to make the top surfaces of the dielectric layer 720 and the hard mask layer 626 coplanar, as shown. Figure 8 As shown; (iii) removing the hard mask layer 626; and (iv) performing an etching process on the dielectric layer 720 to form Figure 9 The structure.

[0106] refer to Figure 5 In operation 515, an etch control layer is formed on the STI region. For example, as shown in the reference... Figure 10 and Figure 11 The etch control layer 224 is formed on the STI region 120. In some embodiments, the formation of the etch control layer 224 may include the following sequential operations: (i) in Figure 9 A dielectric layer 1024 of material with an etch control layer 224 is deposited on the structure, such as... Figure 10 As shown; and (ii) performing an etching process on dielectric layer 1024 to form Figure 11 The structure. In some embodiments, the top surface 224t of the etch control layer 224 may be substantially coplanar with the top surface of the fin base 106P1. In some embodiments, after the etch control layer 224 is formed, a sacrificial polysilicon structure (not shown) may be formed on the portions of the fin structures 106N and 106P that extend above the top surface 224t of the etch control layer 224 and directly on the etch control layer 224.

[0107] refer to Figure 5 In operation 520, an S / D region and a gate structure are formed on the fin structure. For example, as shown in reference... Figures 12A to 12C As described, S / D regions 110N and 110P, and gate structures 112A, 112BC, 112D, and 112EF are formed on fin structures 106N and 106P. The S / D regions 110N and 110P are... Figure 12A and Figure 12B Not visible in the middle. Gate structures 112A, 112D, and 112EF are in Figure 12B and Figure 12C Not visible in the middle. Gate structure 112BC is in Figure 12C It is not visible in the middle.

[0108] In some embodiments, S / D regions 110N and 110P can be formed on the portions of fin structures 106N and 106P not covered by the sacrificial polysilicon structure. After forming S / D regions 110N and 110P, ESL 116 and ILD layers 118 can be formed, and then the sacrificial polysilicon structure is replaced with gate structures 112A, 112BC, 112D, and 112EF directly on the etch control layer 224, such as... Figure 12A and Figure 12B As shown in the image.

[0109] The formation of gate structures 112A, 112BC, 112D, and 112EF may include the following sequential operations: (i) removing the sacrificial polysilicon structure (not shown); (ii) after forming S / D regions 110N and 110P, forming the IL layer 212A by performing an oxidation process on the portions of fin structures 106N and 10P extending above the top surface 224t of the etch control layer 224, as follows. Figure 12B As shown in the diagram; (iii) a high-k dielectric layer 212B is deposited directly on the IL layer 212A and the etch control layer 224, as shown in the diagram. Figure 12A and Figure 12B As shown; (iv) depositing a conductive layer 212C on the high-k dielectric layer 212B, as shown. Figure 12A and Figure 12B As shown in the diagram; and (v) performing CMP processes on the high-k dielectric layer 212B and the conductive layer 212C to make the top surfaces of ESL 116, IL layer 212A, high-k dielectric layer 212B, and conductive layer 212C substantially coplanar with each other, as shown in the diagram. Figure 12A and Figure 12B As shown in the image.

[0110] refer to Figure 5 In operation 525, an isolation structure is formed to cut the gate structure and the fin structure. For example, see reference... Figures 13A to 13C and Figures 14A to 14C The process involves forming an isolation structure 122A to cleave the gate structure 112BC into gate structures 112B and 112C, and forming an isolation structure 122B to cleave the gate structure 112EF into gate structures 112E and 112F. The process for forming the isolation structures 122A and 122B can be referred to as the CMG process described above. The formation of the isolation structures 122A and 122B may include the following sequential operations: (i) forming isolation trenches 1322A and 1322B (in... Figure 13B and Figure 13C (Not visible in the middle), such as Figures 13A to 13C As shown; (ii) in Figures 13A to 13C(iii) depositing a dielectric layer (not shown) of material having isolation structures 122B and 122A on the structure to fill isolation trenches 1322A and 1322B; and (iii) performing a CMP process on the dielectric layer so that the top surfaces of isolation structures 122A and 122B are substantially coplanar with the top surface of ILD layer 118.

[0111] The formation of isolation trenches 1322A and 1322B may include performing an etching process to etch redundant gate portions of gate structures 112BC and 112EF between fin structures 106N and 106P, and to etch redundant dielectric portions, including gate spacers 114, ESL 116, and portions of the ILD layer 118 on the sidewalls of the redundant gate portions. The etching process may include dry etching using an etchant that has higher etch selectivity for the metal material of the redundant gate portions than for the material of the etching control layer 224. Due to the lower etch selectivity of the etching control layer 224, the etching rate of the etching process can be significantly reduced after the redundant gate portions are removed and the top surface 224t of the etching control layer 224 is exposed in the isolation trenches 1322A and 1322B. As a result, the etching depth of the isolation trenches 1322A and 1322B can be precisely controlled, preventing them from extending into the substrate 104. In some embodiments, the bottom surfaces 1322As and 1322Bs of the isolation trenches 1322A and 1322B are substantially planar due to the reduced etching rate at the etch control layer 224.

[0112] In some embodiments, isolation trench 1322B may extend deeper into the STI region 120 to a distance D3 than isolation trench 1322A, which may extend to a distance D1 within the STI region. This difference in depth between isolation trenches 1322A and 1322B may be due to the higher etch rate of the redundant gate portion of gate structure 112EF compared to the higher etch rate of the redundant gate portion of gate structure 112BC. The higher etch rate may be due to the fact that gate structure 112EF is wider along the X-axis than gate structure 112BC. The discussion of the cross-sectional and depth profiles of isolation structures 122A and 122B applies to the cross-sectional and depth profiles of isolation trenches 1322A and 1322B.

[0113] Figure 15 Manufacturing according to some embodiments having Figures 4A to 4C The flowchart illustrates an example method 1500 of the semiconductor device 100 shown in the cross-sectional view. For illustrative purposes, reference will be made to... Figures 16 to 19 , Figures 20A to 20C , Figures 21A to 21C ,and Figures 22A to 22C The example manufacturing process for manufacturing semiconductor device 100 shown is described below. Figure 15 The operation shown is illustrated. Figures 16 to 19It is along the various stages of manufacturing of the semiconductor device 100 according to some embodiments. Figure 1A and Figure 1B A cross-sectional view of line BB. Figures 20A to 22A It is along the various stages of manufacturing of the semiconductor device 100 according to some embodiments. Figure 1A and Figure 1B The cross-sectional view of line AA. Figures 20B to 22B It is along the various stages of manufacturing of the semiconductor device 100 according to some embodiments. Figure 1A and Figure 1B A cross-sectional view of line BB. Figures 20C to 22C It is along the various stages of manufacturing of the semiconductor device 100 according to some embodiments. Figure 1A and Figure 1B A cross-sectional view of line CC. Operations may be performed in different orders, or not at all, depending on the specific application. It should be noted that method 1500 may not produce a complete semiconductor device 100. Therefore, it should be understood that additional processes may be provided before, during, and after method 1500, and some other processes may only be briefly described herein. Unless otherwise mentioned, Figure 1A , Figure 1B , Figures 4A to 4C , Figures 16 to 19 , Figures 20A to 20C , Figures 21A to 21C ,and Figures 22A to 22C The descriptions of elements that have the same reference numerals and / or letters are applicable to each other.

[0114] refer to Figure 15 Operation 1505 is similar to Figure 5 Operation 505. After operation 1505, a result similar to... Figure 6 The structure. Operation 1510 on... Figure 6 The subsequent processing of the structure will refer to Figure 16 Describe it.

[0115] refer to Figure 15 In operation 1510, an etch control layer and an STI region are formed on the substrate. For example, see reference... Figures 17 to 19 The etching control layer 424 is formed directly on the substrate 104, and an STI region 120 is formed on the etching control layer. The formation of the etching control layer 424 and the STI region 120 may include the following sequential operations: (i) in Figure 6 A dielectric layer 1624 of material with an etch control layer 424 is deposited on the structure, such as... Figure 16 As shown; (ii) in Figure 16 A dielectric layer 1720 with an STI region 120 is deposited on the structure, such as... Figure 17As shown; (iii) Perform a CMP process to make the top surfaces of dielectric layers 1624 and 1720 substantially coplanar with the top surface of hard mask layer 626, as shown. Figure 18 As shown; (iv) removing hard mask layer 626 (not shown); and (v) performing an etching process on dielectric layers 1624 and 1720 to form Figure 19 The structure. In some embodiments, the top surface 424s of the fin sidewall portion of the etching control layer 424 may extend above the top surface 120t of the STI region 120, such as Figure 19 As shown in the figure. In some embodiments, the top surface 424s may be substantially coplanar with the top surface 120t of the STI region 120 (not shown). In some embodiments, after forming the etch control layer 424, a sacrificial polysilicon structure (not shown) may be formed on the portions of the fin structures 106N and 106P extending above the top surface 424s of the etch control layer 424 and directly on the STI region 120.

[0116] refer to Figure 15 In operation 1520, an S / D region and a gate structure are formed on the fin structure. For example, as shown in reference... Figures 20A to 20C As described, S / D regions 110N and 110P, and gate structures 112A, 112BC, 112D, and 112EF are formed on fin structures 106N and 106P. The S / D regions 110N and 110P are... Figure 20A and Figure 20B Not visible in the middle. Gate structures 112A, 112D, and 112EF are in Figure 20B and Figure 20C Not visible in the middle. Gate structure 112BC is in Figure 20C It is not visible in the middle.

[0117] In some embodiments, S / D regions 110N and 110P can be formed on the portions of fin structures 106N and 106P not covered by the sacrificial polysilicon structure. After forming S / D regions 110N and 110P, ESL 116 and ILD layer 118 can be formed, and then the sacrificial polysilicon structure can be replaced with gate structures 112A, 112BC, 112D, and 112EF directly on the STI region 120 and the top surface 424s, as shown. Figure 20A and Figure 20B As shown in the image.

[0118] The formation of gate structures 112A, 112BC, 112D, and 112EF may include the following sequential operations: (i) removing the sacrificial polysilicon structure (not shown); (ii) after forming S / D regions 110N and 110P, forming the IL layer 212A by performing an oxidation process on the portions of fin structures 106N and 106P extending above the top surface 424s of the etch control layer 424, as shown. Figure 20B As shown in the figure; (iii) deposit a high-k dielectric layer 212B directly on the IL layer 212A, as shown in the figure; Figure 20A and Figure 20B As described in the text; (iv) depositing a conductive layer 212C on the high-k dielectric layer 212B, as... Figure 20A and Figure 20B As shown in the diagram; and (v) performing CMP processes on the high-k dielectric layer 212B and the conductive layer 212C to make the top surfaces of ESL 116, ILD 120, the high-k dielectric layer 212B, and the conductive layer 212C substantially coplanar, as shown in the diagram. Figure 20A and Figure 20B As shown in the image.

[0119] refer to Figure 15 In operation 1525, an isolation structure is formed to cleave the gate structure. For example, as shown in reference... Figures 21A to 21C and Figures 22A to 22C The isolation structure 122A is formed to cleave the gate structure 112BC into gate structures 112B and 112C, and the isolation structure 122B is formed to cleave the gate structure 112EF into gate structures 112E and 112F. The formation of the isolation structures 122A and 122B may include the following sequential operations: (i) forming isolation trenches 2122A and 2122B (in...) Figure 21B and Figure 21C (Not visible in the middle), such as Figures 21A to 21C As shown; (ii) in Figures 21A to 21C (iii) depositing a dielectric layer (not shown) of material having isolation structures 122A and 122B on the structure to fill isolation trenches 2122A and 2122B; and (iii) performing a CMP process on the dielectric layer so that the top surfaces of the isolation structures 122A and 122B are substantially coplanar with the top surface of the ILD layer 118.

[0120] The formation of isolation trenches 2122A and 2122B may include performing an etching process to etch redundant gate portions of gate structures 112BC and 112EF between fin structures 106N and 106P, and to etch redundant dielectric portions, including gate spacers 114, ESL 116, and portions of the ILD layer 118 on the sidewalls of the redundant gate portions. The etching process may include dry etching using an etchant that has higher etch selectivity for the metal material of the redundant gate portions than for the material of the etching control layer 424. Due to the lower etch selectivity of the etching control layer 424, the etching rate of the etching process can be significantly reduced after the top surface 424t of the etching control layer 424 is exposed in the isolation trenches 2122A and 2122B. As a result, the etching depth of isolation trenches 2122A and 2122B can be precisely controlled, preventing them from extending into the substrate 104. In some embodiments, due to the reduced etching rate at the etch control layer 424, the substantially planar bottom surfaces 2122As and 2122Bs of the isolation trenches 2122A and 2122B can be achieved. The description of the cross-sectional and depth profiles of the isolation structures 122A and 122B applies to the cross-sectional and depth profiles of the isolation trenches 2122A and 2122B.

[0121] This disclosure provides an example semiconductor device (e.g., semiconductor device 100) having an etch control layer (e.g., etch control layers 224, 324, and 424) between a substrate (e.g., substrate 104) and a gate structure (e.g., gate structures 112A-112F), and example methods (e.g., methods 500 and 1500) for manufacturing the semiconductor device. During the formation of isolation structures (e.g., isolation structures 122A and 122B) in a CMG process, the etch control layer prevents isolation trenches (e.g., isolation trenches 1322A, 1322B, 2122A, and 2122B) from extending into the substrate via an STI region (e.g., STI region 120). In some embodiments, the etch control layers (e.g., etch control layers 224 and 324) may be directly disposed on the STI region, and the bottom surface of the isolation structure may be disposed in the etch control layer or in the STI region. In some embodiments, an etch control layer (e.g., etch control layer 424) may be directly disposed on the substrate, and the bottom surface of the isolation structure may be disposed within the etch control layer. In some embodiments, the etch control layer may have an etch selectivity lower than that of the gate structure to reduce the etch rate of the CMG process after etching the gate structure. Reducing the etch rate after etching the gate structure allows for more precise control over the etch depth of the isolation trenches in the etch control layer and / or the STI region compared to that achieved in a semiconductor device without an etch control layer.

[0122] In some embodiments, a method of manufacturing a semiconductor device includes forming a fin structure having a first fin portion and a second fin portion on a substrate, forming a first dielectric layer on the substrate and on the sidewalls of the first fin portion, forming a second dielectric layer on the first dielectric layer, performing an oxidation process on the second fin portion to form an oxide layer, depositing a gate dielectric layer on the oxide layer and on the second dielectric layer, depositing a gate conductive layer on the gate dielectric layer, and forming an isolation structure extending through the gate conductive layer, the gate dielectric layer, and the second dielectric layer.

[0123] In some embodiments, forming an isolation structure includes: forming an isolation trench having a bottom surface in a first dielectric layer. In some embodiments, forming an isolation structure includes: forming an isolation trench having a bottom surface in a second dielectric layer. In some embodiments, forming an isolation structure includes: etching a gate conductive layer, a gate dielectric layer, and a second dielectric layer to expose a top surface of the first dielectric layer; and depositing a dielectric material on the top surface of the first dielectric layer. In some embodiments, forming an isolation structure includes: forming an isolation trench having a bottom surface of the isolation trench and a top surface of the substrate with a distance of at least about 10 nm. In some embodiments, forming an isolation structure includes: forming an isolation trench having a rectangular cross-sectional profile along a first plane and a trapezoidal cross-sectional profile along a second plane perpendicular to the first plane. In some embodiments, forming an isolation structure includes: forming an isolation trench having a plurality of vertical sidewalls along the first plane and a plurality of inclined sidewalls along the second plane perpendicular to the first plane. In some embodiments, forming a first dielectric layer includes: depositing an oxide layer on a substrate and on a fin structure. In some embodiments, forming a second dielectric layer includes: depositing a nitride layer on the first dielectric layer. In some embodiments, forming the fin structure includes: depositing a silicon-germanium layer on a substrate; etching the silicon-germanium layer to form a second fin portion; and etching the substrate to form a first fin portion.

[0124] In some embodiments, a method of manufacturing a semiconductor device includes forming a fin structure on a substrate, depositing a first dielectric layer on the fin structure and on the substrate, depositing a second dielectric layer on the first dielectric layer, etching the first and second dielectric layers to expose a top portion of the fin structure, depositing a gate dielectric layer on the top portion of the fin structure, depositing a gate conductive layer on the gate dielectric layer, and forming an isolation structure having a bottom surface in the first dielectric layer.

[0125] In some embodiments, depositing the first dielectric layer includes depositing a nitride layer on the fin structure and on a substrate. In some embodiments, depositing the second dielectric layer includes depositing an oxide layer on the first dielectric layer. In some embodiments, etching the first and second dielectric layers includes making the top surface of the fin sidewall portion of the first dielectric layer substantially coplanar with the top surface of the second dielectric layer. In some embodiments, forming an isolation structure includes etching a gate conductive layer, a gate dielectric layer, and a second dielectric layer to expose the top surface of the first dielectric layer. In some embodiments, forming an isolation structure includes forming an isolation trench having a rectangular cross-sectional profile along a first plane and a trapezoidal cross-sectional profile along a second plane perpendicular to the first plane.

[0126] In some embodiments, a semiconductor device includes a substrate, an STI region disposed on the substrate, an etch control layer disposed on the STI region, first and second fin structures disposed on the substrate, a first gate structure and a second gate structure disposed on the first and second fin structures and on the etch control layer, and an isolation structure disposed between the first gate structure and the second gate structure and in the etch control layer.

[0127] In some embodiments, the isolation structure is disposed at a distance of at least about 10 nm above the top surface of the substrate. In some embodiments, the plurality of gate dielectric layers of the first gate structure and the second gate structure are directly disposed on the etch control layer. In some embodiments, the bottom surface of the isolation structure is disposed in a shallow trench isolation region.

[0128] In some embodiments, the semiconductor device includes a substrate, a fin structure, an etch control layer, a shallow trench isolation region, a gate dielectric layer, a gate conductive layer, and an isolation structure. The fin structure is disposed on the substrate and includes fin portions and an oxide layer. The etch control layer is disposed on the substrate and on a plurality of sidewalls of the fin portions. The shallow trench isolation region is disposed on the etch control layer. The gate dielectric layer is disposed on the oxide layer and on the shallow trench isolation region. The gate conductive layer is disposed on the gate dielectric layer. The isolation structure extends through the gate conductive layer, the gate dielectric layer, and the etch control layer, and the isolation structure has a bottom surface located in the shallow trench isolation region or in the etch control layer.

[0129] In some embodiments, the bottom surface of the isolation structure is at least about 10 nm away from the top surface of the substrate. In some embodiments, the isolation structure includes a rectangular cross-sectional profile along a first plane and a trapezoidal cross-sectional profile along a second plane perpendicular to the first plane. In some embodiments, the isolation structure includes a plurality of vertical sidewalls along the first plane and a plurality of inclined sidewalls along the second plane perpendicular to the first plane.

[0130] In some embodiments, the semiconductor device includes a substrate, a fin structure, a shallow trench isolation region, an etch control layer, a gate dielectric layer, a gate conductive layer, and an isolation structure. The fin structure is disposed on the substrate. The shallow trench isolation region is disposed on the fin structure and on the substrate. The etch control layer is disposed on the shallow trench isolation region, wherein a top portion of the fin structure is exposed from the shallow trench isolation region and the etch control layer. The gate dielectric layer is disposed on the top portion of the fin structure. The gate conductive layer is disposed on the gate dielectric layer. The isolation structure extends through the gate conductive layer, the gate dielectric layer, and the shallow trench isolation region, and the isolation structure has a bottom surface located in the shallow trench isolation region or in the etch control layer.

[0131] In some embodiments, the top surface of the fin sidewall portion of the first dielectric layer is substantially coplanar with the top surface of the second dielectric layer. In some embodiments, the isolation structure includes a rectangular cross-sectional profile along a first plane and a trapezoidal cross-sectional profile along a second plane perpendicular to the first plane.

[0132] In some embodiments, the semiconductor device includes a substrate, a shallow trench isolation region, an etch control layer, first and second fin structures, a first gate structure and a second gate structure, and an isolation structure. The shallow trench isolation region is disposed on the substrate. The etch control layer is disposed on the shallow trench isolation region. The first and second fin structures are disposed on the substrate. The first gate structure and the second gate structure are respectively disposed on the first fin structure and the second fin structure and on the etch control layer. The isolation structure is disposed between the first gate structure and the second gate structure and in the etch control layer, wherein the isolation structure has a bottom surface located in the shallow trench isolation region or in the etch control layer.

[0133] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, Include: One substrate; A fin structure is disposed on the substrate, the fin structure comprising a fin portion and an oxide layer; An etching control layer is disposed on the substrate and on multiple sidewalls of the fin portion; A shallow trench isolation zone is provided on the etching control layer; A gate dielectric layer is disposed on the oxide layer and on the shallow trench isolation region; A gate conductive layer is disposed on the gate dielectric layer; as well as An isolation structure extends through the gate conductive layer, the gate dielectric layer and the etch control layer, and the isolation structure has a bottom surface located in the shallow trench isolation region or in the etch control layer.

2. The semiconductor device as claimed in claim 1, characterized in that, The bottom surface of the isolation structure and the top surface of the substrate have a distance of at least 10 nm.

3. The semiconductor device as claimed in claim 1 or 2, characterized in that, The isolation structure includes a rectangular cross-sectional profile along a first plane and a trapezoidal cross-sectional profile along a second plane perpendicular to the first plane.

4. The semiconductor device as claimed in claim 1 or 2, characterized in that, The isolation structure includes a plurality of vertical sidewalls along a first plane and a plurality of inclined sidewalls along a second plane perpendicular to the first plane.

5. A semiconductor device, characterized in that, Include: A fin structure is mounted on a substrate; A shallow trench isolation area is disposed on the fin structure and on the substrate; An etching control layer is disposed on the shallow trench isolation region, wherein a top portion of the fin structure is exposed from the shallow trench isolation region and the etching control layer; A gate dielectric layer is disposed on the top portion of the fin structure; A gate conductive layer is disposed on the gate dielectric layer; as well as An isolation structure extends through the gate conductive layer, the gate dielectric layer and the shallow trench isolation region, and the isolation structure has a bottom surface located in the shallow trench isolation region or in the etch control layer.

6. The semiconductor device as claimed in claim 5, characterized in that, The bottom surface of the isolation structure and the top surface of the substrate have a distance of at least 10 nm.

7. The semiconductor device as claimed in claim 5 or 6, characterized in that, The isolation structure includes a rectangular cross-sectional profile along a first plane and a trapezoidal cross-sectional profile along a second plane perpendicular to the first plane.

8. A semiconductor device, characterized in that, Include: One substrate; A shallow trench isolation area is disposed on the substrate; An etching control layer is disposed on the shallow trench isolation area; The first and second fin structures are disposed on the substrate; The first gate structure and the second gate structure are respectively disposed on the first fin structure and the second fin structure and on the etching control layer; as well as An isolation structure is disposed between the first gate structure and the second gate structure and in the etch control layer, wherein the isolation structure has a bottom surface located in the shallow trench isolation region or in the etch control layer.

9. The semiconductor device as claimed in claim 8, characterized in that, The isolation structure is disposed at a distance of at least 10 nm above a top surface of the substrate.

10. The semiconductor device as claimed in claim 8 or 9, characterized in that, The first gate structure and the second gate structure have multiple gate dielectric layers directly disposed on the etch control layer.

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