Data transmission device

Abstract

The utility model provides a data transmission device. The data transmission device comprises a radio frequency receiving circuit; a radio frequency transmitting circuit; the HDMI processing unit comprises an HDMI decoding circuit and an HDMI encoding circuit and is used for encoding or decoding the data; the frame header and frame tail processing unit comprises a frame header and frame tail decoding circuit and a frame header and frame tail adding circuit and is used for performing frame header and frame tail decoding or frame header and frame tail adding processing on the data; the UDP unvarnished transmission circuit is used for carrying out UDP unvarnished transmission on the data; the FIFO cache circuit is used for temporarily storing data; the first network port is used for receiving UDP transparent transmission data and sending the UDP transparent transmission data to the FIFO cache circuit or sending the data temporarily stored by the FIFO cache circuit to the UDP transparent transmission circuit; the second network port is used for receiving the data temporarily stored by the FIFO cache circuit or sending the data to the FIFO cache circuit; and the interface conversion circuit is used for converting a data format. According to the scheme, the requirements of modern application for high-speed data transmission and low-delay communication can be met, and strong communication performance and flexibility are provided.

Description

Technical Field

[0001] This utility model relates to the field of data transmission technology, and more particularly to a data transmission device. Background Technology

[0002] In modern communication systems, proximity communication and short-range wireless transmission technologies play a crucial role in industrial automation, smart homes, medical devices, and robot control. With the rapid development of the Internet of Things (IoT) and artificial intelligence (AI), the demand for high-speed data transmission and low-latency communication between devices has become increasingly urgent. In these applications, devices need to exchange large amounts of data in real time to achieve precise control and synchronized operation.

[0003] While existing short-range communication technologies have made some progress, they still have some shortcomings. For example, Bluetooth technology is widely used in short-range wireless communication, but its data transmission rate and stability are unsatisfactory in some demanding applications. Bluetooth connections are easily affected by environmental interference, and interference and signal conflicts may occur when multiple devices are connected. Similarly, while Wi-Fi technology offers high data transmission rates, its power consumption is high, making it unsuitable for some low-power applications. Furthermore, Wi-Fi signals have limitations in penetration and transmission distance, and transmission stability decreases in complex environments. Therefore, developing an efficient and reliable short-range communication system is particularly important. Utility Model Content

[0004] The purpose of this invention is to provide a data transmission device that can meet the needs of modern applications for high-speed data transmission and low-latency communication, providing powerful communication performance and flexibility, and ensuring fast, accurate and stable data exchange between devices.

[0005] The technical solution provided by this utility model is as follows:

[0006] This utility model provides a data transmission device, comprising:

[0007] Radio frequency (RF) receiving circuit, used to receive RF signals;

[0008] Radio frequency (RF) transmitting circuit, used to transmit RF signals;

[0009] An HDMI processing unit, including an HDMI decoding circuit and an HDMI encoding circuit, is used to encode or decode data.

[0010] The frame header and frame tail processing unit includes a frame header and frame tail decryption circuit and a frame header and frame tail addition circuit, which are used to perform frame header and frame tail decryption processing or frame header and frame tail addition processing on the data.

[0011] UDP pass-through circuit, used for UDP pass-through of data;

[0012] FIFO buffer circuit, used for temporary data storage;

[0013] The first network port is used to receive UDP transparent data and send it to the FIFO buffer circuit or send data temporarily stored in the FIFO buffer circuit to the UDP transparent circuit;

[0014] The second network port is used to receive data temporarily stored in the FIFO buffer circuit or to send data to the FIFO buffer circuit;

[0015] Interface conversion circuit, used to convert data formats.

[0016] In some implementations, during the data reception phase, the radio frequency receiving circuit receives a first radio frequency signal, the HDMI decoding circuit extracts an HDMI signal from the first radio frequency signal, the frame header and frame tail removal circuit removes the frame header and frame tail of the HDMI signal to obtain clean data, the UDP pass-through circuit receives the clean data and sends it to the FIFO buffer circuit for temporary storage via the first network port, the second network port receives the clean data temporarily stored by the FIFO buffer circuit, and performs format conversion via the interface conversion circuit.

[0017] In some implementations, during the data transmission phase, the interface conversion circuit converts the instruction data sent by the control center and sends the instruction data to the FIFO buffer circuit for temporary storage via the second network port. The first network port receives the instruction data temporarily stored by the FIFO buffer circuit and sends the instruction data to the frame header and frame tail circuit via the UDP pass-through circuit. The frame header and frame tail circuit adds a frame header and a frame tail to the instruction data to obtain encapsulated data. The HDMI encoding circuit encodes the encapsulated data to obtain a second radio frequency signal, and the radio frequency transmission circuit transmits the second radio frequency signal.

[0018] In some embodiments, it further includes a housing, wherein the first network port and the second network port are disposed on one side of the housing.

[0019] In some embodiments, a first HDMI interface and a second HDMI interface are also provided on one side of the housing, and the first HDMI interface and the second HDMI interface are respectively connected to the HDMI decoding circuit and the HDMI encoding circuit.

[0020] In some embodiments, a receiving antenna and a transmitting antenna are also provided on one side of the housing, the receiving antenna being connected to the radio frequency receiving circuit and the transmitting antenna being connected to the radio frequency transmitting circuit.

[0021] In some embodiments, both the receiving antenna and the transmitting antenna are fiberglass antennas.

[0022] In some implementations, the interface conversion circuit is a GMII network interface to an RGMII network interface.

[0023] In some embodiments, a power interface and a signal indicator light are provided on one side of the housing.

[0024] In some embodiments, a filtering circuit and an amplification circuit are further provided between the radio frequency receiving circuit and the HDMI decoding circuit.

[0025] The data transmission device provided by this utility model can meet the needs of modern applications for high-speed data transmission and low-latency communication, provide powerful communication performance and flexibility, and ensure fast, accurate and stable data exchange between devices. Attached Figure Description

[0026] The preferred embodiments will now be described in a clear and easy-to-understand manner, with reference to the accompanying drawings, to further explain the above-mentioned characteristics, technical features, advantages, and implementation methods of this solution.

[0027] Figure 1 This is a schematic diagram of the overall structure of one embodiment of the present utility model;

[0028] Figure 2 This is a schematic diagram of the data receiving stage of one embodiment of the present invention;

[0029] Figure 3 This is a schematic diagram of the data transmission stage of one embodiment of the present invention.

[0030] The diagram is labeled as follows: 1. Housing; 2. Signal indicator light; 3. Power interface; 4. First fixing metal strip; 5. First HDMI interface; 6. Second HDMI interface; 7. Second fixing metal strip; 8. First network port; 9. Second network port; 10. Transmitting antenna; 11. Receiving antenna; 21. RF receiving circuit; 22. HDMI decoding circuit; 23. HDMI encoding circuit; 24. Frame header and frame tail decoding circuit; 25. Frame header and frame tail adding circuit; 26. UDP pass-through circuit; 27. FIFO buffer circuit; 28. Interface conversion circuit; 29. ​​RF transmitting circuit. Detailed Implementation

[0031] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the specific implementation methods of this utility model will be described below with reference to the accompanying drawings. Obviously, the drawings described below are merely some embodiments of this utility model. For those skilled in the art, other drawings and other implementation methods can be obtained based on these drawings without any creative effort.

[0032] To keep the drawings concise, only the parts relevant to this invention are shown schematically in each figure, and they do not represent the actual structure of the product. Furthermore, for ease of understanding, in some figures, only one of the components with the same structure or function is schematically depicted, or only one is labeled. In this document, "one" not only means "only one," but can also mean "more than one."

[0033] In modern communication systems, proximity communication and short-range wireless transmission technologies play a crucial role in industrial automation, smart homes, medical devices, and robot control. With the rapid development of the Internet of Things (IoT) and artificial intelligence (AI), the demand for high-speed data transmission and low-latency communication between devices has become increasingly urgent. In these applications, devices need to exchange large amounts of data in real time to achieve precise control and synchronized operation.

[0034] While existing short-range communication technologies have made some progress, they still have some shortcomings. For example, Bluetooth technology is widely used in short-range wireless communication, but its data transmission rate and stability are unsatisfactory in some demanding applications. Bluetooth connections are easily affected by environmental interference, and interference and signal conflicts may occur when multiple devices are connected. Similarly, while Wi-Fi technology offers high data transmission rates, its high power consumption makes it unsuitable for some low-power applications. Furthermore, Wi-Fi signals have limitations in penetration and transmission distance, and transmission stability decreases in complex environments. Zigbee technology, despite its advantages in low power consumption and mesh network structure, has a low data transmission rate, making it difficult to meet the needs of large data volume transmission. Zigbee is suitable for low-speed sensor networks but performs poorly in high-data-volume applications such as high-definition video transmission. RFID technology is mainly used for simple data transmission and identification, with a short data transmission range and low rate, failing to meet the needs of real-time large data transmission and complex communication. Therefore, developing an efficient and reliable short-range communication system is particularly important.

[0035] This application overcomes the shortcomings of traditional technologies in terms of environmental adaptability, signal stability, transmission rate, and multi-protocol support by employing integrated circuit design, fiberglass antennas, and high-efficiency data packaging and transmission technologies. The system is suitable for various application scenarios such as industrial automation, smart homes, medical equipment, and robot control, providing powerful communication performance and flexibility, ensuring fast, accurate, and stable data exchange between devices. A detailed description is provided below with reference to the accompanying drawings.

[0036] In one embodiment, refer to the appendix to the specification. Figure 2 and Figure 3 This utility model provides a data transmission device, including: an RF receiving circuit 21, an RF transmitting circuit 29, an HDMI processing unit, a frame header and frame tail processing unit, a UDP pass-through circuit 26, a FIFO buffer circuit 27, a first network port 8, a second network port 9, and an interface conversion circuit 28. The HDMI processing unit includes an HDMI decoding circuit 22 and an HDMI encoding circuit 23, and the frame header and frame tail processing unit includes a frame header and frame tail decryption circuit 24 and a frame header and frame tail addition circuit 25. The RF receiving circuit 21, RF transmitting circuit 29, HDMI decoding circuit 22, HDMI encoding circuit 23, frame header and frame tail decryption circuit 24, frame header and frame tail addition circuit 25, UDP pass-through circuit 26, FIFO buffer circuit 27, and interface conversion circuit 28 used in this application are all conventional circuits in the art, and their specific circuit structures will not be described in detail here. The focus of this application is to cleverly combine these circuits to achieve accurate and low-latency data transmission, so as to meet the needs of modern applications for high-speed data transmission and low-latency communication, provide powerful communication performance and flexibility, and ensure fast, accurate, and stable data exchange between devices.

[0037] The radio frequency receiving circuit 21 is used to receive radio frequency signals; the radio frequency transmitting circuit 29 is used to transmit radio frequency signals; the HDMI processing unit includes an HDMI decoding circuit 22 and an HDMI encoding circuit 23, used to encode or decode data; the frame header and frame tail processing unit includes a frame header and frame tail decryption circuit 24 and a frame header and frame tail addition circuit 25, used to decrypt or add frame headers and frame tails to data; the UDP pass-through circuit 26 is used to pass through data via UDP; the FIFO buffer circuit 27 is used to temporarily store data; the first network port 8 is used to receive UDP pass-through data 26 and send it to the FIFO buffer circuit 27 or send the data temporarily stored in the FIFO buffer circuit 27 to the UDP pass-through circuit 26; the second network port 9 is used to receive the data temporarily stored in the FIFO buffer circuit 27 or send data to the FIFO buffer circuit 27; and the interface conversion circuit 28 is used to convert data formats.

[0038] In one specific implementation, during the data reception stage, the RF receiving circuit 21 receives the first RF signal, the HDMI decoding circuit 22 extracts the HDMI signal from the first RF signal, the frame header and frame tail removal circuit 24 removes the frame header and frame tail of the HDMI signal to obtain clean data, the UDP pass-through circuit 26 receives the clean data and sends it to the FIFO buffer circuit 27 for temporary storage through the first network port 8, and the second network port 9 receives the clean data temporarily stored in the FIFO buffer circuit 27 and performs format conversion through the interface conversion circuit 28.

[0039] In another specific implementation, during the data transmission phase, the interface conversion circuit 28 converts the instruction data sent by the control center and sends the instruction data to the FIFO buffer circuit 27 for temporary storage through the second network port 9. The first network port 8 receives the instruction data temporarily stored by the FIFO buffer circuit 27 and sends the instruction data to the frame header and frame tail circuit 25 through the UDP pass-through circuit 26. The frame header and frame tail circuit 25 adds a frame header and frame tail to the instruction data to obtain encapsulated data. The HDMI encoding circuit 23 encodes the encapsulated data to obtain the second radio frequency signal. The radio frequency transmission circuit 29 transmits the second radio frequency signal.

[0040] Specifically, the RF receiving circuit 21 and the RF transmitting circuit 29 are key components for wireless signal transmission in the system. At the receiving end, the RF receiving circuit 21 receives RF signals from the external environment and converts them into processable digital video signals. This circuit uses a high-sensitivity RF receiver, supporting the 2.4GHz and 5GHz frequency bands, and is capable of receiving high-definition signals. The received signal enters the system through a fiberglass antenna and undergoes internal filtering and amplification to improve signal quality and stability. Preferably, a filtering circuit and an amplification circuit are also provided between the RF receiving circuit 21 and the HDMI decoding circuit 22. The fiberglass antenna has good weather resistance and mechanical strength, making it suitable for various environmental conditions. Specific implementation methods include using a bandpass filter to filter out unwanted frequency band signals and retain signals of the desired frequency band, using a low-noise amplifier (LNA) to improve the signal-to-noise ratio (SNR) of the received signal, and demodulating the RF signal into a baseband signal using a demodulator. The received digital video signal is then transmitted to the HDMI decoding circuit 22 to begin video data decoding and processing.

[0041] At the transmitting end, the RF transmitting circuit 29 is responsible for converting the processed digital video signal back into an RF signal and transmitting it through a fiberglass antenna. This circuit supports high-power output and can adjust the transmission power to adapt to different transmission distances. The video signal is first processed by the HDMI encoding circuit 23, which adds the necessary frame headers and trailers to form a standard HDMI signal. Then, the RF transmitting circuit 29 modulates the HDMI signal, using QAM (Quadrature Amplitude Modulation) technology to convert it into an RF signal, which is then transmitted to the external environment through the fiberglass antenna. The design of this circuit takes into account parameters such as the frequency, bandwidth, and power of the RF signal to ensure the effectiveness and reliability of signal transmission.

[0042] The HDMI processing unit is the core component for processing video data. At the receiving end, the HDMI decoding circuit 22 extracts the HDMI video signal from the signal received by the RF receiving circuit 21. This circuit uses TMDS technology and is capable of processing high-definition video signals up to 1080p. Specifically, it converts the TMDS signal into RGB or YUV video data, extracts the embedded clock signal from the TMDS signal to synchronize the data stream, and parses the video frame structure to extract valid video data. The decoded video data is then transmitted to the video data deframe header / tail circuit 24 for further processing.

[0043] At the transmitting end, the HDMI encoding circuit 23 is responsible for re-encoding the processed video data into an HDMI signal. This circuit also uses TMDS technology and supports the HDMI 1.4 standard, enabling it to process high-resolution video data. Specifically, it converts RGB or YUV video data into a TMDS signal, embeds a synchronization clock signal into the TMDS signal, and encapsulates the video data frames according to the HDMI standard. After processing by the video data header and trailer circuit 25, the video data is transmitted to the HDMI encoding circuit 23. The encoded HDMI signal is then output to the RF transmitting circuit 29 through the HDMI interface, ready for RF transmission.

[0044] The frame header and trailer processing unit is responsible for encapsulating and decapsulating video data. At the receiving end, the video data decapsulation circuit 24 receives video data from the HDMI decoding circuit 23, removes the frame header and trailer from the data, and extracts the clean video data. This circuit uses a custom frame format; the frame header contains synchronization information and data verification information, and the frame trailer contains data integrity check information. Specifically, this involves identifying and removing the frame header information of the video data, verifying the integrity of the video data to ensure it is error-free, and removing the frame trailer information. The decapsulated data is then transmitted to the UDP pass-through circuit 26 for network transmission.

[0045] At the transmitting end, the video data header and trailer circuit 25 is responsible for encapsulating the video data. The video data sent by the host through the interface conversion circuit 28 is first appended with a header and trailer in the video data header and trailer circuit 25. This circuit uses an efficient data packetization algorithm to ensure data integrity and synchronization during transmission. Specifically, it generates a header containing synchronization and data verification information, encapsulates the video data between the header and trailer, and generates a trailer containing data integrity check information. The encapsulated video data is then transmitted to the HDMI encoding circuit 23 for encoding and preparation for radio frequency transmission.

[0046] The UDP pass-through circuit 26 is the core component for high-speed network data transmission in the system. At the receiving end, the video data, after being processed by the frame header / tail cutter circuit 24, is transmitted over the network via the UDP pass-through circuit 26. This circuit uses the MAC layer inside the FPGA to implement the UDP protocol stack, supporting gigabit Ethernet transmission rates. The UDP pass-through circuit is responsible for packaging video data into UDP packets and sending them out through network port 1. The circuit design considers the connectionless nature of the UDP protocol, ensuring fast data transmission and low latency. Specifically, the implementation involves using FPGA logic to implement MAC layer protocol processing, encapsulating video data into UDP packets, and sending the UDP packets through the first network port 8.

[0047] At the sending end, the UDP pass-through circuit 26 receives data packets transmitted from the second network port 9, unpacks them, and extracts the video data. The unpacked data is then transmitted to the video data frame header and trailer circuit 25 for further processing and encapsulation. Specifically, this involves receiving UDP data packets through the second network port 9, extracting video data from the UDP data packets, and verifying the integrity of the video data to ensure accuracy. The design of the UDP pass-through circuit 26 prioritizes transmission efficiency and data integrity, ensuring efficient and reliable video data transmission over the network.

[0048] The FIFO buffer circuit 27 serves to buffer data and balance the data flow in the system. At the receiving end, data sent from the first network port 8 first enters the FIFO1 buffer circuit 27 for temporary storage and balancing. The FIFO1 buffer circuit 27 is designed as an asynchronous FIFO structure, using dual-port RAM technology, which can effectively handle data streams at different rates, avoiding data loss and congestion. Specifically, it uses dual-port RAM to implement an asynchronous FIFO structure, supporting data read / write at different rates, and uses FIFO control logic to synchronize data read / write, buffering incoming data to ensure a smooth data flow.

[0049] At the transmitting end, the FIFO buffer circuit 27 receives data sent from the second network port 9, performs temporary storage and balancing processing. The buffered data is received through the first network port 8 and transmitted to the video data frame header and trailer circuit 25.

[0050] Interface conversion circuit 28 is responsible for converting network interface standards. In this application, interface conversion circuit 28 is a GMII network interface to an RGMII network interface. At the receiving end, data buffered by FIFO buffer circuit 27 is received through the second network port 9 and transmitted to interface conversion circuit 28. This circuit uses a 125MHz clock signal generated by a phase-locked loop (PLL) to ensure data synchronization and efficient conversion. Interface conversion circuit 28 converts the received GMII data to the RGMII standard, ensuring that the data can be correctly received and processed by the host. Specifically, this includes using a PLL to generate a 125MHz clock signal for GMII to RGMII data synchronization, converting GMII signals to RGMII signals, and ensuring data synchronization and integrity during the conversion process.

[0051] At the transmitting end, the interface conversion circuit 28 receives data sent from the host and converts it into RGMII standard data. The converted data is then sent out through the second network port 9 and buffered by the FIFO buffer circuit 27. Specifically, this involves converting the GMII signal to an RGMII signal to ensure data synchronization and integrity during the conversion process, and using a phase-locked loop (PLL) to generate a 125MHz clock signal to ensure data synchronization. This circuit design is simple and efficient, adaptable to the conversion requirements of different network interface standards, and improves system compatibility and flexibility.

[0052] In one embodiment, refer to the appendix to the specification. Figure 1The data testing device of this application includes: a housing 1, which is made of metal to protect the device from external physical damage and electromagnetic interference, and to ensure stable operation of internal components. A first network port 8 and a second network port 9 are located on one side of the housing 1. A first HDMI interface 5 and a second HDMI interface 6 are also provided on one side of the housing 1, which are respectively connected to the HDMI decoding circuit 22 and the HDMI encoding circuit 23. A receiving antenna 11 and a transmitting antenna 10 are also provided on one side of the housing 1. The receiving antenna 11 is connected to the radio frequency receiving circuit 21, and the transmitting antenna 10 is connected to the radio frequency transmitting circuit 29. Preferably, both the receiving antenna 11 and the transmitting antenna 10 are fiberglass antennas. A power interface 3 and a signal indicator light 2 are provided on one side of the housing 1. This data transmission device can be firmly installed on a rack or other fixed position by fixing metal strips (first fixing metal strip 4 and second fixing metal strip 7) located at the bottom of the housing 1, ensuring that the device will not move or vibrate during use, and at the same time helping to reduce the mechanical stress on the device during operation, preventing poor contact or damage caused by vibration or movement.

[0053] In robot control, the device is used for real-time video monitoring and control of the robot's movements. The device is powered on via power interface 3, and indicator light 2 shows that the device is powered on and operational. The receiving antenna 11 receives the robot's radio frequency signals. The first HDMI interface 5 decodes the robot's camera video signals, processes the frame headers and trailers, and then transmits the video data to the robot control center via UDP. The data is transmitted to the control center via the first network port 8, and then buffered in the FIFO buffer circuit 27. The data buffered in the FIFO buffer circuit 27 is received via the second network port 9. The data is then converted via interface conversion circuit 28.

[0054] Command data from the control center is converted via interface conversion circuit 28. The command data is transmitted through the second network port 9. The command data is then buffered by FIFO buffer circuit 27. Data buffered by FIFO buffer circuit 27 is received through the first network port 8. The received data is transparently transmitted to the robot via UDP. The transmitted data undergoes additional frame header and trailer processing. The data is encoded via the second HDMI interface 6 and converted into control signals. These control signals are sent to the robot via transmitting antenna 10 to control the robot's movements.

[0055] This system employs a high-sensitivity RF receiver and a high-power RF transmitter, combined with a fiberglass antenna, significantly improving the quality of signal reception and transmission. Optimized signal processing links ensure stable communication in complex environments, which is particularly important in scenarios requiring high-reliability communication, such as emergency rescue and on-site command. The system supports multiple video and network interfaces (HDMI, GMII, RGMII) and can process high-resolution video signals (1080p). This allows the system to be widely used in smart homes, medical monitoring, industrial control, intelligent transportation, and other fields, meeting the short-range high-frequency data communication needs of different scenarios. The integration of multi-functional modules using FPGA reduces hardware usage and lowers system costs. Simultaneously, the reconfigurability of FPGA allows the system to flexibly respond to different application requirements, extending equipment lifespan and further reducing overall costs. The system design is simple, efficient, and easy to integrate and deploy. Adopting a modular design concept, each module works independently but closely together, improving system reliability and maintainability. For enterprises, this can significantly improve production efficiency and equipment uptime, reducing downtime maintenance costs. The system achieves high-speed network data transmission through a UDP pass-through circuit, supporting gigabit Ethernet transmission rates and ensuring low latency and high throughput. Specific test data shows that in a standard gigabit network environment, the system's UDP data transmission latency is less than 1ms, and the data throughput reaches over 850Mbps. The HDMI processing unit adopts TMDS technology, supporting 1080p high-definition video signal processing. Optimized video data processing ensures high-quality video signal transmission. In practical application tests, the system can stably process 60 frames per second of 1080p video signals without frame loss. The RF circuit, combined with a fiberglass antenna, achieves high-quality RF communication in the 2.4GHz and 5.8GHz frequency bands. In actual testing, the system's effective communication distance in an indoor environment exceeds 30 meters, with stable signal transmission and a bit error rate below 10⁻⁶. The FIFO buffer circuit is designed with an asynchronous FIFO structure, effectively handling data streams at different rates and avoiding data loss and congestion. In data transmission tests at different rates, the FIFO buffer circuit operates stably, ensuring smooth data transmission and real-time processing. The GMII to RGMII converter uses a 125MHz clock signal generated by a phase-locked loop (PLL) to ensure synchronous and efficient data conversion from GMII to RGMII. In actual testing, the converter maintained data transmission accuracy and low latency even under high-load network conditions, achieving a conversion efficiency of over 99%.

[0056] It should be noted that the above embodiments can be freely combined as needed. The above description is only a preferred embodiment of this utility model. It should be pointed out that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this utility model, and these improvements and modifications should also be considered within the protection scope of this utility model.

Claims

1. A data transmission device, characterized in that, include: Radio frequency (RF) receiving circuit, used to receive RF signals; Radio frequency (RF) transmitting circuit, used to transmit RF signals; An HDMI processing unit, including an HDMI decoding circuit and an HDMI encoding circuit, is used to encode or decode data. The frame header and frame tail processing unit includes a frame header and frame tail decryption circuit and a frame header and frame tail addition circuit, which are used to perform frame header and frame tail decryption processing or frame header and frame tail addition processing on the data. UDP pass-through circuit, used for UDP pass-through of data; FIFO buffer circuit, used for temporary data storage; The first network port is used to receive UDP transparent data and send it to the FIFO buffer circuit or send data temporarily stored in the FIFO buffer circuit to the UDP transparent circuit. The second network port is used to receive data temporarily stored in the FIFO buffer circuit or to send data to the FIFO buffer circuit; Interface conversion circuit, used to convert data formats.

2. The data transmission device according to claim 1, characterized in that, During the data reception phase, the radio frequency receiving circuit receives a first radio frequency signal, the HDMI decoding circuit extracts an HDMI signal from the first radio frequency signal, the frame header and frame tail removal circuit removes the frame header and frame tail of the HDMI signal to obtain clean data, the UDP pass-through circuit receives the clean data and sends it to the FIFO buffer circuit for temporary storage through the first network port, the second network port receives the clean data temporarily stored in the FIFO buffer circuit and performs format conversion through the interface conversion circuit.

3. The data transmission device according to claim 1, characterized in that, During the data transmission phase, the interface conversion circuit converts the instruction data sent by the control center and sends the instruction data to the FIFO buffer circuit for temporary storage through the second network port. The first network port receives the instruction data temporarily stored by the FIFO buffer circuit and sends the instruction data to the frame header and frame tail circuit through the UDP pass-through circuit. The frame header and frame tail circuit adds a frame header and a frame tail to the instruction data to obtain encapsulated data. The HDMI encoding circuit encodes the encapsulated data to obtain a second radio frequency signal, and the radio frequency transmission circuit transmits the second radio frequency signal.

4. The data transmission device according to claim 1, characterized in that, Also includes: The housing has the first and second network ports located on one side.

5. The data transmission device according to claim 4, characterized in that, One side of the housing is also provided with a first HDMI interface and a second HDMI interface, which are respectively connected to the HDMI decoding circuit and the HDMI encoding circuit.

6. The data transmission device according to claim 4, characterized in that, A receiving antenna and a transmitting antenna are also provided on one side of the housing. The receiving antenna is connected to the radio frequency receiving circuit, and the transmitting antenna is connected to the radio frequency transmitting circuit.

7. The data transmission device according to claim 6, characterized in that, Both the receiving antenna and the transmitting antenna are fiberglass antennas.

8. The data transmission device according to claim 1, characterized in that, The interface conversion circuit is a GMII network interface to an RGMII network interface.

9. The data transmission device according to claim 4, characterized in that, A power interface and a signal indicator light are provided on one side of the housing.

10. The data transmission device according to claim 2, characterized in that, A filtering circuit and an amplification circuit are also provided between the radio frequency receiving circuit and the HDMI decoding circuit.

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