Anti-backflow protection circuit and power supply system

Abstract

The utility model provides an anti-backflow protection circuit and a power supply system, and relates to the technical field of power supply protection circuits, the anti-backflow protection circuit comprises an input, an output, an MOS tube Q1, a diode, a second switch unit, a third switch unit, a boost bootstrap unit and a comparison unit, the input is connected with the output through the MOS tube Q1; the first input end of the comparison unit is connected with the input, and the second input end is connected with the output; the output end of the comparison unit is connected with the control end of the second switch unit and the boost bootstrap unit, and the control end of the third switch unit is connected to the common end through the two ends in the second switch unit; the grid electrode of the MOS tube Q1 is connected with the input through the third switch unit, the source electrode and the grid electrode of the MOS tube Q1 are connected through a diode, and the boost bootstrap unit is connected with the input and the grid electrode of the MOS tube Q1. According to the utility model, the problems of large power consumption, large noise and high cost in a large current occasion in the existing anti-backflow protection circuit are solved.

Description

TECHNICAL FIELD

[0001] The utility model relates to the technical field of power protection circuit especially relates to a kind of anti-inversion protection circuit and power system. BACKGROUND

[0002] In the electronic design of ordinary times, power supply circuit is essential, and in order to prevent misoperation or its circuit failure leads to power reverse connection or output voltage greater than input voltage, engineers will increase anti-inversion circuit to get design, increase the safety of power operation.

[0003] The existing anti-inversion circuit is usually made of Schottky diode and integrated chip, however, in the above design, Schottky diode has large power consumption in large current field, and integrated chip has large port noise and high cost. UTILITY MODEL CONTENT

[0004] In view of the deficiencies in the prior art, the utility model provides an anti-inversion protection circuit and power system, which solves the problems of large current field, large noise and high cost in the existing anti-inversion protection circuit.

[0005] At least one embodiment of the utility model provides an anti-inversion protection circuit, comprising: input VIN, output VOUT, MOS tube Q1, diode D1, second switch unit, third switch unit, boost bootstrap unit and comparison unit, wherein,

[0006] The input VIN is connected to the output VOUT in sequence through the source and drain of the MOS tube Q1;

[0007] The first input end of the comparison unit is connected to the input VIN, and the second input end of the comparison unit is connected to the output VOUT;

[0008] The output end of the comparison unit is connected to the control end of the second switch unit and the input end of the boost bootstrap unit respectively, and the control end of the third switch unit is connected to the common end through the two ends in the second switch unit;

[0009] The gate of the MOS tube Q1 is connected to the input VIN through the two ends of the third switch unit, the source and gate of the MOS tube Q1 are connected through the diode D1, and the output end of the boost bootstrap unit is connected to the input VIN and the gate of the MOS tube Q1 respectively, so as to superimpose the voltage output by the boost bootstrap unit and input VIN on the gate of the MOS tube Q1.

[0010] The technical scheme disclosed by the utility model has at least the following beneficial effects:

[0011] When the circuit is normally powered and works, the voltage of the input VIN is higher than the voltage of the output VOUT, the output end of the comparison unit outputs a corresponding level, and the second switch unit is controlled to be non-conductive, at this time, the third switch unit is also non-conductive, after receiving the above level, the boost bootstrap unit starts to boost, so as to superimpose the voltage output by the input VIN on the gate of the MOS tube Q1, and then the MOS tube Q1 is completely conductive, thereby reducing the power consumption of the circuit.

[0012] When the circuit output appears reverse flow (the voltage of the output VOUT is higher than the voltage of the input VIN), the comparison unit outputs a corresponding another level, and the second switch unit is controlled to be conductive, after receiving the above another level, the boost bootstrap unit enters an off state, at the same time, the third switch unit is in a conductive state, and the source and the gate of the MOS tube Q1 are short-circuited through the diode D1, the driving voltage of the MOS tube Q1 is equal to the voltage of the input VIN, and then the power MOS tube Q1 is turned off, and the reverse flow protection function is realized.

[0013] Through the above setting, when the MOS tube Q1 normally works, it can be completely conductive, and the resistance is much smaller than that of the Schottky diode, so that the overall circuit power consumption is reduced, and the circuit does not need to be controlled by an integrated chip, but only needs to be controlled by the comparison unit and the boost bootstrap unit, thereby greatly reducing the cost, not generating noise, and being more flexible.

[0014] In the anti-reverse flow protection circuit provided in one of the embodiments of the utility model, the boost bootstrap unit comprises a timer 555, a capacitor C2, a capacitor C3, a diode D2 and a diode D3, wherein,

[0015] The input end of the timer 555 is connected with the output end of the comparison unit;

[0016] The output end of the timer 555 is connected with the input VIN in sequence through the cathode and the anode of the capacitor C3 and the diode D3;

[0017] The output end of the timer 555 is also connected with the gate of the MOS tube Q1 in sequence through the anode and the cathode of the capacitor C3 and the diode D2;

[0018] The two ends of the capacitor C2 are connected with the cathode of the diode D2 and the anode of the diode D3 respectively.

[0019] The technical scheme provided by the utility model has at least the following beneficial effects:

[0020] Through the above setting, when the timer 555 receives one of the levels output by the comparison unit, the timer 555 can generate a square wave to charge and discharge the capacitor C3, and obtain a first output voltage, at the same time, the input voltage VIN is superimposed with the above-mentioned first output voltage through the freewheeling diode D3, and the second output voltage is obtained, and then the voltage higher than the input VIN is obtained through the rectifier D2, the filter capacitor C2, rectification and filtering, and then applied to the gate of the MOS tube Q1, at this time, the source of the MOS tube Q1 is the input VIN, and then the MOS tube Q1 is completely turned on;

[0021] When the timer 555 receives the other level output by the comparison unit, the timer 555 is closed.

[0022] In the anti-inversion protection circuit provided in one of the embodiments of the utility model, the circuit further comprises an inverter U2, and the comparison unit comprises a comparator U1, wherein,

[0023] The cathode of the comparator U1 is connected with the input VIN, the anode of the comparator U1 is connected with the output VOUT, the output end of the comparator U1 is connected with the control end of the second switch unit, and the output end of the comparator U1 is further connected with the input end of the timer 555 through the inverter U2.

[0024] The technical scheme disclosed by the utility model has at least the following beneficial effects:

[0025] When the circuit is normally powered and works, the voltage of the input VIN is higher than the voltage of the output VOUT, the output end of the comparator U1 is at a low level, and then the second switch unit is not turned on, at this time, the third switch unit is also not turned on, the low level is inverted to obtain a high level through the inverter U2, the boost bootstrap unit starts to boost after receiving the high level, so as to superimpose the voltage of the boost bootstrap unit and the input VIN on the gate of the MOS tube Q1, and then the MOS tube Q1 is completely turned on, thereby reducing the power consumption of the circuit.

[0026] When the circuit output appears inversion (the voltage of the output VOUT is higher than the voltage of the input VIN), the comparison unit outputs a corresponding high level, and controls the second switch unit to be turned on, the high level is inverted to obtain a low level through the inverter U2, the boost bootstrap unit enters an off state after receiving the low level, at the same time, the third switch unit is in a turned-on state, and the source and the gate of the MOS tube Q1 are short-circuited through the diode D1, the driving voltage of the MOS tube Q1 is equal to the voltage of the input VIN, and then the power MOS tube Q1 is turned off, and the anti-inversion protection function is realized.

[0027] In the anti-backflow protection circuit provided in one of the embodiments of the utility model, the comparison unit further comprises resistance R5 and resistance R6, wherein,

[0028] The output VOUT is connected with the anode of the comparator U1 through the resistance R5 and the resistance R6.

[0029] The output VOUT is connected with the anode of the comparator U1 through the resistance R5 and the resistance R6.

[0030] The utility model discloses the technical scheme provided at least has the following beneficial effects:

[0031] The voltage input of the anode of the comparator U1 can be provided by the voltage division of the resistance R5 and the resistance R6.

[0032] In the anti-backflow protection circuit provided in one of the embodiments of the utility model, the comparison unit further comprises resistance R7 and capacitor C4, wherein,

[0033] The output VOUT is connected with the anode of the comparator U1 through the resistance R5 and the resistance R6.

[0034] The utility model discloses the technical scheme provided at least has the following beneficial effects:

[0035] The capacitor C4 is charged through the resistance R7 when the power is rapidly applied, so that the bias of the input VIN in the comparison unit is faster than the output VOUT, and the false triggering is avoided.

[0036] In the anti-backflow protection circuit provided in one of the embodiments of the utility model, the comparison unit further comprises diode D4, wherein,

[0037] The anode of the diode D4 is connected with the anode of the comparator U1, and the cathode of the diode D4 is connected with the output VOUT through the resistance R5.

[0038] The utility model discloses the technical scheme provided at least has the following beneficial effects:

[0039] The diode D4 can be used to change the voltage on the capacitor C4 with the voltage of the output VOUT when backflow occurs, so that the excess electricity is quickly discharged after the MOS tube Q1 is turned off.

[0040] In the anti-backflow protection circuit provided in one of the embodiments of the utility model, the comparison unit further comprises resistance R3 and resistance R4, wherein,

[0041] The input VIN is connected with the cathode of the comparator U1 through the resistance R3.

[0042] The input VIN is connected to the common terminal through the resistor R3 and the resistor R4 in turn.

[0043] The technical scheme provided by the utility model has at least the following beneficial effects:

[0044] The voltage input for the cathode of the comparator U1 can be provided by the voltage division of the resistor R3 and the resistor R4.

[0045] In the anti-inversion protection circuit provided in one of the embodiments of the utility model, the circuit further comprises a capacitor C1, and the output VOUT is connected to the common terminal through the capacitor C1.

[0046] The technical scheme provided by the utility model has at least the following beneficial effects:

[0047] The capacitor C1 can be used to ensure that the power-off of the output VOUT is slower than the input VIN after the voltage of the input VIN is turned off, so as to generate reliable signals on the comparison unit.

[0048] In the anti-inversion protection circuit provided in one of the embodiments of the utility model, the second comparison unit is a MOS tube Q2, and the gate of the MOS tube Q2 is connected to the output end of the comparison unit.

[0049] The drain of the MOS tube Q2 is connected to the common terminal, and the source of the MOS tube Q2 is connected to the control end of the third switch unit.

[0050] The third comparison unit comprises a triode Q3, a resistor R2 and a resistor R1, wherein,

[0051] The base of the triode Q3 is connected to the source of the MOS tube Q2 through the resistor R2.

[0052] The base of the triode Q3 is connected to the emitter thereof through the resistor R1, and the gate of the MOS tube Q1 is connected to the input VIN in turn through the emitter and the collector of the triode Q3.

[0053] The utility model further provides a power supply system, and the power supply port of the power supply system is connected with the anti-inversion protection circuit. BRIEF DESCRIPTION OF DRAWINGS

[0054] Figure 1 It is the circuit connection relation schematic view of the utility model about an anti-inversion protection circuit.

[0055] Figure 2 It is the specific circuit diagram of the utility model about an anti-inversion protection circuit.

[0056] In the drawings, the components represented by each reference numeral are listed as follows:

[0057] S1, second switch unit, S2, third switch unit, S3, boost bootstrap unit, S4, comparison unit. DETAILED DESCRIPTION

[0058] The principles and characteristics of the utility model are described below in combination with the drawings, and the examples are only used to explain the utility model and are not used to limit the scope of the utility model.

[0059] The utility model provides a kind of anti-flood protection circuit, please refer to Figure 1 As shown in the figure, comprising: input VIN, output VOUT, MOS tube Q1, diode D1, second switch unit S1, third switch unit S2, boost bootstrap unit S3 and comparison unit S4, wherein,

[0060] The input VIN is connected with output VOUT in sequence through the source and drain of the MOS tube Q1;

[0061] The first input end of the comparison unit S4 is connected with the input VIN, and the second input end of the comparison unit S4 is connected with the output VOUT;

[0062] The output end of the comparison unit S4 is connected with the control end of the second switch unit S1 and the input end of the boost bootstrap unit S3 respectively, and the control end of the third switch unit S2 is connected with the common end through the two ends in the second switch unit S1;

[0063] The gate of the MOS tube Q1 is connected with the input VIN through the two ends of the third switch unit S2, the source and gate of the MOS tube Q1 are connected through the diode D1, and the output end of the boost bootstrap unit S3 is connected with the input VIN and the gate of the MOS tube Q1 respectively, so as to superimpose the voltage output by the boost bootstrap unit S3 and the input VIN on the gate of the MOS tube Q1.

[0064] When the circuit is powered on and works normally, the voltage of the input VIN is higher than the voltage of the output VOUT, the output end of the comparison unit S4 outputs corresponding level, and the second switch unit S1 is not turned on, at this time, the third switch unit S2 is also not turned on, and the boost bootstrap unit S3 starts bootstrap boost after receiving the above level, so as to superimpose the voltage output by the boost bootstrap unit S3 and the input VIN on the gate of the MOS tube Q1, and then completely turn on the MOS tube Q1, thereby reducing the power consumption of the circuit;

[0065] When the circuit output appears reverse flow (the voltage of the output VOUT is higher than the voltage of the input VIN), the comparison unit S4 outputs a corresponding another level, and controls the second switch unit S1 to be turned on, and the boost bootstrap unit S3 enters the off state after receiving the another level, and the third switch unit S2 is also in the on state, and the source and the gate of the MOS tube Q1 are short-circuited through the diode D1, the driving voltage of the MOS tube Q1 is equal to the voltage of the input VIN, and then the off of the power MOS tube Q1 is completed, and the reverse flow protection function is realized.

[0066] Through the above setting, the circuit can be completely turned on when the MOS tube Q1 normally works, the resistance is much smaller than the Schottky diode, the overall circuit power consumption is reduced, the circuit does not need to be controlled by an integrated chip, only needs to be controlled by the comparison unit S4 and the boost bootstrap unit S3, the cost is greatly reduced, noise is not generated, and the flexibility is higher.

[0067] Specifically, please refer to the following figures: Figure 1 Figure 2 The boost bootstrap unit S3 comprises a timer 555, a capacitor C2, a capacitor C3, a diode D2 and a diode D3, wherein,

[0068] The input end of the timer 555 is connected with the output end of the comparison unit S4;

[0069] The output end of the timer 555 is connected with the input VIN in sequence through the capacitor C3 and the cathode and the anode of the diode D3;

[0070] The output end of the timer 555 is further connected with the gate of the MOS tube Q1 in sequence through the capacitor C3 and the anode and the cathode of the diode D2;

[0071] It should be understood that the timer 555 comprises a pin DIS, a pin RESET, a pin OUT, a pin THRES, a pin OUT, a pin CON, a pin VCC and a pin GND, wherein,

[0072] The input end of the timer 555 is the pin RESET, the output end of the timer 555 is the pin OUT, and in addition, in order to ensure the normal operation of the timer 555, the pin VCC is connected with a power supply, the pin GND is grounded, and the pin THRES is connected with the pin TR, and on one hand, the pin THRES and the pin TR are grounded through the capacitor C19, and on the other hand, the pin THRES and the pin OUT are connected through the resistor R16;

[0073] The two ends of the capacitor C2 are connected with the cathode of the diode D2 and the anode of the diode D3 respectively. ​

[0074] Through the above setting, when the timer 555 receives one of the levels output by the comparison unit S4, the timer 555 can generate a square wave to charge and discharge the capacitor C3, and obtain a first output voltage, at the same time, the input voltage VIN passes through the freewheeling diode D3, and the above first output voltage is superimposed to obtain a second output voltage, and then the voltage higher than the input VIN is obtained through the rectifier D2, the filter capacitor C2, rectification and filtering, and then applied to the gate of the MOS tube Q1, at this time, the source of the MOS tube Q1 is the input VIN, and then the MOS tube Q1 is completely turned on;

[0075] When the timer 555 receives the other level output by the comparison unit S4, the timer 555 is turned off.

[0076] Specifically, the circuit further comprises an inverter U2, and the comparison unit S4 comprises a comparator U1, wherein,

[0077] The cathode of the comparator U1 is connected with the input VIN, the anode of the comparator U1 is connected with the output VOUT, the output end of the comparator U1 is connected with the control end of the second switch unit S1, and the output end of the comparator U1 is further connected with the input end of the timer 555 through the inverter U2.

[0078] When the circuit is normally powered and works, the voltage of the input VIN is higher than the voltage of the output VOUT, the output end of the comparator U1 is at a low level, and then the second switch unit S1 is not turned on, at this time, the third switch unit S2 is also not turned on, the low level is inverted to a high level after passing through the inverter U2, the boost bootstrap unit S3 starts to boost after receiving the high level, so as to superimpose the voltage output by the boost bootstrap unit S3 and the input VIN to the gate of the MOS tube Q1, and then the MOS tube Q1 is completely turned on, thereby reducing the power consumption of the circuit;

[0079] When the circuit output appears reverse flow (the voltage of the output VOUT is higher than the voltage of the input VIN), the comparison unit S4 outputs a corresponding high level, and controls the second switch unit S1 to be turned on, the high level is inverted to a low level after passing through the inverter U2, the boost bootstrap unit S3 enters an off state after receiving the above low level, at the same time, the third switch unit S2 is in a turned-on state, and the source and the gate of the MOS tube Q1 are short-circuited through the diode D1, the driving voltage of the MOS tube Q1 is equal to the voltage of the input VIN, and then the MOS tube Q1 is turned off, thereby realizing the reverse flow protection function.

[0080] Specifically, the comparison unit S4 further comprises a resistor R5 and a resistor R6, wherein,

[0081] The output VOUT is connected to the anode of the comparator U1 through the resistor R5.

[0082] The output VOUT is further connected to the common terminal through the resistor R5 and the resistor R6 in sequence.

[0083] The voltage input for the anode of the comparator U1 can be provided through the voltage division of the resistor R5 and the resistor R6.

[0084] Specifically, the comparison unit S4 further comprises a resistor R7 and a capacitor C4, wherein,

[0085] The output VOUT is connected to the anode of the comparator U1 through the resistor R5 and the resistor R7 in sequence, and the anode of the comparator U1 is further connected to the common terminal through the capacitor C4.

[0086] The capacitor C4 is charged through the resistor R7 during fast power-up, so as to ensure that the input VIN is biased faster than the output VOUT in the comparison unit S4, thereby avoiding false triggering.

[0087] Specifically, the comparison unit S4 further comprises a diode D4, wherein,

[0088] The anode of the diode D4 is connected to the anode of the comparator U1, and the cathode of the diode D4 is connected to the output VOUT through the resistor R5.

[0089] The diode D4 can be used to follow the voltage change of the output VOUT on the capacitor C4 after the MOS tube Q1 is turned off during back-priming, so as to quickly discharge the excess electricity.

[0090] Specifically, the comparison unit S4 further comprises a resistor R3 and a resistor R4, wherein,

[0091] The input VIN is connected to the cathode of the comparator U1 through the resistor R3.

[0092] The input VIN is further connected to the common terminal through the resistor R3 and the resistor R4 in sequence.

[0093] The voltage input for the cathode of the comparator U1 can be provided through the voltage division of the resistor R3 and the resistor R4.

[0094] Specifically, the circuit further comprises a capacitor C1, and the output VOUT is connected to the common terminal through the capacitor C1.

[0095] The capacitor C1 can be used to ensure that the output VOUT is powered down slower than the input VIN after the voltage of the input VIN is turned off, so as to generate a reliable signal on the comparison unit S4.

[0096] Specifically, the second comparison unit S4 is a MOS tube Q2, a gate of the MOS tube Q2 is connected with an output end of the comparison unit S4;

[0097] A drain of the MOS tube Q2 is connected with a common end, a source of the MOS tube Q2 is connected with a control end of the third switch unit S2;

[0098] The third comparison unit S4 comprises a triode Q3, a resistor R2 and a resistor R1, wherein,

[0099] A base of the triode Q3 is connected with the source of the MOS tube Q2 through the resistor R2;

[0100] The base of the triode Q3 is connected with an emitter thereof through the resistor R1, and a gate of the MOS tube Q1 is connected with the input VIN in sequence through the emitter and a collector of the triode Q3.

[0101] In summary, working states of the circuit are as follows:

[0102] When the circuit is powered on and works normally, the input VIN is divided by the resistor R4 and the resistor R3, and the voltage of the output VOUT is divided by the resistor R5 and the resistor R6, and when the voltage received by the cathode end of the comparator U1 is greater than the voltage received by the anode end of the comparator U1, the output end of the comparator U1 outputs a low level to the gate of the MOS tube Q2, and then controls the MOS tube Q2 to be not conductive, at this time, the triode Q3 is also not conductive, and after the low level is flipped by the inverter U2, a high level is obtained, when the aforementioned high level is received by the pin RESET of the timer 555, the pin OUT of the timer 555 can generate a square wave to charge and discharge the capacitor C3, and a first output voltage is obtained, at the same time, the input voltage VIN is superimposed with the aforementioned first output voltage through the freewheeling diode D3, and a second output voltage is obtained, and after rectification and filtering through the rectifier D2 and the filter capacitor C2, a voltage higher than the input VIN is obtained to be applied to the gate of the MOS tube Q1, at this time, the source of the MOS tube Q1 is the input VIN, and then the MOS tube Q1 is completely conductive;

[0103] When the circuit output appears reverse flow (the voltage of the output VOUT is higher than the voltage of the input VIN), when the voltage received by the cathode end of the comparator U1 is less than the voltage received by the anode end of the comparator U1 after the voltage of the output VOUT is divided by the resistance R5 and the resistance R6 and the input VIN is divided by the resistance R4 and the resistance R3, the output end of the comparator U1 outputs a high level to the gate of the MOS tube Q2, thereby controlling the MOS tube Q2 to be turned on, and the high level is inverted to obtain a low level after the inverter U2, when the timer 555 receives the low level, the timer 555 enters an off state, and since the MOS tube Q2 is turned on, the input voltage generates a bias on the bias resistor R1 and the resistor R2, so that the triode Q3 is also in a conductive state, and the source and the gate of the MOS tube Q1 are short-circuited through the diode D1, the driving voltage of the MOS tube Q1 is equal to the voltage of the input VIN, thereby completing the off of the power MOS tube Q1, and realizing the reverse flow protection function.

[0104] The utility model further provides a power supply system, the power supply port of power supply system is connected with one kind of anti reverse flow protection circuit as above.

[0105] In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second" can be explicitly or implicitly included at least one feature. In the description of the utility model, the meaning of "a plurality of" is at least two, for example, two, three, etc., unless otherwise specifically limited.

[0106] In the utility model, unless otherwise specifically defined and limited, the terms "installation", "connection", "connection", "fixing" and the like should be understood in a broad sense, for example, it can be fixedly connected, or it can be detachably connected, or it can be integrated; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium, it can be the communication or interaction relationship between two elements, unless otherwise specifically limited. For ordinary skilled in the art, the specific meaning of the above terms in the utility model can be understood according to the specific circumstances.

[0107] In the description of the present specification, the description referring to the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. Furthermore, the person skilled in the art can combine and combine the different embodiments or examples described in the present specification and the features of the different embodiments or examples, without contradiction.

[0108] Although the embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application, and the person skilled in the art can make changes, modifications, replacements and modifications to the above embodiments within the scope of the present application.

Claims

1. A backfeed protection circuit, characterized by The circuit comprises: an input VIN, an output VOUT, a MOS transistor Q1, a diode D1, a second switch unit (S1), a third switch unit (S2), a boost bootstrap unit (S3) and a comparison unit (S4), wherein, the input VIN is connected to the output VOUT through the source and the drain of the MOS transistor Q1 in sequence; a first input end of the comparison unit (S4) is connected to the input VIN, and a second input end of the comparison unit (S4) is connected to the output VOUT; an output end of the comparison unit (S4) is connected to the control end of the second switch unit (S1) and the input end of the boost bootstrap unit (S3) respectively, and the control end of the third switch unit (S2) is connected to a common end through both ends in the second switch unit (S1); the gate of the MOS transistor Q1 is connected to the input VIN through both ends of the third switch unit (S2), the source of the MOS transistor Q1 is connected to the gate through the diode D1, and the output end of the boost bootstrap unit (S3) is connected to the input VIN and the gate of the MOS transistor Q1 respectively to superimpose the voltage output by the boost bootstrap unit (S3) and the input VIN on the gate of the MOS transistor Q1.

2. The reverse flow protection circuit according to claim 1, wherein The boost bootstrap unit (S3) comprises: a timer 555, a capacitor C2, a capacitor C3, a diode D2 and a diode D3, wherein, the input end of the timer 555 is connected to the output end of the comparison unit (S4); the output end of the timer 555 is connected to the input VIN through the capacitor C3 and the cathode and the anode of the diode D3 in sequence; the output end of the timer 555 is also connected to the gate of the MOS transistor Q1 through the capacitor C3 and the anode and the cathode of the diode D2 in sequence; 3. A reverse flow protection circuit according to claim 2, wherein both ends of the capacitor C2 are connected to the cathode of the diode D2 and the anode of the diode D3 respectively. The circuit further comprises an inverter U2, and the comparison unit (S4) comprises a comparator U1, wherein, 4. A reverse flow protection circuit according to claim 3, wherein the cathode of the comparator U1 is connected to the input VIN, the anode of the comparator U1 is connected to the output VOUT, the output end of the comparator U1 is connected to the control end of the second switch unit (S1), and the output end of the comparator U1 is also connected to the input end of the timer 555 through the inverter U2. The comparison unit (S4) further comprises a resistor R5 and a resistor R6, wherein, the output VOUT is connected to the anode of the comparator U1 through the resistor R5; 5. A reverse flow protection circuit according to claim 4, wherein the output VOUT is also connected to a common end through the resistor R5 and the resistor R6 in sequence. The comparison unit (S4) further comprises a resistor R7 and a capacitor C4, wherein, 6. A reverse flow protection circuit according to claim 5, wherein, the output VOUT is connected to the anode of the comparator U1 through the resistor R5 and the resistor R7 in sequence, and the anode of the comparator U1 is also connected to a common end through the capacitor C4. The comparison unit (S4) further comprises a diode D4, wherein, An anode of the diode D4 is connected to an anode of the comparator U1, and a cathode of the diode D4 is connected to the output VOUT through a resistor R5.

7. A reverse flow protection circuit according to claim 6, wherein The comparison unit (S4) further comprises a resistor R3 and a resistor R4, wherein, The input VIN is connected to a cathode of the comparator U1 through the resistor R3; The input VIN is further connected to a common terminal through the resistor R3 and the resistor R4 in sequence.

8. The reverse flow protection circuit of claim 1, wherein, The circuit further comprises a capacitor C1, and the output VOUT is connected to the common terminal through the capacitor C1.

9. The reverse flow protection circuit of claim 1, wherein, The circuit further comprises a second comparison unit and a third comparison unit, the second comparison unit is a MOS tube Q2, a gate of the MOS tube Q2 is connected to an output terminal of the comparison unit (S4); A drain of the MOS tube Q2 is connected to the common terminal, and a source of the MOS tube Q2 is connected to a control terminal of the third switch unit (S2); The third comparison unit comprises a triode Q3, a resistor R2 and a resistor R1, wherein, A base of the triode Q3 is connected to the source of the MOS tube Q2 through the resistor R2; The base of the triode Q3 is connected to an emitter thereof through the resistor R1, and a gate of the MOS tube Q1 is connected to the input VIN through the emitter and a collector of the triode Q3 in sequence.

10. A power supply system characterized by comprising: The power supply system is connected with the anti-backflow protection circuit according to any one of claims 1 to 9.

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