Display control circuit and electronic equipment

Abstract

The utility model discloses a display control circuit and electronic equipment, and belongs to the technical field of electronic circuits. A first wireless communication circuit converts a wireless communication signal into a wired communication signal; the first control circuit outputs an enable signal according to the wired communication signal; the signal buffer circuit buffers the display driving signal according to the enable signal of the first level, or cuts off the output of the display driving signal according to the enable signal of the second level; the display circuit performs display according to the buffered display driving signal; the first level is opposite to the second level; therefore, the use convenience is improved, and the hardware cost is reduced.

Description

Technical Field

[0001] This application belongs to the field of electronic circuit technology, and in particular relates to a display control circuit and electronic device. Background Technology

[0002] In recent years, with the booming performance industry, including concerts and stage displays, the rental of LED displays has also become extremely popular. Meanwhile, the industry trend is towards faster, safer, easier-to-operate, and more multifunctional displays.

[0003] Existing rental LED displays are assembled from multiple large LED cabinets, typically powered by a receiving card that provides the display drive signal. Usually, turning the display on and off requires either software settings from the receiving card manufacturer or hardware control (such as shutting off the power, adding buttons or switches to each display). Replacing the receiving card necessitates adapting to its new software control method, leading to heavy reliance on the receiving card manufacturer and inconvenience. Directly controlling the display by shutting off the power or adding buttons or switches to each display results in high hardware costs. Therefore, a convenient and cost-effective display control circuit is lacking. Utility Model Content

[0004] The purpose of this application is to provide a display control circuit and electronic device, which aims to solve the problems of low convenience and high cost of existing solutions for controlling the on / off state of a display screen.

[0005] This application provides a display control circuit, connected to a display circuit, including:

[0006] A first wireless communication circuit is used to receive wireless communication signals and convert the wireless communication signals into wired communication signals;

[0007] A first control circuit, connected to the first wireless communication circuit, is used to output an enable signal according to the wired communication signal;

[0008] A signal buffer circuit, connected to the first control circuit and the display circuit, is used to receive the display driving signal and buffer the display driving signal according to the first level enable signal, or to disconnect the output of the display driving signal according to the second level enable signal.

[0009] The display circuit is used to display according to the buffered display driving signal;

[0010] The first level is the opposite of the second level.

[0011] In one embodiment, the signal buffer circuit includes multiple signal buffer modules, the display circuit includes multiple display modules, and the multiple signal buffer modules are connected to the multiple display modules in a one-to-one correspondence; the enable signal includes multiple sub-enable signals, and the display drive signal includes multiple sub-display drive signals;

[0012] The signal buffer module is connected to the first control circuit and the display module, and is used to buffer the sub-display drive signal according to the sub-enable signal of the first level, or to disconnect the output of the sub-display drive signal according to the sub-enable signal of the second level.

[0013] The display module is used to display based on the buffered sub-display driving signal.

[0014] In one embodiment, the signal buffer module includes a signal transceiver;

[0015] The output enable terminal of the transceiver serves as the sub-enable signal input terminal of the signal buffer module and is connected to the first control circuit to input the sub-enable signal; the first, second, third, fourth, fifth, sixth, seventh, and eighth data input terminals of the transceiver together serve as the sub-display drive signal input terminals of the signal buffer module. The transceiver is used to input the sub-display drive signal; the first, second, third, fourth, fifth, sixth, seventh, and eighth data output terminals of the transceiver together serve as the buffered sub-display drive signal output terminals of the signal buffer module to output the buffered sub-display drive signal; the direction control terminal of the transceiver is connected to the first power supply.

[0016] In one embodiment, the display control circuit further includes:

[0017] The second control circuit is used to output control signals;

[0018] A second wireless communication circuit, connected to the second control circuit, is used to convert the control signal into a wireless communication signal.

[0019] In one embodiment, the display control circuit further includes:

[0020] Function key circuit, used to output function key signals according to operation;

[0021] The second control circuit is specifically used to output the control signal according to the function key signal.

[0022] In one embodiment, the second control circuit includes a first microprocessor;

[0023] The first general-purpose input / output (GPIO) terminal, the second general-purpose input / output (GPIO) terminal, the third general-purpose input / output (GPIO) terminal, and the fourth general-purpose input / output (GPIO) terminal of the first microprocessor are collectively used as the control signal output terminal of the second control circuit and are connected to the second wireless communication circuit to transmit the control signal.

[0024] In one embodiment, the second wireless communication circuit includes a first wireless transceiver chip, a first antenna, a first inductor, a second inductor, a third inductor, a first capacitor, a second capacitor, and a third capacitor.

[0025] The SPI chip select signal terminal, SPI clock signal terminal, SPI input signal terminal, and SPI output signal terminal of the first wireless transceiver chip are collectively used as the control signal input terminal of the second wireless communication circuit and connected to the second control circuit to input the control signal. The first antenna terminal of the first wireless transceiver chip, the first end of the first inductor, and the first end of the second inductor are connected. The second antenna terminal of the first wireless transceiver chip, the second end of the first inductor, and the first end of the third inductor are connected. The second end of the third inductor and the first end of the second capacitor are connected. The second end of the second capacitor and the first end of the third capacitor are connected to the first antenna. The power supply terminal of the first wireless transceiver chip, the first end of the first capacitor, and the second end of the second inductor are connected. The second ends of the first capacitor and the second ends of the third capacitor are connected to the power ground.

[0026] In one embodiment, the first wireless communication circuit includes a second wireless transceiver chip, a second antenna, a fourth inductor, a fifth inductor, a sixth inductor, a fourth capacitor, a fifth capacitor, and a sixth capacitor.

[0027] The SPI chip select signal terminal, SPI clock signal terminal, SPI input signal terminal, and SPI output signal terminal of the second wireless transceiver chip together serve as the wired communication signal output terminal of the first wireless communication circuit, and are connected to the first control circuit to output the wired communication signal; the first antenna terminal of the second wireless transceiver chip, the first terminal of the fourth inductor, and the first terminal of the fifth inductor are connected; the second antenna terminal of the second wireless transceiver chip, the second terminal of the fourth inductor, and the first terminal of the sixth inductor are connected; the second terminal of the sixth inductor is connected to the first terminal of the fifth capacitor; the second terminal of the fifth capacitor, the first terminal of the sixth capacitor, and the second antenna are connected; the power supply terminal of the second wireless transceiver chip, the first terminal of the fourth capacitor, and the second terminal of the fifth inductor are connected; the second terminals of the fourth capacitor and the second terminals of the sixth capacitor are connected to the power ground.

[0028] In one embodiment, the first control circuit includes a second microprocessor, a first resistor, a second resistor, a third resistor, and a fourth resistor;

[0029] The first, second, third, and fourth general-purpose input / output (GPIO) terminals of the second microprocessor together serve as the wired communication signal input terminals of the first control circuit, connected to the first wireless communication circuit to input the wired communication signal; the fifth GPIO terminal of the second microprocessor is connected to the first end of the first resistor, and the second end of the first resistor serves as the first sub-enable signal output terminal of the first control circuit, connected to the first signal buffer module to output the first sub-enable signal; the sixth GPIO terminal of the second microprocessor is connected to the second... The first end of the first resistor is connected, and the second end of the second resistor serves as the second sub-enable signal output terminal of the first control circuit, connected to the second signal buffer module to output the second sub-enable signal; the seventh general-purpose input / output terminal of the second microprocessor is connected to the first end of the third resistor, and the second end of the third resistor serves as the third sub-enable signal output terminal of the first control circuit, connected to the third signal buffer module to output the third sub-enable signal; the eighth general-purpose input / output terminal of the second microprocessor is connected to the first end of the fourth resistor, and the second end of the fourth resistor serves as the fourth sub-enable signal output terminal of the first control circuit, connected to the fourth signal buffer module to output the fourth sub-enable signal.

[0030] This application also provides an electronic device, which includes the above-described display control circuit.

[0031] The beneficial effects of this application embodiment compared with the prior art are as follows: When the signal buffer circuit receives the first level enable signal, it buffers the display drive signal to output the buffered display drive signal. When it receives the second level enable signal, it disconnects the output of the display drive signal. Thus, the on / off state of the display circuit can be controlled solely by the level of the enable signal output by the first control circuit. Even if different receiver cards are replaced and different display drive signals are input, there is no need to readjust the logic of the receiver card controlling the on / off state of the display circuit, thereby improving the ease of use. Furthermore, the display control circuit provided by this application does not require the addition of additional button circuits or power off switches for different display circuits, reducing hardware costs and further improving the ease of use. Attached Figure Description

[0032] To more clearly illustrate the technical applications in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a schematic diagram of a display control circuit provided in one embodiment of this application;

[0034] Figure 2 A schematic diagram of another structure of the display control circuit provided in one embodiment of this application;

[0035] Figure 3 A schematic diagram of another structure of the display control circuit provided in one embodiment of this application;

[0036] Figure 4 A schematic diagram of another structure of the display control circuit provided in one embodiment of this application;

[0037] Figure 5 This is a partial example circuit schematic diagram of a display control circuit provided in an embodiment of this application. Detailed Implementation

[0038] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0039] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0040] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0041] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0042] Figure 1 A schematic diagram of a display control circuit according to an embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are described in detail below:

[0043] The aforementioned display control circuit is connected to the display circuit and includes a first wireless communication circuit 10, a first control circuit 20, and a signal buffer circuit 30.

[0044] The first wireless communication circuit 10 is used to access wireless communication signals and convert wireless communication signals into wired communication signals.

[0045] The first control circuit 20 is connected to the first wireless communication circuit 10 and is used to output an enable signal according to the wired communication signal.

[0046] The signal buffer circuit 30 is connected to the first control circuit 20 and the display circuit. It is used to receive the display drive signal and buffer the display drive signal according to the first level enable signal, or disconnect the output of the display drive signal according to the second level enable signal.

[0047] The display circuit is used to display based on the buffered display drive signal.

[0048] The first level is the opposite of the second level.

[0049] The first level can be low, and the second level can be high; or

[0050] The first voltage level can be high, and the second voltage level can be low.

[0051] In specific implementation, when the wireless communication signal carries power-on information, the first wireless communication circuit 10 outputs a wired communication signal carrying power-on information based on the wireless communication signal carrying power-on information, the first control circuit 20 outputs a low-level enable signal based on the wired communication signal carrying power-on information, the signal buffer circuit 30 buffers the display drive signal based on the low-level enable signal, and the display circuit displays based on the buffered display drive signal.

[0052] When the wireless communication signal carries power-off information, the first wireless communication circuit 10 outputs a wired communication signal carrying power-off information based on the wireless communication signal carrying power-off information, the first control circuit 20 outputs a high-level enable signal based on the wired communication signal carrying power-off information, the signal buffer circuit 30 disconnects the output of the display drive signal based on the high-level enable signal, and the display circuit stops displaying.

[0053] When the wireless communication signal carries delayed shutdown information, the first wireless communication circuit 10 outputs a wired communication signal carrying delayed shutdown information according to the wireless communication signal carrying delayed shutdown information. The first control circuit 20 receives the wired communication signal carrying power-on information, first maintains a low-level enable signal output, and then outputs a high-level enable signal after a preset time, so that the display circuit stops displaying after a preset time.

[0054] In summary, the operating state of the display circuit can be controlled simply by changing the level of the enable signal, improving ease of use; no hardware modifications to the display circuit are required, reducing costs.

[0055] In today's intelligent world, the first wireless communication circuit 10 can realize wireless communication, reduce the construction of hardware equipment, realize efficient connection between various types of devices, and thus realize the intelligent application of various display circuits.

[0056] As an example rather than a limitation, such as Figure 2 As shown, the signal buffer circuit 30 includes multiple signal buffer modules 31, the display circuit includes multiple display modules, and the multiple signal buffer modules 31 are connected to the multiple display modules one by one; the enable signal includes multiple sub-enable signals, and the display drive signal includes multiple sub-display drive signals.

[0057] The signal buffer module 31 is connected to the first control circuit 20 and the display module, and is used to buffer the sub-display drive signal according to the sub-enable signal of the first level, or to disconnect the output of the sub-display drive signal according to the sub-enable signal of the second level.

[0058] The display module is used to display based on the buffered sub-display drive signal.

[0059] By accepting multiple sub-display drive signals through multiple signal buffer modules 31, the delay time for buffering sub-display drive signals is reduced, thereby improving the response speed of the display module.

[0060] As an example rather than a limitation, such as Figure 3 As shown, the display control circuit also includes a second control circuit 40 and a second wireless communication circuit 50.

[0061] The second control circuit 40 is used to output control signals.

[0062] The second wireless communication circuit 50 is connected to the second control circuit 40 and is used to convert control signals into wireless communication signals.

[0063] By incorporating a second control circuit 40, the display control circuit can output control signals carrying different information based on operational inputs, thus enriching its functionality. Simultaneously, controlling the display circuit via wireless communication signals enhances its control flexibility.

[0064] As an example rather than a limitation, such as Figure 4 As shown, the display control circuit also includes a function key circuit 60.

[0065] The function key circuit 60 is used to output function key signals according to the operation.

[0066] The second control circuit 40 is specifically used to output control signals based on the function key signals.

[0067] As an example and not a limitation, the display control circuit also includes a reset button circuit.

[0068] The reset button circuit is used to output a reset button signal according to the operation, and the microprocessor in the second control circuit 40 is used to reset according to the reset button signal.

[0069] In a specific implementation, the function key circuit 60 may include a power-on key circuit, a power-off key circuit, and a delayed power-off key circuit.

[0070] The power button circuit outputs a power button signal based on the operation. The second control circuit 40 outputs a control signal carrying power-on information based on the power button signal. The second wireless communication circuit 50 outputs a wireless communication signal carrying power-on information based on the control signal carrying power-on information, so that the display circuit can display the information.

[0071] The power off button circuit outputs a power off button signal based on the operation. The second control circuit 40 outputs a control signal carrying power off information based on the power off button signal. The second wireless communication circuit 50 outputs a wireless communication signal carrying power off information based on the control signal carrying power off information, so that the display circuit stops displaying.

[0072] The delayed shutdown button circuit outputs a delayed shutdown button signal based on the operation. The second control circuit 40 outputs a control signal carrying delayed shutdown information based on the shutdown button signal. The second wireless communication circuit 50 outputs a wireless communication signal carrying delayed shutdown information based on the control signal carrying delayed shutdown information. The display circuit stops displaying after a preset time.

[0073] The operation of the display circuit is controlled through hardware circuitry, improving ease of use.

[0074] Figure 5 The illustration shows a partial example circuit structure of a display control circuit provided in an embodiment of this application. For ease of explanation, only the parts related to the embodiment of this application are shown, and are described in detail below:

[0075] The signal buffer module 31 includes a signal transceiver U5.

[0076] The output enable terminal OE of the transceiver U5 serves as the sub-enable signal input terminal of the signal buffer module 31, and is connected to the first control circuit 20 to input the sub-enable signal. The first data input terminal A0, the second data input terminal A1, the third data input terminal A2, the fourth data input terminal A3, the fifth data input terminal A4, the sixth data input terminal A5, the seventh data input terminal A6, and the eighth data input terminal A7 of the transceiver U5 together serve as the sub-display drive signal input terminals of the signal buffer module 31. The signal transceiver U5 is used to input the sub-display drive signal. The first data output terminal B0, the second data output terminal B1, the third data output terminal B2, the fourth data output terminal B3, the fifth data output terminal B4, the sixth data output terminal B5, the seventh data output terminal B6, and the eighth data output terminal B7 of the signal transceiver U5 together serve as the buffered sub-display drive signal output terminal of the signal buffer module 31 to output the buffered sub-display drive signal. The direction control terminal DIR of the signal transceiver U5 is connected to the first power supply.

[0077] It should be noted that resistor-capacitor filtering components can be set at each data output terminal of the signal transceiver U5 to improve the stability of the display control circuit.

[0078] It should be noted that if the direction control terminal DIR of the transceiver U5 is connected to the power ground, then the A0-A7 ports of the transceiver U5 can be used for output signals, and the B0-B7 ports can be used for input signals.

[0079] This circuit has a high degree of integration and is easy to use.

[0080] The second control circuit 40 includes a first microprocessor U1.

[0081] The first general-purpose input / output terminal PB12, the second general-purpose input / output terminal PB13, the third general-purpose input / output terminal PB14, and the fourth general-purpose input / output terminal PB15 of the first microprocessor U1 together serve as the control signal output terminal of the second control circuit 40, and are connected to the second wireless communication circuit 50 to send control signals.

[0082] The fifth general-purpose input / output terminal PB4 of the first microprocessor U1 serves as the power-on button signal input terminal of the second control circuit 40, and is connected to the power-on button to input the power-on button signal; the sixth general-purpose input / output terminal PB3 of the first microprocessor U1 serves as the power-off button signal input terminal of the second control circuit 40, and is connected to the power-off button to input the power-off button signal; the seventh general-purpose input / output terminal PA15 of the first microprocessor U1 serves as the delayed power-off button signal input terminal of the second control circuit 40, and is connected to the delayed power-off button to input the delayed power-off button signal; the external reset terminal NRST of the first microprocessor U1 serves as the reset button signal input terminal of the second control circuit 40, and is connected to the reset button to input the reset button signal.

[0083] This circuit is simple and reliable.

[0084] The second wireless communication circuit 50 includes a first wireless transceiver chip U2, a first antenna ANT1, a first inductor L1, a second inductor L2, a third inductor L3, a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0085] The SPI chip select signal terminal CSN, the SPI clock signal terminal SCK, the SPI input signal terminal MOSI, and the SPI output signal terminal MISO of the first wireless transceiver chip U2 are collectively used as the control signal input terminal of the second wireless communication circuit 50 and are connected to the second control circuit 40 to input control signals. The first antenna ANT1 terminal RFP of the first wireless transceiver chip U2 is connected to the first end of the first inductor L1 and the first end of the second inductor L2. The second antenna ANT2 terminal RFN of the first wireless transceiver chip U2 is connected to the second end of the first inductor L1 and the first end of the third inductor L3. The second end of the third inductor L3 is connected to the first end of the second capacitor C2. The second end of the second capacitor C2 and the first end of the third capacitor C3 are connected to the first antenna ANT1. The power supply terminal VDD_PA of the first wireless transceiver chip U2 is connected to the first end of the first capacitor C1 and the second end of the second inductor L2. The second ends of the first capacitor C1 and the second ends of the third capacitor C3 are connected to the power ground.

[0086] The first wireless transceiver chip, U2, operates in the 2.4GHz ISM band, has low power consumption, and is easy to use.

[0087] The first wireless communication circuit 10 includes a second wireless transceiver chip U3, a second antenna ANT2, a fourth inductor L4, a fifth inductor L5, a sixth inductor L6, a fourth capacitor C4, a fifth capacitor C5, and a sixth capacitor C6.

[0088] The SPI chip select signal terminal CSN, the SPI clock signal terminal SCK, the SPI input signal terminal MOSI, and the SPI output signal terminal MISO of the second wireless transceiver chip U3 together serve as the wired communication signal output terminal of the first wireless communication circuit 10, and are connected to the first control circuit 20 to output a wired communication signal. The first antenna ANT2 terminal RFP, the first terminal of the fourth inductor L4, and the first terminal of the fifth inductor L5 of the second wireless transceiver chip U3 are connected. The second antenna ANT2 terminal RFN, the second terminal of the fourth inductor L4, and the first terminal of the sixth inductor L6 of the second wireless transceiver chip U3 are connected. The second terminal of the sixth inductor L6 is connected to the first terminal of the fifth capacitor C5. The second terminal of the fifth capacitor C5, the first terminal of the sixth capacitor C6, and the second antenna ANT2 are connected. The power supply terminal VDD_PA of the second wireless transceiver chip U3, the first terminal of the fourth capacitor C4, and the second terminal of the fifth inductor L5 are connected. The second terminals of the fourth capacitor C4 and the second terminals of the sixth capacitor C6 are connected to the power ground.

[0089] The second wireless transceiver chip U2 operates in the 2.4GHz ISM band, has low power consumption, and can realize medium- and long-range wireless communication, improving the flexibility of the display control circuit.

[0090] The first control circuit 20 includes a second microprocessor U4, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4.

[0091] The first general purpose input / output (GPIO) terminals PB12, PB13, PB14, and PB15 of the second microprocessor U4 together serve as the wired communication signal input terminals of the first control circuit 20, connected to the first wireless communication circuit 10 to input wired communication signals; the fifth GPIO terminal PA4 of the second microprocessor U4 is connected to the first end of the first resistor R1, and the second end of the first resistor R1 serves as the first sub-enable signal output terminal of the first control circuit 20, connected to the first signal buffer module 31 to output the first sub-enable signal; the sixth GPIO terminal PA5 of the second microprocessor U4 is connected to... The first end of the second resistor R2 is connected to the second signal buffer module 31, which serves as the second sub-enable signal output terminal of the first control circuit 20. The seventh general-purpose input / output terminal PA6 of the second microprocessor U4 is connected to the first end of the third resistor R3. The second end of the third resistor R3 serves as the third sub-enable signal output terminal of the first control circuit 20, which serves as the third signal buffer module 31. The eighth general-purpose input / output terminal PA0 of the second microprocessor U4 is connected to the first end of the fourth resistor R4. The second end of the fourth resistor R4 serves as the fourth sub-enable signal output terminal of the first control circuit 20, which serves as the fourth signal buffer module 31.

[0092] By limiting the current of the enable signals of each resistor pair, the stability of the display control circuit is improved.

[0093] The power button circuit includes the first button S1.

[0094] The first end of the first button S1 serves as the power button signal output terminal of the power button circuit to output the power button signal; the second end of the first button S1 is connected to the power ground.

[0095] The power off button circuit includes a second button S2.

[0096] The first end of the second button S2 serves as the power-off button signal output terminal of the power-on button circuit to output the power-off button signal; the second end of the second button S2 is connected to the power ground.

[0097] The delayed shutdown button circuit includes a third button S3.

[0098] The first terminal of the third button S3 serves as the delayed shutdown button signal output terminal of the power-on button circuit, outputting a delayed shutdown button signal; the second terminal of the third button S3 is connected to the power ground.

[0099] The reset button circuit includes a fourth button, S4.

[0100] The first end of the fourth button S4 serves as the reset button signal output terminal of the power-on button circuit to output the reset button signal; the second end of the fourth button S4 is connected to the power ground.

[0101] The following is based on the working principle. Figure 5 Further explanation is provided below:

[0102] Figure 5 The example uses four signal buffer circuits 30 and four display modules. In actual use, the number of signal buffer circuits 30 and display modules can be set according to actual needs.

[0103] When the first button S1 is pressed, the first terminal of the first button S1 outputs a power-on button signal to the fifth general-purpose input / output terminal PB4 of the first microprocessor U1. Based on the power-on button signal, the first microprocessor U1 outputs control signals carrying power-on information from its first general-purpose input / output terminal PB12, second general-purpose input / output terminal PB13, third general-purpose input / output terminal PB14, and fourth general-purpose input / output terminal PB15 to the SPI chip select signal terminal CSN, the SPI clock signal terminal SCK, and the first wireless transceiver chip U2. The first wireless transceiver chip U2 has an SPI input signal terminal MOSI and an SPI output signal terminal MISO. Based on a control signal carrying power-on information, the first wireless transceiver chip U2 outputs a wireless communication signal carrying power-on information to the second antenna ANT2 via the first antenna ANT1. The second antenna ANT2 converts the wireless communication signal carrying power-on information into a communication signal carrying power-on information. The second wireless transceiver chip U3 outputs a communication signal carrying power-on information from its SPI chip select signal terminal CSN, SPI clock signal terminal SCK, and SPI input signal terminal MISO. The MOSI and the SPI output signal terminal MISO of the second wireless transceiver chip U3 output wired communication signals carrying power-on information to the first general-purpose input / output terminal PB12, the second general-purpose input / output terminal PB13, the third general-purpose input / output terminal PB14, and the fourth general-purpose input / output terminal PB15 of the second microprocessor U4. Based on the wired communication signal carrying power-on information, the second microprocessor U4 outputs signals from the fifth general-purpose input / output terminal PA4, the sixth general-purpose input / output terminal PA5, and the seventh general-purpose input / output terminal PA6, respectively. The eighth general-purpose input / output terminal PA0 of the second microprocessor U4 outputs four low-level sub-enable signals. The first data input terminal A0, the second data input terminal A1, the third data input terminal A2, the fourth data input terminal A3, the fifth data input terminal A4, the sixth data input terminal A5, the seventh data input terminal A6, and the eighth data input terminal A7 of the transceiver U5 are connected to the sub-display drive signal. Each transceiver U5 buffers the sub-display drive signal according to the low-level enable signal.The buffered sub-display drive signals are output from the first data output terminal B0, the second data output terminal B1, the third data output terminal B2, the fourth data output terminal B3, the fifth data output terminal B4, the sixth data output terminal B5, the seventh data output terminal B6, and the eighth data output terminal B7 of the transceiver U5 to the display modules. Each display module then displays according to the buffered sub-display drive signals.

[0104] When the second button S2 is pressed, the first terminal of the second button S2 outputs a power-off button signal to the sixth general-purpose input / output terminal PB3 of the first microprocessor U1. The first microprocessor U1 outputs a control signal carrying power-off information according to the power-off button signal. The first wireless transceiver chip U2 outputs a wireless communication signal carrying power-off information through the first antenna ANT1 according to the control signal carrying power-off information. The second antenna ANT2 receives the wireless communication signal carrying power-off information and converts it into a communication signal carrying power-off information. The second wireless transceiver chip U3 outputs a wired communication signal carrying power-off information according to the communication signal carrying power-off information. The second microprocessor U4 outputs four high-level sub-enable signals according to the wired communication signal carrying power-off information. Each transceiver U5 disconnects the sub-display drive signal according to the high-level sub-enable signals, and the display circuit stops displaying.

[0105] When the third button S3 is pressed, the first terminal of the third button S3 outputs a delayed shutdown button signal to the seventh general-purpose input / output terminal PA15 of the first microprocessor U1. The first microprocessor U1 outputs a control signal carrying delayed shutdown information according to the delayed shutdown button signal. The first wireless transceiver chip U2 outputs a wireless communication signal carrying delayed shutdown information through the first antenna ANT1 according to the control signal carrying delayed shutdown information. The second antenna ANT2 receives the wireless communication signal carrying delayed shutdown information and converts the wireless communication signal into a communication signal carrying shutdown information. The second wireless transceiver chip U3 outputs a wired communication signal carrying delayed shutdown information according to the communication signal carrying shutdown information. The second microprocessor U4 outputs four high-level sub-enable signals after a preset time according to the wired communication signal carrying delayed shutdown information. Each transceiver U5 disconnects the sub-display drive signal according to the high-level sub-enable signals, and the display circuit stops displaying.

[0106] When the fourth button S4 is pressed, the first terminal of the fourth button S4 outputs a reset button signal to the external reset terminal NRST of the first microprocessor U1, and the first microprocessor U1 is reset, thereby resetting the display control circuit.

[0107] This application also provides an electronic device that includes the above-described display control circuit.

[0108] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0109] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A display control circuit, connected to a display circuit, characterized in that, include: A first wireless communication circuit is used to receive wireless communication signals and convert the wireless communication signals into wired communication signals; A first control circuit, connected to the first wireless communication circuit, is used to output an enable signal according to the wired communication signal; A signal buffer circuit, connected to the first control circuit and the display circuit, is used to receive the display driving signal and buffer the display driving signal according to the first level enable signal, or to disconnect the output of the display driving signal according to the second level enable signal. The display circuit is used to display according to the buffered display driving signal; The first level is the opposite of the second level.

2. The display control circuit as described in claim 1, characterized in that, The signal buffer circuit includes multiple signal buffer modules, the display circuit includes multiple display modules, and the multiple signal buffer modules are connected to the multiple display modules in a one-to-one correspondence; the enable signal includes multiple sub-enable signals, and the display drive signal includes multiple sub-display drive signals. The signal buffer module is connected to the first control circuit and the display module, and is used to buffer the sub-display drive signal according to the sub-enable signal of the first level, or to disconnect the output of the sub-display drive signal according to the sub-enable signal of the second level. The display module is used to display based on the buffered sub-display driving signal.

3. The display control circuit as described in claim 2, characterized in that, The signal buffer module includes a signal transceiver; The output enable terminal of the transceiver serves as the sub-enable signal input terminal of the signal buffer module and is connected to the first control circuit to input the sub-enable signal; the first, second, third, fourth, fifth, sixth, seventh, and eighth data input terminals of the transceiver together serve as the sub-display drive signal input terminals of the signal buffer module. The transceiver is used to input the sub-display drive signal; the first, second, third, fourth, fifth, sixth, seventh, and eighth data output terminals of the transceiver together serve as the buffered sub-display drive signal output terminals of the signal buffer module to output the buffered sub-display drive signal; the direction control terminal of the transceiver is connected to the first power supply.

4. The display control circuit as described in claim 1, characterized in that, Also includes: The second control circuit is used to output control signals; A second wireless communication circuit, connected to the second control circuit, is used to convert the control signal into a wireless communication signal.

5. The display control circuit as described in claim 4, characterized in that, Also includes: Function key circuit, used to output function key signals according to operation; The second control circuit is specifically used to output the control signal according to the function key signal.

6. The display control circuit as described in claim 4, characterized in that, The second control circuit includes a first microprocessor; The first general-purpose input / output (GPIO) terminal, the second general-purpose input / output (GPIO) terminal, the third general-purpose input / output (GPIO) terminal, and the fourth general-purpose input / output (GPIO) terminal of the first microprocessor are collectively used as the control signal output terminal of the second control circuit and are connected to the second wireless communication circuit to transmit the control signal.

7. The display control circuit as described in claim 4, characterized in that, The second wireless communication circuit includes a first wireless transceiver chip, a first antenna, a first inductor, a second inductor, a third inductor, a first capacitor, a second capacitor, and a third capacitor; The SPI chip select signal terminal, the SPI clock signal terminal, the SPI input signal terminal, and the SPI output signal terminal of the first wireless transceiver chip are collectively used as the control signal input terminal of the second wireless communication circuit and connected to the second control circuit to input the control signal. The first antenna terminal of the first wireless transceiver chip, the first terminal of the first inductor, and the first terminal of the second inductor are connected. The second antenna terminal of the first wireless transceiver chip, the second terminal of the first inductor, and the first terminal of the third inductor are connected. The second terminal of the third inductor is connected to the first terminal of the second capacitor. The second terminal of the second capacitor and the first terminal of the third capacitor are connected to the first antenna. The power supply terminal of the first wireless transceiver chip, the first terminal of the first capacitor, and the second terminal of the second inductor are connected. The second terminals of the first capacitor and the second terminals of the third capacitor are connected to the power ground.

8. The display control circuit as described in claim 1, characterized in that, The first wireless communication circuit includes a second wireless transceiver chip, a second antenna, a fourth inductor, a fifth inductor, a sixth inductor, a fourth capacitor, a fifth capacitor, and a sixth capacitor; The SPI chip select signal terminal, the SPI clock signal terminal, the SPI input signal terminal, and the SPI output signal terminal of the second wireless transceiver chip are collectively used as the wired communication signal output terminal of the first wireless communication circuit and connected to the first control circuit to output the wired communication signal. The first antenna terminal of the second wireless transceiver chip, the first terminal of the fourth inductor, and the first terminal of the fifth inductor are connected. The second antenna terminal of the second wireless transceiver chip, the second terminal of the fourth inductor, and the first terminal of the sixth inductor are connected. The second terminal of the sixth inductor is connected to the first terminal of the fifth capacitor. The second terminal of the fifth capacitor, the first terminal of the sixth capacitor, and the second antenna are connected. The power supply terminal of the second wireless transceiver chip, the first terminal of the fourth capacitor, and the second terminal of the fifth inductor are connected. The second terminals of the fourth capacitor and the second terminals of the sixth capacitor are connected to the power ground.

9. The display control circuit as described in claim 1, characterized in that, The first control circuit includes a second microprocessor, a first resistor, a second resistor, a third resistor, and a fourth resistor; The first general-purpose input / output terminal, the second general-purpose input / output terminal, the third general-purpose input / output terminal, and the fourth general-purpose input / output terminal of the second microprocessor are collectively used as the wired communication signal input terminal of the first control circuit and connected to the first wireless communication circuit to input the wired communication signal. The fifth general-purpose input / output terminal of the second microprocessor is connected to the first end of the first resistor, and the second end of the first resistor serves as the first sub-enable signal output terminal of the first control circuit, connected to the first signal buffer module to output the first sub-enable signal; the sixth general-purpose input / output terminal of the second microprocessor is connected to the first end of the second resistor, and the second end of the second resistor serves as the second sub-enable signal output terminal of the first control circuit, connected to the second signal buffer module to output the second sub-enable signal; the seventh general-purpose input / output terminal of the second microprocessor is connected to the first end of the third resistor, and the second end of the third resistor serves as the third sub-enable signal output terminal of the first control circuit, connected to the third signal buffer module to output the third sub-enable signal; the eighth general-purpose input / output terminal of the second microprocessor is connected to the first end of the fourth resistor, and the second end of the fourth resistor serves as the fourth sub-enable signal output terminal of the first control circuit, connected to the fourth signal buffer module to output the fourth sub-enable signal.

10. An electronic device, characterized in that, Includes the display control circuit as described in any one of claims 1 to 9.

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