Probability bit structure and magnetic tunnel junction structure

Abstract

The utility model relates to a probability bit structure and a magnetic tunnel junction structure. The probabilistic bit structure includes: a transistor; a magnetic tunnel junction (MTJ) operably connected with the transistor through a bottom electrode vertical interconnect channel (BEVA) to form a magnetoresistive random access memory (MRAM); and a heater including at least one conductive loop surrounding the MTJ or the BEVA. In one case, a probabilistic bit includes an MTJ structure including: an MTJ cell including an insulating layer disposed between a free layer and a fixed layer; a top electrode vertical interconnect channel (TEVA) connected to the MTJ cell; the BEVA is connected to the MTJ unit; and a heater disposed between a first intermetallic dielectric (IMD) region and the TEVA. The heater heats the MTJ structure when a voltage or a current is applied to the metallization layer first and second contacts, and the heater is shaped to one of a square, a rectangle, a circle, and an ellipse.

Description

Technical Field

[0001] The embodiments disclosed herein relate to probabilistic bit structures and magnetic tunnel junction structures. Background Technology

[0002] The following text covers the fields of quantum computing, probabilistic bits, quantum data storage, and related fields. Utility Model Content

[0003] Embodiments of this utility model relate to a probabilistic bit structure comprising: a transistor; a magnetic tunnel junction (MTJ) operatively connected to the transistor via a bottom electrode vertical interconnect channel (BEVA) to form a magnetoresistive random access memory (MRAM); and a heater comprising at least one conductive loop surrounding the MTJ or the BEVA.

[0004] Embodiments of this utility model relate to a method for forming a probabilistic bit structure. The method includes: forming a transistor region on a substrate; forming a first intermetallic dielectric (IMD) region on the substrate and the transistor region; forming a magnetic tunnel junction (MTJ) structure on the first IMD region. The MTJ structure includes: an MTJ cell comprising an insulating layer formed between a free layer and a fixed layer; a top electrode vertical interconnect channel (TEVA) formed and connected to the MTJ cell; a bottom electrode vertical interconnect channel (BEVA) formed and connected to the MTJ cell; a heater formed between the first IMD region and the TEVA; and a first metallization layer contact and a second metallization layer contact formed and connected to the heater, wherein the heater heats the MTJ structure when a voltage or current is applied to the first and second metallization layer contacts.

[0005] Embodiments of this utility model relate to a magnetic tunnel junction (MTJ) structure, comprising: an MTJ unit including an insulating layer disposed between a free layer and a fixed layer; a top electrode vertical interconnect channel (TEVA) connected to the MTJ unit; a bottom electrode vertical interconnect channel (BEVA) connected to the MTJ unit; and a heater including at least one conductive loop surrounding the MTJ unit or the BEVA. Attached Figure Description

[0006] A better understanding of aspects of this disclosure can be obtained from the following detailed description, which is taken in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various structures are not drawn to scale. In fact, the dimensions of the various structures may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1AExample embodiments of semiconductor structures suitable for use as probability bits and including heat-assisted magnetic tunnel junction (MTJ) structures according to this disclosure are illustrated. Figure 1B This graph illustrates experimental switching data for an MTJ structure operating at 150°C. The y-axis indicates the read current of the MTJ cell, and the x-axis indicates the hold time of the MTJ cell.

[0008] Figure 2A A side cross-sectional view illustrating a first example embodiment of a probability bit structure including a heat-assisted MTJ unit, wherein a heater surrounds a bottom electrode vertical interconnect channel (BEVA) of the MTJ unit; Figure 2B A side cross-sectional view illustrating a second example embodiment of a probabilistic bit structure including a heat-assisted MTJ unit, wherein a heater surrounds the MTJ unit; and Figure 2C A side cross-sectional view illustrating a third example embodiment of a probability bit structure including multiple heat-assisted MTJ units, wherein a heater surrounds multiple MTJ units BEVA.

[0009] Figures 3A to 3F A top view illustrating an example embodiment of a heater applicable to a probability bit-based MTJ according to the present disclosure is illustrated. Figure 3A Explanation of square heater, Figure 3B Explain the rectangular heater. Figure 3C Describe another rectangular heater, Figure 3D Explanation of circular heater, Figure 3E Describe the elliptical heater, and Figure 3F To illustrate another elliptical heater.

[0010] Figures 4A to 4E The steps for forming the probabilistic bit containing the thermally assisted MTJ structure are illustrated with a series of graphical side cross-sectional views.

[0011] Figure 5A Figure 5F illustrates the process through illustrative perspective and side cross-sectional views. Figure 4A The steps described herein produce detailed views of the probability bits generated by the MTJ heater. Figure 5B is a view along the plane X-X'( Figure 5A Cross-sectional view of ) Figure 5D It is along the plane Y-Y' ( Figure 5C Figure 5F is a cross-sectional view along the plane Y-Y'. Figure 5E Cross-sectional view of ). Detailed Implementation

[0012] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first member on or on a second member may include embodiments in which the first and second members are formed in direct contact, and may also include embodiments in which additional members may be formed between the first and second members such that the first and second members are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself define a relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, spatially relative terms (e.g., "below," "under," "down," "above," "up," and similar) may be used herein to describe the relationship of one element or component to another element(s), as illustrated in the accompanying drawings. In addition to covering the orientations depicted in the drawings, spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise) and the spatially relative descriptors used herein may be interpreted accordingly.

[0014] As used herein, the terms “surrounding” and “surround” or similar phrases refer to the periphery of a heater or heater layer as disclosed herein, wherein the heater shape has a continuous boundary or periphery that encloses or encloses a heating area, defined by continuous segments or individual segments. Additionally, as used herein, the terms “surrounding” and “surround” or similar phrases may include heater shapes that are not continuous boundaries or peripheries, and may include one or more discontinuities.

[0015] As used in this article, the term "heated zone" or similar phrase refers to a zone or area heated by a heater or heater layer.

[0016] The terms "ring" and "heating zone" refer to shapes that are not limited to circular rings but include, but are not limited to, other geometric shapes, including circles, squares, rectangles, ellipses, other polygons and other curved shapes.

[0017] The following description and the illustrated examples relate to heat-assisted probability bit structures and methods of forming them, including the use of magnetic tunnel junction (MTJ) cells to store programmable probability bits (p bits) with appropriate randomness. These probability bits can be used as data storage in quantum computing (QC) systems.

[0018] A magnetoresistive random access memory (MRAM) cell is formed by: a magnetic tunnel junction (MTJ), in which two ferromagnetic layers are separated by a thin insulating barrier; and a transistor operatively connected to the MTJ to drive the MRAM cell by applying a potential difference across the two ferromagnetic layers. When a potential difference is applied across the two ferromagnetic layers, current flows through the insulating barrier via a quantum mechanical tunnel. The resistance of the MTJ depends on the relative orientation of the magnetic elements in the two ferromagnetic layers. The resistance is lowest when magnetized parallel and highest when magnetized antiparallel. One of the relative orientations can be used to represent "1" and the other to represent "0". Generally, the magnetic orientation of one of the layers (pinned layer) remains fixed, while the magnetic orientation of the other layer (free layer) is set during write operations. The state of the MRAM cell can be interrogated by measuring the resistance of the junction. For the MRAM cell array to provide reliable data storage, a sufficiently large resistance difference must be achieved between the two possible states for each cell in the array.

[0019] Conventional computing systems employ deterministic bit structures, which typically store either "0" or "1" values. Increasing the computational efficiency of a conventional computing system may require increasing storage (e.g., quantization to bit count) and the resulting power consumption. The efficiency of a conventional computing system is limited by storage and power consumption.

[0020] Quantum computing (QC) significantly improves computational efficiency with lower energy and fewer bits. Quantum computing systems use semiconductor structures or devices to store p bits. These are referred to as probabilistic bit structures, or more simply probabilistic bits, as described herein. Typically, probabilistic bit structures operate at low temperatures (e.g., below 4K in some designs). This is problematic because it therefore requires, for example, the use of liquid helium as a coolant fluid to achieve temperatures below 4K to cool the p-bit storage array.

[0021] This disclosure and the various non-limiting illustrative embodiments described herein provide probabilistic bits comprising an MRAM structure and a thermally coupled electrically controllable heater. One or more MTJ cells of the MRAM structure are heated to an elevated operating temperature (i.e., an increase relative to room temperature, typically considered to be about 20°C to 22°C). The elevated temperature increases the thermal fluctuation rate between the "0" and "1" values ​​of the data stored in the MRAM. The probabilistic bit stores a superposition of "0" and "1" values, and thus the thermal fluctuation in the disclosed p bits effectively provides the desired superposition of "0" and "1" values, thereby enabling operation as a probabilistic bit. As appreciated herein, by increasing the operating temperature of the MRAM, the fluctuation rate can be advantageously and significantly increased, thereby providing p bits with a faster switching speed. In the experimental examples provided herein, millisecond fluctuations were observed at an operating temperature of 150°C. Since the thermal fluctuation rate typically scales approximately exponentially with increasing temperature, it is anticipated that increasing the operating temperature of the MRAM cell for the probabilistic bit to about 200°C should advantageously provide thermal fluctuations in the stored values ​​in the MRAM in the microsecond or nanosecond range. Furthermore, in the probabilistic bit as disclosed herein, heating is locally provided by (micro)heaters, which can be, for example, formed as annular heaters tightly surrounding the MTJ or its bottom electrode vertical interconnect channel (BEVA), thereby achieving efficient heating of the MTJ for the probabilistic bit only and thus advantageously low power consumption of the QC memory. Another advantage of the disclosed probabilistic bit structure is that it does not require cooling to, for example, a low operating temperature below 4K.

[0022] As discussed above, compared to conventional (i.e., von Neumann) computing architectures that have deterministic bits (i.e., storing "0" or "1" rather than a superposition of these values), using QC significantly improves computational efficiency with low energy and fewer bits (<100). Compared to QC, the conventional computing architecture faces bottlenecks of low efficiency and high energy consumption. However, probabilistic bit structures (i.e., probabilistic bit devices) are needed to realize quantum computing.

[0023] This disclosure and the embodiments described herein provide a probabilistic bit structure and a method of forming the same, comprising one or more MTJ cells heated to implement probabilistic bits for storing qubit values, the qubit values ​​being a superposition of "0" and "1" values ​​represented by rapid thermally induced fluctuations of MRAM between "0" and "1" values. Advantageously, the disclosed probabilistic bits can operate at ambient room temperature (e.g., 20°C to 22°C in some typical buildings), wherein localized heating of the MTJ device provides elevated MTJ temperatures, thus enabling low-power operation of the probabilistic bit array.

[0024] This document discloses a probabilistic bit (p bits) based on a random MTJ that operates at an ambient temperature of approximately 25°C or lower (e.g., ambient room temperature). The desired temperature of the random MTJ, with a microsecond to nanosecond hold, is generated in these p bits by an MTJ unit heater. The current / voltage supplied to the MTJ heater is derived from an external circuit system.

[0025] A key characteristic of the probability bits in a QC device is the superposition of "0" and "1" states. In the MTJ-based probability bit structure disclosed in this paper, a random MTJ with a short state holding time mimics this superposition over a specific time period. For example, if the MTJ state holding time is 1 nsec, then 1000 fluctuations ("0"→"1" and "1"→"0") occur within 2000 nsec. In other words, within this 2000 nsec time frame, from the observer's perspective, the "0" and "1" states are superimposed.

[0026] According to one aspect of this disclosure, the MTJ cell is heated in situ by an annular heater, thereby performing random switching at room temperature. The annular heater provides a substantially uniform heat distribution and thermally assists the MTJ cell to perform random switching at room temperature and can reduce the hold time to the microsecond to nanosecond level at elevated MTJ cell temperatures (e.g., 200°C or higher). Other ways to achieve reduced hold times in the microsecond to nanosecond range may include modifying the MTJ by reducing the MTJ free layer thickness or reducing the MTJ size.

[0027] refer to Figure 1B The graph illustrates experimental switching data for an MTJ structure operating at 150°C. The y-axis indicates the read current of the MTJ cell, and the x-axis indicates the hold time of the MTJ cell. As shown, the MTJ structure at 150°C performs switching at a rate in the millisecond range. As previously mentioned, since fluctuations scale approximately exponentially with increasing temperature, it is expected that increasing the operating temperature to approximately 200°C should advantageously provide for thermal fluctuations in the stored values ​​in the MRAM in the microsecond or nanosecond range.

[0028] refer to Figure 1A This describes an example embodiment of the probability bit structure 1, including the heat-assisted MTJ structure 500. For example... Figure 1AAs shown herein, the probability bit structure includes a MOSFET transistor located in a MOSFET transistor region 100, a first intermetallic dielectric (IMD) region 200 formed on the transistor region 100, and a second IMD region 300 formed on the first IMD region 200, the second IMD region 300 including an MTJ cell 502 and a heater arrangement 520. The MOSFETs of the MOSFET transistor region 100 are electrically connected to the MTJ cell 502 to form a magnetoresistive random access memory (MRAM). Although the transistor region 100 described herein includes an MRAM using planar MOSFETs to form probability bits, it should be understood that the probability bit structure is not limited to this particular semiconductor device, and other types of electronic devices can be used as drivers for the MRAM, such as bipolar junction transistors (BJTs), FinFETs, gate all-around (GAA) transistors, etc.

[0029] MOSFET transistor region 100 includes a MOSFET comprising a raised gate 102 region, a source 101 region, and a drain 103 region formed on a Si substrate 104 by known workflows such as photolithography, etching, deposition, p- and n-doping, and / or polishing. According to the illustrated example embodiment, the MOSFET gate 102 controls the MOSFET to turn the MTJ cell 502 on and off, for example, as a word line associated with MRAM cell read / write operations.

[0030] A first intermetallic dielectric (IMD) region 200 formed on transistor region 100 includes a transistor source path 202 with electrical contact source region 101 and a transistor drain path 201 with electrical contact drain region 103, as well as a top patterned metallization layer comprising exemplary conductive traces 206 and 205 formed by known photolithography, etching, deposition, and polishing processes. The patterned metallization layer provides contacts for the source and drain paths.

[0031] The exemplary second IMD region 300 includes a bottom path 301 and a bottom patterned metallization layer 305. It should be understood that in alternative embodiments, this layer 300 may be omitted, or conversely, this layer 300 may be repeated to provide multiple metallization layers with interconnecting paths.

[0032] The third IMD region 400 / 401 formed on the second IMD region 300 includes an MTJ unit 502, a heater 520 containing a conductive circuit, a top electrode vertical interconnect channel (TEVA) 503, a bottom electrode vertical interconnect channel (BEVA) 501 connected to the bottom patterned metallization layer 305, and a top patterned metallization layer 505. Although generally described as a third IMD region, this may be implemented as multiple IMD regions or fabricated using multiple IMD regions, depending on the situation.

[0033] The non-limiting illustrative MTJ cell 502 includes a free layer 513, an insulating or barrier layer 512, and a fixed layer 511. The MTJ cell 502 is connected to TEVA 503 and BEVA 501, which are respectively connected to a top metallization layer 505 and a bottom metallization layer 305. The bottom metallization layer 305 provides a connection between the MTJ cell 502 and the MOSFET drain 103 for operation control by an external control device (not shown). The magnetic moment of the MTJ cell 502 may be in-plane or vertical.

[0034] As will be further described herein, heater 520 includes an enclosure surrounding BEVA 501 (as shown in the image). Figure 1A (as shown in the image) or surrounding the MTJ 502 (for example, see...) Figure 2B The conductive circuit of the alternative embodiment) and the MTJ heater 520 is displaced from BEVA 501 (or from MTJ if arranged surrounding MTJ) by a distance and has a substantially continuous shape surrounding BEVA 501 (or alternatively, surrounding MTJ). The shape of the heater 520 is not limited to a particular geometry, but is a continuous or substantially continuous shape, such as, but not limited to, a circle, square, rectangle, ellipse, etc. When voltage or current is applied to the contacts of the heater 520 by an external device (not shown) Figure 1A When (not shown in the image), the material of heater 520 radiates heat uniformly toward BEVA 501 and raises the temperature of MTJ unit 502, thereby providing a heat-assisted MTJ structure.

[0035] According to an example embodiment of the disclosed probability bit structure, heater 520 may surround the illustrated BEVA 501, surround multiple BEVAs configured with multiple MTJ units, surround MTJ unit 502, or surround multiple MTJ units configured with multiple MTJ units. In some non-limiting illustrative embodiments, the free layer material of MTJ unit 502 is CoFeB, CoFe, FeB, CoB, NiFe, or NiFeMo; the insulator or barrier layer material is MgO or Al2O3; and the fixed layer material is multilayered as appropriate and includes Co and Pt, Fe and Pt, Co and Pd, or Fe and Pd in ​​some non-limiting illustrative embodiments. In some non-limiting illustrative embodiments, the heater material is W, Ti, Ta, Mo, WN, TiN, TaN, MoN, or graphene. In some non-limiting illustrative embodiments, the materials of BEVA 501 and TEVA 503 are W, Ti, Ta, Mo, TiN, TaN, MoN, or Cu.

[0036] To control heater 520, a switching device (not shown, such as an NMOS or other type of transistor) can be used to selectively turn heater 520 on and off. In addition to the switching device, peripheral circuitry (not shown) may be provided to control the voltage / current applied to heater 520. In the various considered embodiments, heater 520 may be controlled individually, or more than one heater 520 associated with multiple MTJ units may be controlled to turn on and off simultaneously.

[0037] refer to Figures 2A to 2C The diagram shows a cross-sectional view illustrating an example embodiment of a probabilistic bit structure including a heat-assisted MTJ unit 502 according to various non-limiting illustrative embodiments of the present disclosure. Figure 2A This is a first example embodiment of a probabilistic bit structure including a heat-assisted MTJ unit 502, wherein a heater 520 surrounds the MTJ unit BEVA 501. Figure 2B This describes a second example embodiment of the probabilistic bit structure including a heat-assisted MTJ unit 502, wherein a heater 520 surrounds the MTJ unit 502, and Figure 2C The description includes a third example embodiment of a probability bit structure comprising multiple thermally assisted MTJ units 502 and 602, wherein a heater 520 surrounds multiple MTJ units BEVA 501 and 601.

[0038] like Figure 2AAs shown, this probabilistic embodiment includes a thermally assisted MTJ unit 502, wherein a heater 520 surrounds an MTJ unit BEVA 501. The MTJ structure includes an IMD region 401, which includes the MTJ unit 502, the heater 520, multiple TEVAs 503, 531, 532 and 533, BEVA 501, bottom patterned metallization layers 305 and 306, and top patterned metallization layers 505, 525, 526 and 527. Additionally, the MTJ structure includes an insulating layer 527 sandwiched between the MTJ unit 502 and the heater 520, and another insulating layer 528 encapsulating the MTJ unit 502.

[0039] MTJ cell 502 includes a free layer 513, an insulating or barrier layer 512, and a fixed layer 511. MTJ cell 502 is connected to TEVA 503 and BEVA 501, which are respectively connected to a top metallization layer 505 and a bottom metallization layer 305. According to an exemplary embodiment, bottom metallization layer 305 provides a connection between MTJ cell 502 and MOSFET drain 103 for operation control by an external control device (not shown). The MOSFET is electrically connected to MTJ cell 502 to form a magnetoresistive random access memory (MRAM), as previously referenced. Figure 1A As described. The magnetic moment of MTJ unit 502 can be in-plane or perpendicular.

[0040] Additional TEVAs 531 and 532 provide a connection between heater 520 and an external control device to turn heater 520 on and off. Further additional TEVA 533 connects top metallization 527 to bottom metallization 306 to facilitate pass-through connections to integrated control devices or other structures, such as to the source 101 of the MOSFET used to control MTJ unit 502.

[0041] As shown, heater 520 is displaced or offset from BEVA 501 by a distance distBEVA. According to the example non-limiting illustrative embodiment, the distance distBEVA is greater than 80 nm to ensure sufficient distance to avoid electrical shunting between heater 520 and BEVA 501.

[0042] According to the disclosed probabilistic site structure, the MTJ unit free layer 513 material is CoFeB, CoFe, FeB, CoB, NiFe, or NiFeMo in some non-limiting illustrative embodiments; the insulator or barrier layer material is MgO or Al2O3 in some non-limiting illustrative embodiments; and the fixing layer material is multilayered as appropriate and includes Co and Pt, Fe and Pt, Co and Pd, or Fe and Pd in ​​some non-limiting illustrative embodiments. In some non-limiting illustrative embodiments, the heater material is W, Ti, Ta, Mo, WN, TiN, TaN, MoN, or graphene. In some non-limiting illustrative embodiments, the BEVA and TEVA materials are W, Ti, Ta, Mo, TiN, TaN, MoN, or Cu.

[0043] According to the disclosed probabilistic bit structure, the thickness of the MTJ unit free layer 513 material is between about 2 nm and about 5 nm in some non-limiting illustrative embodiments, the thickness of the insulator or barrier layer 512 material is between about 1 nm and about 2 nm in some non-limiting illustrative embodiments, and the thickness of the fixing layer material is between about 5 nm and about 15 nm in some non-limiting illustrative embodiments.

[0044] According to an example embodiment of the disclosed probabilistic bit structure, the thickness of the MTJ heater 520 is between approximately 50 nm and approximately 300 nm, and the dimensions (length / width) of the heater 520 are between approximately 50 nm and approximately 300 nm in some non-limiting illustrative embodiments. The heater current required to operate the heater 520 to achieve the desired MTJ cell temperature depends on the dimensions and material of the heater 520. For switching speeds in the microsecond or nanosecond range, in some non-limiting illustrative embodiments, the target MTJ cell temperature is 200°C, and the heater current can be at least >500 μA, although these are also possible variations or different illustrative values ​​depending solely on the configuration of the heater 520.

[0045] like Figure 2B As shown, this probabilistic embodiment includes a thermally assisted MTJ unit 502, with a heater 520 surrounding the MTJ unit 502. The MTJ structure includes an IMD region 401, which includes the MTJ unit 502, the heater 520, a plurality of TEVAs 503, 531, 532 and 533, a BEVA 501, bottom patterned metallization layers 305 and 306, and top patterned metallization layers 505, 525, 526 and 527. Additionally, the MTJ structure includes an insulating layer 527 sandwiched between the MTJ unit 502 and the heater 520, and another insulating layer 528 encapsulating the MTJ unit 502.

[0046] MTJ cell 502 includes a free layer 513, an insulating or barrier layer 512, and a fixed layer 511. MTJ cell 502 is connected to TEVA 503 and BEVA 501, which are respectively connected to a top metallization layer 505 and a bottom metallization layer 305. According to an example embodiment, the bottom metallization layer 305 provides a connection between MTJ cell 502 and MOSFET drain 103 for operation control by an external control device (not shown). The MOSFET electrically connected to MTJ cell 502 forms an MRAM, as previously referenced. Figure 1A As described. The magnetic moment of MTJ unit 502 can be in-plane or perpendicular.

[0047] Additional TEVAs 531 and 532 provide a connection between heater 520 and an external control device to turn the heater on and off. Further additional TEVA 533 connects the top metallization layer 527 to the bottom metallization layer 306 to facilitate pass-through connections to integrated control devices or other structures, such as to the source 101 of the MOSFET used to control the MTJ unit 502.

[0048] In this embodiment, such as Figure 2B As shown, heater 520 is displaced or offset from MTJ unit 502 by a distance distMTJ. According to the example non-limiting illustrative embodiment, the distance distMTJ is greater than 50 nm to ensure sufficient distance to avoid electrical shunting between heater 520 and MTJ unit 502.

[0049] According to the disclosed probabilistic site structure examples, the free layer material of the MTJ unit is CoFeB, CoFe, FeB, CoB, NiFe, or NiFeMo in some non-limiting illustrative embodiments; the insulating or barrier layer material is MgO or Al2O3 in some non-limiting illustrative embodiments; and the fixed layer material is multilayered as appropriate and includes Co and Pt, Fe and Pt, Co and Pd, or Fe and Pd in ​​some non-limiting illustrative embodiments. The heater material is W, Ti, Ta, Mo, WN, TiN, TaN, MoN, or graphene. The BEVA and TEVA materials are W, Ti, Ta, Mo, TiN, TaN, MoN, or Cu.

[0050] According to the disclosed probabilistic bit structure, the thickness of the MTJ unit free layer 513 material is between about 2 nm and about 5 nm in some non-limiting illustrative embodiments, the thickness of the insulator or barrier layer 527 material is between about 1 nm and about 2 nm in some non-limiting illustrative embodiments, and the thickness of the fixed layer 611 material is between about 5 nm and about 15 nm in some non-limiting illustrative embodiments.

[0051] According to exemplary embodiments of the disclosed probabilistic bit structure, the thickness of the MTJ heater 520 is between about 50 nm and about 300 nm in some non-limiting illustrative embodiments, and the dimensions (length / width) of the heater 520 are between about 50 nm and about 300 nm in some non-limiting illustrative embodiments. The heater current for operating the heater 520 to achieve the desired MTJ cell temperature depends on the dimensions and material of the heater 520. For switching speeds in the microsecond or nanosecond range, in some non-limiting illustrative embodiments, the target MTJ cell temperature is 200°C, and the heater current can be at least >500 μA, although these are merely illustrative values ​​that may vary depending on the configuration of the heater 520.

[0052] like Figure 2C As shown, this probabilistic embodiment includes multiple thermally assisted MTJ units 502 and 602 and corresponding BEVAs 501 and 601, wherein a heater 520 surrounds the multiple BEVAs 501 and 601 associated with the MTJ units. (In another variant embodiment, with...) Figure 2B Similar to other embodiments, the heater may surround multiple MTJ units.

[0053] Figure 2C The probability bit structure includes an IMD region 401, which includes a first MTJ unit 502, a second MTJ unit 602, a heater 520, multiple TEVAs 503, 531, 532 and 533, first and second BEVAs 501 and 601, bottom patterned metallization layers 305, 306 and 307, and top patterned metallization layers 505, 525, 526, 527 and 605. Additionally, the MTJ structure includes an insulating layer 527 sandwiched between the first MTJ unit 502 and the second MTJ unit 602, a heater 520, and another insulating layer 528 encapsulating the MTJ units.

[0054] Each of MTJ cells 502 and 602 includes free layers 513, 613, insulating or barrier layers 512, 612, and fixed layers 511, 611. Each of the MTJ cells is connected to TEVA 503, 603 and BEVA 501, 601, which are respectively connected to top metallization layers 505, 605 and bottom metallization layers 305, 307. According to an exemplary embodiment, bottom metallization layers 305, 307 provide each of the first and second MTJ cells 502, 602 with a connection to a common or individual MOSFET drain for operation control by an external control device (not shown) to form one or more MRAM devices with probabilistic bits (although other types of transistors or other types of drive electronics configurations for forming MRAM are also contemplated). The magnetic moment of the MTJ cell may be in-plane or may be vertical.

[0055] Additional TEVAs 531 and 532 provide a connection between heater 520 and an external control device to turn heater 520 on and off. Further additional TEVA 533 connects top metallization 527 to bottom metallization 306 to facilitate pass-through connections to integrated control devices or other structures, such as to the source 101 of a MOSFET used to control the MTJ cell.

[0056] like Figure 2C As shown, heater 520 is displaced or offset by a distance distBEVA from each of BEVA 501 and 601. According to the example non-limiting illustrative embodiment, the distance distBEVA is greater than 80 nm to ensure sufficient distance to avoid electrical shunting between heater 520 and BEVA 501 and 601.

[0057] According to the disclosed probabilistic site structure, the MTJ unit free layer 513 material is CoFeB, CoFe, FeB, CoB, NiFe, or NiFeMo in some non-limiting illustrative embodiments; the insulator or barrier layer material is MgO or Al2O3 in some non-limiting illustrative embodiments; and the fixing layer material is multilayered as appropriate and includes Co and Pt, Fe and Pt, Co and Pd, or Fe and Pd in ​​some non-limiting illustrative embodiments. In some non-limiting illustrative embodiments, the heater material is W, Ti, Ta, Mo, WN, TiN, TaN, MoN, or graphene. In some non-limiting illustrative embodiments, the BEVA and TEVA materials are W, Ti, Ta, Mo, TiN, TaN, MoN, or Cu.

[0058] According to the disclosed probabilistic bit structure, the thickness of the free layer 513, 613 material of the MTJ unit is between about 2 nm and about 5 nm in some non-limiting illustrative embodiments, the thickness of the insulator or barrier layer 512, 612 material is between about 1 nm and about 2 nm in some non-limiting illustrative embodiments, and the thickness of the fixed layer 511, 611 material is between about 5 nm and about 15 nm in some non-limiting illustrative embodiments.

[0059] Figures 3A to 3F A top view illustrating an example embodiment of the heater according to this disclosure.

[0060] As previously mentioned, heater 520 can have various layouts. Figures 3A to 3F Some non-limiting illustrative embodiments of heater 520 are shown in an isolated top view. (Referring to the reference...) Figures 3A to 3F In the following description of the embodiments, all heater dimensions should be understood as non-limiting illustrative examples. Figure 3A The square heater 520 has a thickness of 50nm to 300nm, a width Hwidth of 150nm to 300nm, and a length Hlength of 150nm to 300nm.

[0061] Figure 3B The rectangular heater 520 has a thickness of 50nm to 300nm, a width Hwidth of 150nm to 300nm, and a length Hlength of 300nm to 500nm.

[0062] Figure 3C Another rectangular heater 520 is described. The thickness of the heater 520 segment is 50nm to 300nm, the width Hwidth is 300nm to 500nm, and the length Hlength is 150nm to 300nm.

[0063] Figure 3D The circular heater 520 has a continuous section with a thickness of 50 nm to 300 nm and a diameter Hdiameter of 150 nm to 300 nm.

[0064] Figure 3E The elliptical heater 520 has a continuous section thickness of 50nm to 300nm, a major axis length Hlength of 300nm to 500nm, and a minor axis length Hwidth of 150nm to 300nm.

[0065] Figure 3FAnother elliptical heater 520 is described. The thickness of the continuous segment of heater 520 is 50nm to 300nm, the major axis length Hwidth = 300nm to 500nm, and the minor axis length Hlength = 150nm to 300nm.

[0066] Figures 3A to 3F The illustrative heater 520 embodiment includes a single conductive loop surrounding the BEVA or MTJ; however, it is considered that the heater includes two or more conductive loops surrounding the BEVA or MTJ, wherein multiple loops provide additional thermal heating.

[0067] Figures 4A to 4E The various steps for forming a probability bit structure according to this disclosure are illustrated by a series of graphical side cross-sectional views, the probability bit structure comprising a heat-assisted MTJ structure including a heater surrounding an MTJ unit BEVA (Example 1). In the... Figures 4A to 4E In the following description of the manufacturing process depicted herein, all heater dimensions and materials should be understood as non-limiting illustrative examples. Figure 4A The device structure is shown after processing steps including etching SiO2 intermetallic dielectric (IMD) layers / regions, depositing heater material, and performing chemical mechanical polishing (CMP); Figure 4B Displayed in including deposited SiN x The device structure after photolithography of the insulating layer, etching of the insulating layer and SiO2 intermetallic dielectric (IMD) layer / region, deposition of TaN / TiN BEVA and further processing steps of CMP; Figure 4C Demonstrating SiN incorporating MTJ unit deposition processes, MTJ unit etching, and MTJ unit deposition and encapsulation. x The device structure following further processing steps of the insulating layer; Figure 4D The device structure is shown after the deposition of the encapsulated MTJ unit and the previously deposited insulating layer of SiO2 intermetallic dielectric (IMD) layer / region, and the subsequent CMP processing steps; and Figure 4E The device structure is shown after further processing steps, including etching and deposition to form multiple TEVAs (similar to the formation of BEVAs), deposition of a top metallization layer for connecting the MTJ structure to a voltage / current source to operate the heater, and for read / write operations associated with the MTJ cell. This is described in further detail below. Figures 4A to 4E The aforementioned non-limiting illustrative manufacturing process is described in the text.

[0068] It should be understood that the MTJ structure is formed on an interconnect structure that has previously been deposited on another semiconductor structure (e.g., a transistor, i.e., a MOSFET), which forms the MRAM together with the MTJ after the MTJ structure is formed on the transistor region of the other semiconductor structure, as referenced. Figures 4A to 4E Describe it. For example, using known processes on a Si substrate (104, see...) Figure 1A Formed on the surface as follows Figure 1A The MOSFET shown in the figure. The substrate 104 may be, for example, a bulk substrate (e.g., a bulk silicon substrate) or a silicon-on-insulator (SOI) substrate. One or more shallow trench isolation (STI) regions may include dielectric-filled trenches within the substrate 104.

[0069] Word line transistors may be disposed between STI regions. A word line transistor includes a word line gate electrode and word line source / drain regions, and may include other regions, such as a word line gate dielectric, word line sidewall spacers, etc. The source / drain regions are disposed within the substrate between the word line gate electrodes and are doped to have a first conductivity type, which is opposite to a second conductivity type of the channel region beneath the gate dielectric. The word line gate electrode may be, for example, doped polysilicon or a metal, such as aluminum, copper, or a combination thereof. The word line gate dielectric may be, for example, an oxide (e.g., silicon dioxide) or a high-k dielectric material. For example, the word line sidewall spacers may be made of silicon nitride (e.g., Si3N4).

[0070] Interconnect structures are disposed on a substrate and couple devices (e.g., transistors and MTJ structures) to each other. The interconnect structures may include multiple IMD layers and multiple metallization layers stacked alternately on top of each other. The IMD layers may be made of, for example, a low-k dielectric (e.g., undoped silicate glass), an oxide (e.g., silicon dioxide), or an extremely low-k dielectric layer. The metallization layers include metal lines formed within trenches and may be made of metal (e.g., copper or aluminum). Connections to… Figure 4A The metallized contacts shown in the MTJ structure extend from the bottom metallized layer of the IMD to the source / drain region; and pathways can extend between the metallized layers. The contacts and pathways extend through a dielectric protective layer (which may be made of a dielectric material and can act as an etch stop layer during manufacturing). The dielectric protective layer may be made of an extremely low-k dielectric material (e.g., SiC, for example). The contacts and pathways may be made of a metal (e.g., copper or tungsten, for example).

[0071] MRAM cells, including MTJ cells as disclosed herein, are configured to store corresponding data states and are arranged within an interconnect structure between adjacent metal layers, such as... Figures 4A to 4EAs shown in the diagram. As will be further described below, the MRAM cell includes a bottom electrode and a top electrode made of a conductive material. The MRAM cell includes an MTJ between its top electrode and bottom electrode. The MRAM cell may also include MRAM sidewall spacers.

[0072] In summary, the above paragraphs describe the formation of transistors (e.g., MOSFETs) on Si substrates, further including the formation of... Figure 4A The interconnect structure of contact connections shown in the MTJ structure is illustrated. Furthermore, an MTJ SiO2 IMD is formed on top of this previously formed structure. Figure 4A The previously formed structure also includes Figure 4A The electrometallized layer contacts shown in the image.

[0073] refer to Figure 4A This paper demonstrates the steps for forming an MTJ structure by etching a SiO2 intermetallic dielectric (IMD) layer / region 400 and depositing heater material 520, as previously described herein. Additionally, after depositing heater material 520, the process performs chemical mechanical polishing (CMP) on the top surface. Suitable heater materials include W, Ti, Ta, Mo, WN, TiN, TaN, MoN, or graphene.

[0074] refer to Figure 4B Demonstrating deposited SiN x The steps include: etching insulating layer 527 and SiO2 intermetallic dielectric (IMD) layer / region 400; depositing TaN / TiN BEVA 501; and performing chemical mechanical polishing on the top surface insulating layer 527. Other suitable BEVA materials include W, Ti, Ta, Mo, TiN, TaN, MoN, or Cu.

[0075] refer to Figure 4C This demonstrates the SiN deposition process of MTJ unit 502, the etching of MTJ unit 502, and the deposition and encapsulation of MTJ unit 502. x Step 528 for insulating layer. The MTJ cell formation process includes forming an MTJ stack, including depositing multiple layers to produce a fixed layer 511, an insulator 512, and a free layer 513. These layers can be formed using photoresist masks, other known photolithography, deposition, and etching processes. Suitable materials for the MTJ cell free layer 513 include CoFeB, CoFe, FeB, CoB, NiFe, or NiFeMo; suitable materials for the insulator or barrier layer 512 include MgO or Al2O3; and suitable materials for the fixed multilayer material 511 include Co and Pt, Fe and Pt, Co and Pd, or Fe and Pd.

[0076] The reference is to the SiO2 intermetallic dielectric (IMD) layer / region 401 encapsulating the MTJ cell 502 and the previously deposited insulating layer 528, and to the CMP performed on the top surface of the deposited IMD 401. Figure 4D .

[0077] refer to Figure 4E The process demonstrates etching and deposition to form multiple TEVAs 503, 531, 532, and 533 (similar to the formation of BEVA501) and deposition of top metallization layers 505, 525, 526, and 527 for connecting the MTJ structure to a voltage / current source to operate the heater 520 and for read / write operations associated with the MTJ cell 502. Suitable TEVA materials include SiO2, W, Ti, Ta, Mo, TiN, TaN, MoN, or Cu.

[0078] Figure 5A To Figure 5F is through Figure 4A Various other detailed views of the MTJ heater 520 produced by the steps described herein. Figure 5B is a view along... Figure 5A The diagram shows a cross-sectional view of heater 520 taken from plane X-X'. Figure 5D It is along Figure 5C The cross-sectional view of heater 520 taken along the plane Y-Y' is shown in Figure 5F. Figure 5E The diagram shows a cross-sectional view of heater 520 taken from the plane Y-Y'.

[0079] Some further embodiments are described below.

[0080] In a non-limiting illustrative embodiment, a probabilistic bit structure includes: a transistor; a magnetic tunnel junction (MTJ) operatively connected to the transistor via a bottom electrode vertical interconnect channel (BEVA) to form a magnetoresistive random access memory (MRAM); and a heater including at least one conductive loop surrounding the MTJ or the BEVA.

[0081] In a non-limiting illustrative embodiment, a method for forming a probabilistic bit structure includes: forming a transistor region on a substrate; forming a first intermetallic dielectric (IMD) region on the substrate and the transistor region; forming a magnetic tunnel junction (MTJ) structure on the first IMD region, the MTJ structure including: an MTJ cell including an insulating layer formed between a free layer and a fixed layer; a top electrode vertical interconnect channel (TEVA) formed and connected to the MTJ cell; a bottom electrode vertical interconnect channel (BEVA) formed and connected to the MTJ cell; a heater formed between the first IMD region and the TEVA; and a first metallization layer contact and a second metallization layer contact formed and connected to the heater, wherein the heater heats the MTJ structure when a voltage or current is applied to the first and second metallization layer contacts.

[0082] In a non-limiting illustrative embodiment, a magnetic tunnel junction (MTJ) structure includes: an MTJ cell including an insulating layer disposed between a free layer and a fixed layer; a top electrode vertical interconnect channel (TEVA) connected to the MTJ cell; a bottom electrode vertical interconnect channel (BEVA) connected to the MTJ cell; and a heater including at least one conductive loop surrounding the MTJ cell or the BEVA.

[0083] The foregoing summary of the features of several embodiments enables those skilled in the art to better understand aspects of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purposes and / or benefits as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0084] Symbol Explanation

[0085] 1: Probability bit structure

[0086] 100: MOSFET transistor region

[0087] 101: Source Region / Source

[0088] 102: Raised gate region

[0089] 103: Transistor drain region / MOSFET drain

[0090] 104: Si substrate

[0091] 200: First Intermetallic Dielectric (IMD) Region

[0092] 201: Transistor drain path

[0093] 202: Transistor source path

[0094] 205: Conductive trace

[0095] 206: Conductive traces

[0096] 300: Second IMD Zone

[0097] 301: Bottom Path

[0098] 305: Bottom patterned metallization layer

[0099] 306: Bottom patterned metallization layer

[0100] 307: Bottom Patterned Metallization Layer

[0101] 400: Third IMD region / SiO2 intermetallic dielectric (IMD) layer / region

[0102] 401: Third IMD region / SiO2 intermetallic dielectric (IMD) layer / region

[0103] 500: Heat-Assisted Magnetic Tunnel Junction (MTJ) Structure

[0104] 501: Bottom Electrode Vertical Interconnect Channel (BEVA) / MTJ Unit BEVA / First BEVA or TaN / TiN BEVA

[0105] 502: Heat-assisted MTJ unit / First MTJ unit

[0106] 503: Top Electrode Vertical Interconnect Channel (TEVA)

[0107] 505: Top patterned metallization layer

[0108] 511: Fixing layer / Fixing multiple layers of materials

[0109] 512: Insulator or barrier layer

[0110] 513: Free Layer

[0111] 520: Heater Arrangement / Heater / MTJ Heater

[0112] 525: Top patterned metallization layer

[0113] 526: Top patterned metallization layer

[0114] 527: Top patterned metallization layer / insulating layer

[0115] 528: Insulating layer / SiN xInsulation layer

[0116] 531:TEVA

[0117] 532:TEVA

[0118] 533:TEVA

[0119] 601:MTJ Unit BEVA / Second BEVA

[0120] 602: Heat-assisted MTJ unit / Second MTJ unit

[0121] 603:TEVA

[0122] 605: Top patterned metallization layer

[0123] 611: Fixed layer

[0124] 612: Insulator or barrier layer

[0125] 613: Free Layer

[0126] distBEVA: Distance

[0127] distMTJ: Distance

[0128] Hdiameter: diameter

[0129] Hlength: Length / Major axis length / Minor axis length

[0130] Hwidth: Width / Short axis length / Long axis length.

Claims

1. A probability bit structure, characterized in that... It includes: transistor; A magnetic tunnel junction (MTJ) operatively connected to the transistor via a bottom electrode vertical interconnect channel (BEVA) to form a magnetoresistive random access memory (MRAM); and A heater comprising at least one conductive loop surrounding the MTJ or the BEVA.

2. The probability bit structure according to claim 1, characterized in that... The MTJ includes an insulating layer disposed between the free layer and the fixed layer.

3. The probability bit structure according to claim 2, characterized in that... It further includes: Substrate; A transistor region disposed on the substrate and including the transistor; A first intermetallic dielectric (IMD) region is disposed on the substrate and the transistor region; An MTJ structure, disposed on the first IMD region, includes the MTJ, a top electrode vertical interconnect channel (TEVA) connected to the MTJ, a BEVA connected to the MTJ, and a heater electrically connected to a first electrical contact and a second electrical contact. When voltage or current is applied to the first and second electrical contacts, the heater heats the... MTJ structure.

4. The probability bit structure according to claim 3, characterized in that... The at least one conductive circuit of the heater surrounds the BEVA.

5. The probability bit structure according to claim 2, characterized in that... The MTJ has an in-plane magnetic moment or a vertical moment.

6. The probability bit structure according to claim 1, characterized in that... The MTJ includes a first MTJ and a second MTJ. MTJ, and the at least one conductive loop of the heater surrounds both the first MTJ and the second MTJ.

7. The probability bit structure according to claim 1, characterized in that... The MTJ includes a first MTJ and a second MTJ. MTJ, wherein the BEVA includes a first BEVA connected to the first MTJ and a second BEVA connected to the second MTJ, and the at least one conductive loop of the heater surrounds both the first BEVA and the second BEVA.

8. A magnetic tunnel junction structure, characterized in that... It includes: MTJ unit, which includes an insulating layer disposed between a free layer and a fixed layer; The top electrode vertical interconnect channel TEVA is connected to the MTJ unit; The bottom electrode vertical interconnect channel BEVA is connected to the MTJ unit; and A heater comprising at least one conductive loop surrounding the MTJ unit or the BEVA.

9. The magnetic tunnel junction structure according to claim 8, characterized in that... The heater includes at least one conductive loop surrounding the MTJ unit.

10. The magnetic tunnel junction structure according to claim 8, characterized in that... The heater contains at least one conductive loop surrounding the BEVA.

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