Server and server system

Abstract

The utility model discloses a server and a server system, and relates to the technical field of server architecture.The server comprises a case, n mainboards, at least one second signal connector and a cable, each mainboard comprises at least one processor and at least one first signal connector connected with the processor, and n is a positive integer larger than or equal to 2; the second signal connector is used for being connected with a preset device, the preset device comprises at least one of a network interface card, a data processor, a first expansion board and a computing fast link device, and the second signal connector is connected with one of the first signal connectors of at least two mainboards in the n mainboards through a cable. The second signal connector is connected with the first signal connectors of the at least two mainboards through cables, so that cross-processor communication between the single second signal connector and more than two processors is realized, the communication overhead of the processors is reduced, the technical problem of relatively long communication delay of the processors in related technologies can be solved, and the communication efficiency of the processors is improved. And the communication delay of the processor is reduced.

Description

TECHNICAL FIELD

[0001] The utility model relates to server architecture technical field more specifically, relate to a kind of server and server system. BACKGROUND

[0002] In related art, for network interface card, data processor or expansion card and other equipment, it is usually directly connected on a single CPU (Central Processing Unit, central processor) by x16 signal, and communication is carried out by single CPU, and the communication overhead of CPU is large, and there is large communication delay.

[0003] In addition, for the double Multihost network card (multi-host network card) in related art, it is interconnected with multiple CPUs on a single mainboard, and with the design of extreme single-path computing performance, the width size limit of 19-inch chassis in related art makes it impossible to design multiple CPUs on a single mainboard in the chassis, so the interconnection of network interface card, data processor or expansion card and other equipment with multiple CPUs cannot be realized.

[0004] Therefore, how to realize the interconnection of network interface card, data processor or expansion card and other equipment to multiple CPUs and reduce the communication delay of CPU is a problem to be solved by the technical personnel in the field. UTILITY MODEL CONTENT

[0005] The present application provides a kind of server, to at least solve the interconnection of network interface card, data processor or expansion card and other equipment to multiple processors in related art, to reduce the problem of long communication delay of processor.

[0006] The present application provides a kind of server, comprising:

[0007] Chassis;

[0008] n mainboards, all mainboards are stacked in the chassis along the height direction of the chassis, each mainboard includes at least one processor and at least one first signal connector, the first signal connector is connected with the processor, wherein n is a positive integer greater than or equal to 2;

[0009] At least one second signal connector is provided in the chassis for connecting a predetermined device, the predetermined device includes at least one of a network interface card, a data processor, a first expansion board and a computing fast link device;The second signal connector is connected with one of the first signal connectors of at least two mainboards in the n mainboards through a cable.

[0010] In one aspect, the cable comprises:

[0011] The first cable is provided with a third signal connector and a fourth signal connector at two ends respectively, the third signal connector is connected with the first signal connector, and the fourth signal connector is arranged at the edge of the mainboard.

[0012] The second cable is connected with a fifth signal connector at one end and connected with the second signal connector at the other end, the fifth signal connector is connected with the fourth signal connector, and the second signal connector is connected with at least two second cables corresponding to the first signal connector of the mainboard.

[0013] In another aspect, the fifth signal connector corresponding to the first signal connector of a single mainboard is connected with N second cables, N is a positive integer greater than or equal to 2.

[0014] The second signal connector is connected with at least one second cable corresponding to the first signal connector of the mainboard.

[0015] In another aspect, the first signal connector and the fifth signal connector are xL signal connectors, the second signal connector is an xP signal connector, the number of the second cables connected with a single second signal connector is K, and:

[0016] ;

[0017] Wherein, L, P and K are positive integers.

[0018] In another aspect, the first signal connector, the third signal connector, the fourth signal connector, the fifth signal connector and the second signal connector are blind insertion quick release connectors; the second signal connector is used for hot plug connection with the preset device.

[0019] In another aspect, it further comprises:

[0020] The cable quick release module support is detachably arranged in the case, and the fifth signal connector and the second signal connector are arranged in the corresponding cable quick release module support.

[0021] In another aspect, the fourth signal connector is fixedly arranged at the edge of the mainboard through a fixing member.

[0022] In another aspect, one of the fourth signal connector and the fixing member is provided with a protruding portion, and the other is provided with a groove matched with the protruding portion; the protruding portion and the groove have a preset gap therebetween.

[0023] In another aspect, the fixing member comprises:

[0024] A crossbeam is arranged above the fourth signal connector and is used to press the fourth signal connector.

[0025] At least two vertical beams are connected with the crossbeam perpendicularly, and a space for accommodating the fourth signal connector is formed between any two adjacent vertical beams.

[0026] A fixed folding edge is arranged at the bottom of the vertical beam and is provided with a mounting part for fixing the mainboard.

[0027] On the other hand, the second signal connector is used to connect a second expansion board, and the second expansion board is used to connect the data processor; and / or,

[0028] The first expansion board is provided with at least two signal slots.

[0029] On the other hand, each mainboard includes at least two first signal connectors, and the server further includes an eighth signal connector connected with at least two first signal connectors of one of the mainboards through a third cable.

[0030] On the other hand, the number of the second signal connectors is M, the number of the mainboards is at least 2M, each of the second signal connectors is connected with one of the first signal connectors of i mainboards through the cable, different second signal connectors are connected with different mainboards, M is a positive integer greater than or equal to 2, and i is a positive integer greater than or equal to 2 and less than or equal to M.

[0031] On the other hand, the number of the second signal connectors is one, and the number of the mainboards is four, each of the second signal connectors is connected with one of the first signal connectors of four mainboards through the cable.

[0032] The application further provides a server system including the above server.

[0033] On the other hand, the second signal connector of one of the servers is connected with one of the first signal connectors of the mainboard of at least one other server.

[0034] According to the application, since the single second signal connector is connected with the first signal connectors of the at least two mainboards through the cable, the connection between the single second signal connector and the processors of the at least two mainboards is realized, cross-processor communication between the single second signal connector and the more than two processors is realized, the communication overhead between the single processor and the second signal connector is relatively small, therefore, the technical problem of long communication delay of the processor in the related art can be solved, and the technical effect of reducing the communication delay of the processor is achieved. In addition, since the at least two mainboards are stacked along the height direction of the case, and each mainboard includes at least one processor, when the single mainboard cannot be provided with multiple processors due to the width size limitation of the case, the interconnection problem between the preset device and the multiple processors can be solved.

[0035] When the second signal connector is connected with the network interface card, the network interface card is connected with one of the first signal connectors of the at least two mainboards through the cable, that is, the network interface card is a multihost network card, the signals of the processors of the more than two mainboards can be transmitted to one network interface card, so that the network card overhead of the processor of the single mainboard is reduced, the delay of the network card link is reduced, the network card performance is improved, and the network bottleneck is avoided, which is especially suitable for business scenarios that rely on high-performance computing clusters.

[0036] When the second signal connector is connected with the data processor, the data processor (DPU, Data Processing Unit) is connected with one of the first signal connectors of the at least two mainboards through the cable, that is, the processors of the more than two mainboards can share the data processor, so that the data processor can work cooperatively with the processors of the at least two mainboards and migrate the computing power to each other, so that the server performance can be optimized, and each processor of the mainboard does not need to be matched with a data processor, therefore, the hardware cost of the data processor shared by the processor of the single mainboard can be greatly reduced.

[0037] When the second signal connector is connected with the first expansion board, the first expansion board is connected with one of the first signal connectors of the at least two mainboards through the cable, and the first expansion board can be connected with other devices according to actual needs, so that the expansion needs of the more than two mainboards for other devices can be met. BRIEF DESCRIPTION OF DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments or the related art, the accompanying drawings needed to be used in the embodiments or the related art description will be briefly introduced. Obviously, the accompanying drawings in the following description are only embodiments of the application, and those skilled in the art can obtain other accompanying drawings according to the provided accompanying drawings without creating any creative labor.

[0039] Figure 1This is a schematic diagram of the connection structure between the server motherboard and the preset device provided in a specific embodiment of the present utility model.

[0040] Figure 2 This is a schematic diagram of the connection from the motherboard to the second signal connector.

[0041] Figure 3 This is a schematic diagram showing the structure of two Multihost network cards connected to four motherboards.

[0042] Figure 4 This is a schematic diagram showing the structure of the dual DPUs connected to four motherboards.

[0043] Figure 5 This diagram illustrates the structure of two dual-processor servers, each with its own independent DPU, after partitioning the four motherboards.

[0044] Figure 6 This diagram illustrates the structure of two dual-processor servers sharing a single DPU after partitioning four motherboards.

[0045] Figure 7 This is a schematic diagram of the interconnection structure of four motherboards' processors.

[0046] Figure 8 This is a schematic diagram showing the interconnection of the processors on the motherboards of two two-way servers after a four-way server has been split up.

[0047] Figure 9 This is a schematic diagram of the fourth signal connector.

[0048] Figure 10 This is a structural schematic diagram of the fastener.

[0049] Figure label:

[0050] 10-Main board; 11-First signal connector; 12-Second signal connector; 20-Preset device; 21-Sixth signal connector; 30-Cable; 31-First cable; 32-Second cable; 33-Fourth signal connector; 331-Protrusion; 34-Fifth signal connector; 40-Fixed part; 41-Crossbeam; 411-Groove; 42-Vertical beam; 43-Fixed folded edge. Detailed Implementation

[0051] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0052] It should be noted that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. The terms "mount", "connect", "connect" should be broadly understood, for example, it can be fixed connection, or detachable connection, or integral connection; can be mechanical connection, or electrical connection; can be directly connected, or indirectly connected through intermediate medium, can be the communication between two elements inside. The terms "parallel", "perpendicular", "equal" include the case described and the case similar to the case described, the range of the similar case is within the acceptable deviation range, wherein the acceptable deviation range is determined by the person skilled in the art considering the measurement being discussed and the error related to the measurement of the specific quantity (i.e. the limitation of the measurement system). For example, "parallel" includes absolute parallel and approximate parallel, wherein the acceptable deviation range of approximate parallel may, for example, be within 5° deviation; "perpendicular" includes absolute perpendicular and approximate perpendicular, wherein the acceptable deviation range of approximate perpendicular may, for example, also be within 5° deviation. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality may, for example, be that the difference between the two equalities is less than or equal to 5% of either. For the person skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0053] In order for those skilled in the art to better understand the present application, the present application will be further described in detail below in conjunction with the drawings and specific embodiments.

[0054] Please refer to Figure 1The utility model embodiment provides a kind of server, including cabinet, n mainboards 10, at least one second signal connector 12 and cable, mainboard 10 and second signal connector 12 are located in cabinet, all mainboards 10 are stacked in cabinet, each mainboard 10 includes at least one processor and at least one first signal connector 11, and first signal connector 11 is connected with processor;Second signal connector 12 is used to connect preset device 20, and preset device 20 includes at least one of network interface card, data processor, first extension board and computing fast link device, and second signal connector 12 is connected with the first signal connector 11 of at least two mainboards 10 of n mainboards 10 respectively by cable 30 one of each other.It is, n is the positive integer greater than or equal to 2.In addition, illustratively, second signal connector 12 can be located in the rear window of cabinet, to facilitate the connection of preset device.

[0055] That is, in the embodiment, single second signal connector 12 is connected with the first signal connector 11 of at least two mainboards 10 by cable 30, that is, the connection of single preset device 20 and the processor of at least two mainboards 10 can be realized, to realize the cross-processor communication between single preset device 20 and more than two processors, so that the communication overhead between single processor and preset device 20 such as network interface card, data processor or first extension board is relatively small, to reduce the purpose of processor communication delay.

[0056] In addition, it needs to be explained that all mainboards 10 are stacked along the height direction of cabinet, since at least two mainboards 10 are stacked along the height direction of cabinet, and each mainboard 10 includes at least one processor, so that the server includes at least two processors, the interconnection problem between preset device 20 and multiple processors when single mainboard 10 cannot be set multiple processors due to the width size limitation of cabinet can be solved, multiple mainboards 10 are stacked along the height direction of cabinet, and do not occupy too much width size additionally, so that the width limitation of cabinet in related art can be met, and simultaneously, multiple processors are realized by setting multiple mainboards 10.It needs to be explained that the processor in the embodiment refers to central processing unit CPU.In addition, it can be understood that the height direction of cabinet in the embodiment refers to the height direction of conventional cabinet, such as the height direction of 1U, 2U etc.

[0057] It can be understood that when the second signal connector 12 connects the network interface card, the network interface card is connected to one of the first signal connectors 11 of each of the at least two mainboards 10 through the cable 30, that is, the network interface card is a multihost network card, and the signals of the processors of two or more mainboards 10 can be transmitted to one network interface card, so that the network card overhead of the processor of a single mainboard 10 can be reduced, the delay of the network card link can be reduced, the network card performance can be improved, and the network bottleneck can be avoided, which is especially suitable for business scenarios that rely on high-performance computing clusters. Exemplarily, the network interface card is an OCP network card (OpenCompute Project Network Card).

[0058] When the second signal connector 12 connects the data processor, the data processor (DPU, Data Processing Unit) is connected to one of the first signal connectors 11 of each of the at least two mainboards 10 through the cable 30, that is, the processors of two or more mainboards 10 can share the data processor, so that the data processor can work cooperatively with the processors of the at least two mainboards 10 and migrate computing power to each other, thereby optimizing the server performance, and each processor of the mainboard 10 does not need to be matched with a data processor, so that the hardware cost of the data processor shared by the processor of a single mainboard 10 can be greatly reduced.

[0059] When the second signal connector 12 connects the first expansion board, the first expansion board is connected to one of the first signal connectors 11 of each of the at least two mainboards 10 through the cable 30, and the first expansion board can be connected to other devices according to actual needs, so that the expansion needs of two or more mainboards 10 for other devices can be met.

[0060] It should be noted that the compute express link device, that is, the CXL device, when the second signal connector 12 connects the CXL device, the CXL device is connected to one of the first signal connectors 11 of each of the at least two mainboards 10 through the cable 30. Exemplarily, the first signal connector 11 on the mainboard 10 is an MCIO terminal, and the signal connected out of the MCIO terminal is a flexible bus signal, which can switch the PCIe signal or the CXL signal according to the device connected downstream; when the second signal connector 12 connects the CXL device, the server firmware can be used to identify the CXL device, and the bus can be used to assign the CXL signal to the first signal connector 11. In addition, when the second signal connector 12 connects the OCP network card, the DPU or the first expansion board, the first signal connector 11 can output the PCIe signal, so that the second signal connector 12 can connect the PCIe device or the CXL device according to the user's configuration needs.

[0061] In addition, it can be understood that when the number of second signal connectors 12 is at least two, the second signal connectors 12 can support a redundant design. For example, the number of second signal connectors 12 is two, and the preset device 20 is two OCP network cards or two DPUs, that is, the second signal connectors 12 support a redundant design of double multihost OCP network cards, and when one of the OCP network cards fails, the other OCP network card can be used as a backup. For some application scenarios, only one of the OCP network cards needs to be used, and the other OCP network card is in standby state. When one of the OCP network cards fails, the OCP network card in standby state can replace the failed OCP network card to work, avoiding service interruption and improving server reliability.

[0062] It should be noted that with the high-speed growth of server platform processor cores, high-specification single-way motherboards are produced. For example, the width of the single-way motherboard is 423 mm, and the depth is 305 mm. The extreme design of the computing performance of the single-way motherboard enables a single machine to support higher memory bandwidth, thereby meeting the scene requirements of high bandwidth, high cores, and large memory. In some embodiments, each motherboard 10 is the above-mentioned single-way motherboard, that is, the present embodiment can realize the interconnection of two or more single-way motherboards. For a four-way server of a key computing type, since it is impossible to design a single motherboard to contain four processors within the width of a standard 19-inch chassis, four single-way motherboards can be used to realize the four-way server design.

[0063] In addition, as shown in Figure 2 In some embodiments, the first signal connector 11 is an x8 signal connector, for example, an x8 MCIO connector, that is, the processor of the motherboard 10 outputs a group of x8 PCIe signals through the x8 MCIO connector on the motherboard 10. It can be understood that the x8 MCIO connector is a conventional MCIO terminal on the motherboard 10, which is not located at the board edge and is not used for board-to-board connection. Obviously, the present embodiment sets the first signal connector 11 as the x8 MCIO connector, which can expand the use scenarios of the x8 MCIO connector. For example, the MCIO terminal can be connected to the NVME backplane through a cable, and if PCIe devices need to be expanded, the MCIO terminal can be connected to a PCIe expansion card through a cable. The MCIO terminal output by the processor of the single-way motherboard can be used as a PCIe resource. If a two-way server or a multi-way server is needed, the MCIO signal of the MCIO terminal can be used as the interconnection UPI signal (as shown in Figure 7 and Figure 8 ) between the processors of different motherboards 10, so as to realize the interconnection between the processors of different motherboards 10 and the transmission of information between the processors of different motherboards 10.

[0064] In addition, it should be noted that the single preset device 20 is connected to one of the first signal connectors 11 of each of the at least two mainboards 10 via the cable 30. The single preset device 20 can be connected to one of the first signal connectors 11 of each of some of the mainboards 10 via the cable 30 (as shown in FIG. 2), or the single preset device 20 can be connected to one of the first signal connectors 11 of each of all of the mainboards 10 via the cable 30 (as shown in FIG. 3). Figure 5 Figure 6

[0065] It can be understood that when the single preset device 20 is connected to one of the first signal connectors 11 of each of some of the mainboards 10 via the cable 30, the mainboards 10 connected to the preset device 20 can be taken as a partition unit, and the other mainboards 10 and the corresponding preset device 20 can be taken as another partition unit, which is beneficial to the splitting of the multi-path server. For example, when the number of the mainboards 10 is four, the preset device 20 is a data processing unit (DPU), and the number of the data processing units (DPUs) is two, one data processing unit (DPU) is connected to two mainboards 10, and the other data processing unit (DPU) is connected to the other two mainboards 10, that is, the processors of every two mainboards 10 share one data processing unit (DPU), a four-path server can be changed into two two-path servers, and each two-path server supports an independent data processing unit (DPU).

[0066] In addition, when the single preset device 20 is connected to one of the first signal connectors 11 of each of all of the mainboards 10 via the cable 30, that is, the processors of all of the mainboards 10 share one preset device 20, which is beneficial to reducing the communication overhead of the processors of each mainboard 10. At this time, if the multi-path server is split, it is beneficial to realize that multiple servers share one preset device 20. For example, when the number of the mainboards 10 is four, the preset device 20 is a data processing unit (DPU), and the number of the data processing units (DPUs) is one, one data processing unit (DPU) is connected to the four mainboards 10, that is, the processors of the four mainboards 10 share one data processing unit (DPU), and if the four-path server is changed into two two-path servers, two servers can share one data processing unit (DPU).

[0067] ​​With the diversified development of application scenarios of the server, the load difference is large, for example, some key database applications need to use four-way servers, and some traditional cloud businesses only need to use two-way servers, therefore, the scheme of the embodiment of the utility model is beneficial to realize the switching transformation of four-way servers and two-way servers, that is, a single server can support physical partitioning, for example, for a four-way server, if a data processor (DPU) is connected with two mainboards 10 as a partition, then the four-way server includes two partitions, that is, double partitions, the four-way server with double partitions can be switched to two two-way servers, and the two two-way servers can respectively execute different businesses and each is matched with a data processor (DPU). For a four-way server, if a data processor (DPU) is connected with four mainboards 10 as a partition, then the four-way server is single partition, and when the four-way server with single partition is switched to two two-way servers, then the two two-way servers share the same data processor (DPU), and this condition is applied to the application scenario in which the data processor (DPU) does not need to do a large amount of work, and considering that the cost of the data processor (DPU) is relatively high, at this time, the two two-way servers sharing the same data processor (DPU) can reduce the cost. It can be seen that the architecture mode of the embodiment of the utility model can flexibly realize different expansion use requirements of users.

[0068] In order to facilitate connection, as shown in Figure 2 and Figure 3 In some embodiments, the cable 30 includes a first cable 31 and a second cable 32, two ends of the first cable 31 are respectively provided with a third signal connector and a fourth signal connector 33, the third signal connector is connected with the first signal connector 11, and the fourth signal connector 33 is arranged at the edge of the mainboard 10; one end of the second cable 32 is connected with a fifth signal connector 34, the other end of the second cable 32 is connected with the second signal connector 12, the fifth signal connector 34 is connected with the fourth signal connector 33, the second signal connector 12 is used for being connected with the sixth signal connector 21 of the preset device 20, and the second signal connector 12 is connected with the second cable 32 corresponding to each of the first signal connectors 11 of the at least two mainboards 10.

[0069] That is, in the embodiment, the cable 30 between the second signal connector 12 and the first signal connector 11 of the mainboard 10 is designed as a segmented cable, the first cable 31 is a first segment cable, which is led out from the first signal connector 11 of the mainboard 10 to the edge of the mainboard 10, and the second cable 32 is a second segment cable, which is extended from the edge of the mainboard 10 to the second signal connector 12. The first cable 31 is connected with the first signal connector 11 of the mainboard 10 through a third signal connector, the first cable 31 and the second cable 32 are connected with each other through a fourth signal connector 33 and a fifth signal connector 34, and the second cable 32 is connected with the sixth signal connector 21 of the preset device 20 through the second signal connector 12. It can be understood that the design of the third signal connector, the fourth signal connector 33, the fifth signal connector 34 and the second signal connector 12 is beneficial to the connection between the first cable 31 and the mainboard 10, the first cable 31 and the second cable 32, and the second cable 32 and the preset device 20, and is convenient for operation. In addition, the design is also beneficial to the positioning and fixing of the positions of the first cable 31 and the second cable 32.

[0070] Further, in some embodiments, the first signal connector 11, the third signal connector, the fourth signal connector 33, the fifth signal connector 34 and the second signal connector 12 are all blind insertion quick release connectors. That is, the connection between the first cable 31 and the mainboard 10, the connection between the second cable 32 and the first cable 31, and the connection between the second cable 32 and the preset device 20 are all quick release blind insertion interconnection designs, which are beneficial to the quick insertion and maintenance of the preset device 20 and the hot plug of the preset device 20.

[0071] Further, in some embodiments, the second signal connector 12 is used for hot plug connection with the preset device 20. That is, the present embodiment supports hot plug of network interface cards, data processors, first expansion boards and computing fast link devices, etc. Especially when the number of second signal connectors 12 is at least two, the number of preset devices 20 is at least two, for example, the case where a server includes at least two OCP network cards and / or at least two DPUs, at least two OCP network cards can be hot plugged and at least two DPUs can be hot plugged. It can be understood that in order to realize hot plug, the cable 30 interconnecting between the second signal connector 12 and each first signal connector adopts a quick-release blind plug connector, and in addition, for power supply of the preset device 20, a button for controlling power supply of the preset device 20 needs to be provided, and when hot plugging the preset device 20, the power supply of the preset device 20 needs to be turned off first before hot plugging, without the need to turn off the power supply of the server. In addition, it can be understood that the second signal connector 12 supports blind plug hot plug, and through the hard connection between the second signal connector 12 and the sixth signal connector 21 of the preset device 20, it is beneficial to quickly maintain the devices on the mainboard 10. That is, when it is necessary to maintain the components on the mainboard 10, such as processors or memories, the preset device 20, such as OCP network cards, DPUs, first expansion boards or CXL devices, etc. can be directly pulled out through the rear window of the server, after the preset device 20 is pulled out, the second cable 32 can be further pulled out, and then the computing node is extracted to maintain the mainboard 10. It should be noted that the four mainboards 10 in the present embodiment can be divided into two computing nodes, and each computing node includes two mainboards 10. Exemplarily, one computing node includes a first mainboard (denoted as S0) and a second mainboard (denoted as S1), and the other computing node includes a third mainboard (denoted as S2) and a fourth mainboard (denoted as S3).

[0072] Further, in some embodiments, the server further includes a cable quick-release module support which is detachably arranged in the case, and the fifth signal connector 34 and the second signal connector 12 are respectively arranged in the corresponding cable quick-release module support.

[0073] That is, the embodiment supports the fifth signal connector 34 and the second signal connector 12 by the cable quick release module support, to ensure the stability and reliability of the position of the second signal connector 12 and the sixth signal connector 21. In addition, when the mainboard 10 needs to be maintained, after the preset device 20 is pulled out, the cable quick release module support is removed, the second cable 32 is removed, and then the mainboard 10 is pulled out to maintain the mainboard 10. Exemplarily, the first signal connector 11, the third signal connector, the fourth signal connector 33, the fifth signal connector 34 and the second signal connector 12 all support hot plug, that is, through hot plug, hot maintenance of the mainboard 10 is realized, that is, maintenance of the mainboard 10 is realized without turning off the power supply of the server. In addition, as described below, the fourth signal connector 33 of the first cable 31 is fixedly arranged at the edge of the mainboard 10 by the fixing member 40. The fixing member 40 is detachably connected with the mainboard 10, that is, by detaching the fixing member 40 and pulling out the third signal connector, the first cable 31 can be removed from the mainboard 10 to facilitate maintenance of the mainboard 10.

[0074] Further, as shown in Figure 3 some embodiments, a first signal connector 11 of a single mainboard 10 corresponds to a fifth signal connector 34 connected with N second cables 32, N is a positive integer greater than or equal to 2; a single second signal connector 12 is connected with at least one second cable 32 corresponding to a first signal connector 11 of at least two mainboards 10.

[0075] That is, the second cable 32 in the embodiment is formed by dividing a cable into N parts, that is, the second cable 32 is one of the N cables led out by the fifth signal connector 34 corresponding to a single first signal connector 11, and a single second signal connector 12 is connected with at least one second cable 32 corresponding to a first signal connector 11 of at least two mainboards 10. This scheme is advantageous for reasonably allocating signals from each mainboard 10 to the second signal connector 12, and is advantageous for realizing interconnection of the second signal connector 12 to multiple mainboards 10.

[0076] It should be noted that the embodiment does not limit the specific number of N, exemplarily N=2, that is, the second cable 32 is formed by dividing a cable into two parts, and the second cable 32 is one of the two cables led out by the fifth signal connector 34 corresponding to a single first signal connector 11.

[0077] Further, in some embodiments, the first signal connector 11 and the fifth signal connector 34 are both xL signal connectors, the second signal connector 12 is an xP signal connector, the number of the second cables 32 connected by the single second signal connector 12 is K, and then:

[0078] ;

[0079] wherein L, P and K are all positive integers.

[0080] It can be understood that the first signal connector 11 and the fifth signal connector 34 are both xL signal connectors, after the fifth signal connector 34 corresponding to the single first signal connector 11 is led out N cables, the signal transmitted by the single second cable 32 is an xL / N signal, and in order to meet the xP signal requirement of the second signal connector 12, the number of the second cables 32 is . That is, the second signal connector 12 needs to be connected with at least two first signal connectors 11 of the mainboards 10 respectively through second cables 32.

[0081] Further, it needs to be explained that the specific number of L and P is not limited in the embodiment, and in some embodiments, the value of P is 8, 16 or 32, and the value of L is 8 or 16. That is, the second signal connector 12 can be an x8 signal connector, an x16 signal connector or an x32 signal connector, and of course, the second signal connector 12 can also be other signal connectors according to actual requirements. The first signal connector 11 is an x8 signal connector or an x16 signal connector.

[0082] In some embodiments, the first signal connector 11 is an x8 signal connector, the second signal connector 12 and the sixth signal connector 21 are both x16 signal connectors, the number of the mainboards 10 is four, the number of the preset devices 20 is two, the two preset devices 20 are both network interface cards or both data processors, the number of the second cables 32 corresponding to the single first signal connector 11 of the mainboard 10 is two, the second cables 32 are used for transmitting x4 signals, and the two second signal connectors 12 are both used for connecting with the single first signal connector 11 of the four mainboards 10 respectively.

[0083] As Figure 3As shown, when both preset devices 20 are network interface cards, the scheme is a double Multihost network card, for the convenience of description, the two Multihost network cards are respectively called Multihost OCP0 and Multihost OCP1, in the embodiment, the sixth signal connectors 21 of the Multihost OCP0 and the Multihost OCP1 are both x16 signal connectors, exemplarily, the sixth signal connector 21 is a first OCP 4C+ connector, and the second signal connector 12 is a second OCP 4C+ connector. In addition, the four mainboards 10 are respectively called a first mainboard (denoted as S0), a second mainboard (denoted as S1), a third mainboard (denoted as S2) and a fourth mainboard (denoted as S3); the processor of the first mainboard S0 is called CPU0, the processor of the second mainboard S1 is called CPU1, the processor of the third mainboard S2 is called CPU2, and the processor of the fourth mainboard S3 is called CPU3. The port numbered P3 in the processor on each mainboard 10 is defined as a P3 port, and the P3 port is an x16 PCIe port, wherein the lower 8 bits (P3:0~7) of the P3 port are led out on the mainboard 10 through the MCIO connector (that is, the first signal connector 11). In addition, in the embodiment, the number of second cables 32 corresponding to a first signal connector 11 of a single mainboard 10 is two, that is, the fifth signal connector 34 of each first signal connector 11 of the mainboard 10 leads a split cable, and the P3 port of the processor of each mainboard 10 is connected to the two Multihost network cards, that is, the Multihost OCP0 and the Multihost OCP1, through the first cable 31 and the two second cables 32 respectively connected to the fifth signal connector 34 corresponding to the first cable 31.Exemplarily, the 4-bit signals of P3 port of 0~3 of the processor of each mainboard 10 are connected to Multihost OCP0 via the first cable 31 and one of the second cables 32, the 4-bit signals of P3 port of 4~7 of the processor of each mainboard 10 are connected to Multihost OCP1 via the first cable 31 and another of the second cables 32, that is, the first cable 31 is used to transmit x8 signals, the second cable 32 is used to transmit x4 signals, finally, the four second cables 32 corresponding to the four mainboards 10 and used to transmit the 4-bit signals of P3 port of 0~3 are merged together and connected to the second signal connector 12, for example, the second OCP 4C+ connector described above, to be connected to the x16 signal connector of Multihost OCP0, for example, the first OCP 4C+ connector described above; similarly, the four second cables 32 corresponding to the four mainboards 10 and used to transmit the 4-bit signals of P3 port of 4~7 are merged together and connected to another second signal connector 12, for example, the second OCP 4C+ connector described above, to be connected to the x16 signal connector of Multihost OCP1, for example, the first OCP 4C+ connector described above.

[0084] As shown in the following Table 1, the PCIe resources allocated to the two Multihost network cards are given to the processors of the four mainboards 10.

[0085] Table 1

[0086]

[0087] Similarly, as Figure 4As shown, when both preset devices 20 are data processors, the scheme is a double data processor, for the convenience of description, the two data processors are respectively referred to as DPU0 and DPU1, in the embodiment, the sixth signal connectors 21 of the DPU0 and the DPU1 are both x16 signal connectors. In addition, the four motherboards 10 are respectively referred to as a first motherboard (denoted as S0), a second motherboard (denoted as S1), a third motherboard (denoted as S2) and a fourth motherboard (denoted as S3); the processor of the first motherboard S0 is referred to as CPU0, the processor of the second motherboard S1 is referred to as CPU1, the processor of the third motherboard S2 is referred to as CPU2, and the processor of the fourth motherboard S3 is referred to as CPU3. The port numbered P10 in the processor on each motherboard 10 is defined as a P10 port, which is an x16 PCIe port, wherein the lower 8 bits (P10:0~7) of the P10 port are led out on the motherboard 10 through the MCIO connector (that is, the first signal connector 11). In addition, in the embodiment, N=2, that is, the fifth signal connector 34 leads a cable that is divided into two, the number of the second cables 32 corresponding to a single first cable 31 is two, and the first signal connector 11 of the P10 port of the processor of each motherboard 10 is connected to the two DPUs, that is, the DPU0 and the DPU1, through the first cable 31 and the two second cables 32 connected to the first cable 31 respectively. Exemplarily, the 4-bit signals of 0~3 of the P10 port of the processor of each motherboard 10 are connected to the DPU0 through the first cable 31 and one of the second cables 32, and the 4-bit signals of 4~7 of the P10 port of the processor of each motherboard 10 are connected to the DPU1 through the first cable 31 and the other second cable 32, that is, the first cable 31 is used to transmit x8 signals, and the second cable 32 is used to transmit x4 signals. Finally, the four second cables 32 corresponding to the four motherboards 10 and used to transmit the 4-bit signals of 0~3 of the P10 port are merged together and connected to the second signal connector 12 to be connected to the x16 signal connector of the DPU0; similarly, the four second cables 32 corresponding to the four motherboards 10 and used to transmit the 4-bit signals of 4~7 of the P10 port are merged together and connected to another second signal connector 12 to be connected to the x16 signal connector of the DPU1.

[0088] As shown in the following table 2, the PCIe resources allocated to the two DPUs for the processors of the four motherboards 10.

[0089] Table 2

[0090]

[0091] In some embodiments, the second signal connector 12 is used to connect a second expansion board, and the second expansion board is used to connect a data processor, that is, in the present embodiment, the data processor is connected to the second signal connector 12 through the second expansion board, and the second expansion board is provided with a seventh signal connector, and the seventh signal connector is connected to the second signal connector 12.

[0092] That is, the present embodiment expands the application data processor (DPU) through the second expansion board, and in this case, the data processor is connected to one of the first signal connectors 11 of each motherboard 10 through the slot of the second expansion board.

[0093] In addition, in some embodiments, the second signal connector 12 and the sixth signal connector 21 are both x16 signal connectors, the number of the motherboards 10 is four, the number of the preset devices 20 is four, the four preset devices 20 are two network interface cards and two data processors, each motherboard 10 includes at least two first signal connectors 11, one of the two first signal connectors 11 of each motherboard 10 is used to connect the two network interface cards, and the other of the two first signal connectors 11 of each motherboard 10 is used to connect the two data processors, the number of the first cables 31 corresponding to one first signal connector 11 of a single motherboard 10 is one, and the number of the second cables 32 corresponding to one first signal connector 11 of a single motherboard 10 is two, the first cable 31 is used to transmit x8 signals, the second cable 32 is used to transmit x4 signals, and the two second signal connectors 12 used to connect the two network interface cards are both used to connect one first signal connector 11 of each of the four motherboards 10; and the two second signal connectors 12 used to connect the two data processors are both used to connect the other first signal connector 11 of each of the four motherboards 10.

[0094] That is, the present embodiment is a scheme of double Multihost network cards and double DPUs, and exemplarily, the P3 port of the processor on each motherboard 10 is defined to be used to connect the two Multihost network cards, and the P10 port of the processor on each motherboard 10 is defined to be used to connect the two DPUs, and then, as shown in Table 3, the PCIe resources allocated to the two Multihost network cards and the two DPUs by the processor of the four motherboards 10 are defined.

[0095] Table 3

[0096]

[0097] In addition, when the cable 30 connected between the processor of the motherboard 10 and the preset device 20 is divided into the first cable 31 and the second cable 32, in order to facilitate the fixation of the fourth signal connector 33, in some embodiments, the fourth signal connector 33 is fixedly arranged at the edge of the motherboard 10 through the fixing member 40.

[0098] That is, the fourth signal connector 33 is fixed to the edge of the mainboard 10 by the fixing member 40, which is beneficial to ensure the position accuracy and stability of the fourth signal connector 33, so as to ensure the reliability of the blind-mate connection between the second cable 32 and the first cable 31. It should be noted that the specific structure of the fixing member 40 is not limited in the present embodiment, as long as the fourth signal connector 33 can be fixed to the edge of the mainboard 10 by the fixing member 40.

[0099] Further, as shown in Figs. 4 and 5, in some embodiments, one of the fourth signal connector 33 and the fixing member 40 is provided with a protrusion 331, and the other is provided with a groove 411 matched with the protrusion 331. For example, the fourth signal connector 33 is provided with the protrusion 331, and the fixing member 40 is provided with the groove 411. For example, the top of the fourth signal connector 33 is provided with a rectangular protrusion 331, and the part of the fixing member 40 used to press above the fourth signal connector 33 is provided with a rectangular groove 411. When the fixing member 40 is installed, the rectangular groove 411 is aligned with the rectangular protrusion 331, so that the groove 411 clamps the protrusion 331. Then, the fixing member 40 is connected with the mainboard 10. The cooperation between the groove 411 and the protrusion 331 can limit the position, so as to fix the fourth signal connector 33, so as to ensure that the position of the fourth signal connector 33 remains unchanged. Figure 9 Figure 10 In addition, in some embodiments, the protrusion 331 and the groove 411 have a preset gap.

[0100] In addition, in some embodiments, the protrusion 331 and the groove 411 have a preset gap.

[0101] ​In other words, in this embodiment, the limiting position between the protrusion 331 and the groove 411 is a floating limiting position, meaning that the protrusion 331 has a certain offset within the groove 411. This allows the fourth signal connector 33 to have a certain adjustment range when it mates with the seventh signal connector, avoiding the problem of mating accuracy issues when the seventh signal connector 33 mates with the fourth signal connector 33 due to the fourth signal connector 33 being too rigidly fixed in position. It is understandable that, since one end of the second cable 32 needs to ensure the mating of the seventh signal connector with the fourth signal connector 33, and the other end of the second cable 32 needs to ensure the mating of the second signal connector 12 with the sixth signal connector 21, in this multi-connector mating situation, a preset gap exists between the protrusion 331 and the groove 411 to ensure smooth mating between each pair of connectors. This facilitates reliable mating of both ends of the second cable 32 by adjusting the position of the fourth signal connector 33. It should be noted that this embodiment does not limit the specific value of the preset gap between the protrusion 331 and the groove 411, as long as the position of the fourth signal connector 33 can be finely adjusted. For example, the range of the preset gap between the protrusion 331 and the groove 411 is 0~2mm, that is, the range of the single-sided gap between the protrusion 331 and the groove 411 is 0~1mm. For example, the preset gap between the protrusion 331 and the groove 411 is 0.3mm, 0.5mm, 0.8mm, 1mm, 1.4mm, 1.6mm, etc.

[0102] Furthermore, the above embodiments do not limit the specific shape of the fixing member 40, as long as it can achieve the fixing of the fixing member 40 to the fourth signal connector 33, such as... Figure 10 As shown, in some embodiments, the fixing member 40 includes a crossbeam 41, a vertical beam 42, and a fixing flange 43. The crossbeam 41 spans above the fourth signal connector 33 and is used to press against the fourth signal connector 33. There are at least two vertical beams 42, which are vertically connected to the crossbeam 41 to support the crossbeam 41 at a preset height, thereby ensuring that the crossbeam 41 can be pressed against the fourth signal connector 33. A space for accommodating the fourth signal connector 33 is formed between any two adjacent vertical beams 42. The fixing flange 43 is located at the bottom of the vertical beam 42 and has a mounting portion for fixing to the main board 10.

[0103] When installing, the fixing member 40 is installed from top to bottom, the space between the two vertical beams 42 is aligned with the fourth signal connector 33, and finally the horizontal beam 41 is pressed on the fourth signal connector 33. At this time, the fixed folded edge 43 is attached to the mainboard 10, and the fixed folded edge 43 can be fixed with the mainboard 10 to achieve the installation of the fixing member 40. It should be noted that the specific structure of the installation part of the fixed folded edge 43 and the fixing method thereof with the mainboard 10 are not limited in the embodiment, as long as the fixed folded edge 43 can be fixed with the mainboard 10. Exemplarily, the fixed folded edge 43 is screwed to the mainboard 10, and the connection method is simple and convenient to realize.

[0104] In addition, in order to facilitate the server to expand other devices, in some embodiments, the first expansion board is provided with at least two signal slots, exemplarily, the first expansion board is provided with an x16 signal slot or two x8 signal slots.

[0105] That is, in the embodiment, since the first expansion board is connected with one of the first signal connectors 11 of each of the at least two mainboards 10 through the cable 30, when the expansion device is inserted into the x16 signal slot or the two x8 signal slots of the first expansion board, the expansion of other devices can be realized, so that the user can support the use of different expansion devices according to different use scenarios and configuration requirements.

[0106] In addition, in some embodiments, the number of the first signal connectors 11 of each mainboard 10 is at least two, and the server further comprises an eighth signal connector connected with at least two first signal connectors 11 of one of the mainboards 10 through a third cable. That is, when the user explicitly wants to use one preset device 20, for example, uses one OCP, and the one OCP must be connected to one mainboard 10, the preset device 20 can be connected with the eighth signal connector. Exemplarily, the eighth signal connector is an x16 signal connector, and the eighth signal connector is connected with two x8 signal connectors of one of the mainboards 10 through a third cable. That is, the network interface card can be directly connected with the x16 signal connector, and the embodiment can realize the flexible switching of the direct connection of the network interface card with the x16 signal connector and the Multihost network card connection, and can meet the various needs of the user. By changing the cable connection method, the different configuration requirements of the user can be conveniently and flexibly realized.

[0107] In addition, in order to facilitate the splitting of the multi-path server, in some embodiments, the number of second signal connectors 12 is M, the number of mainboards 10 is at least 2M, each of the i mainboards 10 is connected to one of the first signal connectors 11 through a cable 30, different second signal connectors 12 are connected to different mainboards 10, M is a positive integer greater than or equal to 2, and i is a positive integer greater than or equal to 2 and less than or equal to M.

[0108] That is, the server in the present embodiment is divided into zones, for example, one preset device 20 is connected to one of the first signal connectors 11 of each of the i mainboards 10 as a zone, and the server in the present embodiment can be divided into at least two zones. Since different preset devices 20 are connected to different mainboards 10, different zones can have independent preset device 20 expansion, which is beneficial to the splitting of the multi-path server.

[0109] In some embodiments, the number of second signal connectors 12 is two, and the number of mainboards 10 is four. One of the second signal connectors 12 is connected to one of the first signal connectors 11 of each of two mainboards 10 through a cable 30, and the other second signal connector 12 is connected to one of the first signal connectors 11 of each of the other two mainboards 10 through a cable 30.

[0110] For example, as shown in FIG. 2, the server in the present embodiment is divided into two zones, and each zone has one preset device 20. The first zone has two mainboards 10, and the second zone has two mainboards 10. The first zone has one preset device 20 connected to one of the first signal connectors 11 of each of the two mainboards 10 through a cable 30, and the second zone has one preset device 20 connected to one of the first signal connectors 11 of each of the two mainboards 10 through a cable 30. Figure 5As shown, the number of M is 2, the preset device 20 is a data processor DPU, the number of the mainboard 10 is four, the number of i is 2, then each DPU connects two mainboards 10, for example, DPU0 connects the 4-bit signals of 0~3 of the P10 port of the CPU0 of the first mainboard S0 through a first cable 31 and a second cable 32, and connects the 4-bit signals of 4~7 of the P10 port of the CPU0 of the first mainboard S0 through the first cable 31 and another second cable 32, at the same time, DPU0 connects the 4-bit signals of 0~3 of the P10 port of the CPU1 of the second mainboard S1 through a first cable 31 and a second cable 32, and connects the 4-bit signals of 4~7 of the P10 port of the CPU1 of the second mainboard S1 through the first cable 31 and another second cable 32; DPU1 connects the 4-bit signals of 0~3 of the P10 port of the CPU2 of the third mainboard S2 through a first cable 31 and a second cable 32, and connects the 4-bit signals of 4~7 of the P10 port of the CPU2 of the third mainboard S2 through the first cable 31 and another second cable 32, at the same time, DPU1 connects the 4-bit signals of 0~3 of the P10 port of the CPU3 of the fourth mainboard S3 through a first cable 31 and a second cable 32, and connects the 4-bit signals of 4~7 of the P10 port of the CPU3 of the fourth mainboard S3 through the first cable 31 and another second cable 32. That is, DPU0, the first mainboard S0 and the second mainboard S1 are a partition, DPU1, the third mainboard S2 and the fourth mainboard S3 are a partition, then at this time, a four-way server can be split into two two-way servers, and the two two-way servers respectively have independent DPU expansion. Table 4 below is the resource allocation when each partition has independent DPU expansion, in order to facilitate understanding, the two two-way servers are respectively referred to as the first two-way server and the second two-way server.

[0111] Table 4

[0112]

[0113] In some other embodiments, the preset device 20 is connected with each of the first signal connectors 11 of all the mainboards 10 through the cable 30. Exemplarily, the number of the second signal connector 12 is one, and the number of the mainboard 10 is four, the second signal connector 12 is connected with each of the first signal connectors 11 of the four mainboards 10 through the cable 30.

[0114] For example, as Figure 6As shown, one DPU is connected with one of the first signal connectors 11 of each of the four mainboards 10 through the cable 30, and as a partition, when the four-way server is split into two two-way servers, the two two-way servers can share one DPU. For example, the DPU0 is connected with the 4-bit signals of 0~3 of the P10 port of the CPU0 of the first mainboard S0 through the first first cable 31 and the first second cable 32, connected with the 4-bit signals of 0~3 of the P10 port of the CPU1 of the second mainboard S1 through the second first cable 31 and the second second cable 32, connected with the 4-bit signals of 0~3 of the P10 port of the CPU2 of the third mainboard S2 through the third first cable 31 and the third second cable 32, and connected with the 4-bit signals of 0~3 of the P10 port of the CPU3 of the fourth mainboard S3 through the fourth first cable 31 and the fourth second cable 32. In this case, when the four-way server is split into two two-way servers, the two two-way servers share one DPU0. As shown in Table 5, the resource allocation when the two two-way servers share one DPU0.

[0115] Table 5

[0116]

[0117] In addition to the above-mentioned server, the embodiment of the utility model also provides a server system comprising the server disclosed in the above-mentioned embodiment, which comprises at least two servers disclosed in any one of the above-mentioned embodiments.

[0118] That is to say, the preset device 20 of the single server in the embodiment is connected with the first signal connectors 11 of at least two mainboards 10 through the cable 30, realizing the cross-processor communication between the single preset device 20 and two or more processors, so that the communication overhead between the single processor and the preset device 20 such as the network interface card, the data processor or the first expansion board is relatively small, and the purpose of reducing the processor communication delay is achieved. In addition, different servers have independent preset devices 20, so that different services can be run by using different servers.

[0119] Further, in some embodiments, the second signal connector 12 of one server is connected with one of the first signal connectors 11 of the mainboard 10 of at least one other server.

[0120] That is to say, in the embodiment, the interconnection between multiple servers is realized, so that multiple servers can share one preset device 20.

[0121] It should be further noted that the terms such as first and second, and the like, are used merely to distinguish one entity or action from another without necessarily requiring or implying any actual such relationship or order between such entities or actions.

[0122] The various embodiments described in this specification are presented purely by way of example and for purposes of illustration only. Each of the various embodiments highlights a different aspect of the application, and the embodiments are not mutually exclusive.

[0123] The above provides a kind of server and server system provided in the application in detail.This paper applies specific example to the principle and implementation mode of the application are described, the above embodiment is only for helping to understand the method of the application and its core idea.It should be pointed out, for the ordinary skill in the art, without departing from the principle of the application, the application can be improved and modified to several, these improvements and modifications also fall within the scope of protection of the claims of the application.

Claims

1. A server, characterized in that, include: Chassis; n motherboards (10) are stacked in the chassis. Each motherboard (10) includes at least one processor and at least one first signal connector (11) connected to the processor, where n is a positive integer greater than or equal to 2. At least one second signal connector (12) is disposed in the chassis for connecting a preset device (20), the preset device (20) including at least one of a network interface card, a data processor, a first expansion board and a computing fast link device; the second signal connector (12) is connected via a cable (30) to one of the first signal connectors (11) of at least two of the n motherboards (10).

2. The server according to claim 1, characterized in that, The cable (30) includes: The first cable (31) has a third signal connector and a fourth signal connector (33) at both ends, the third signal connector is connected to the first signal connector (11), and the fourth signal connector (33) is located at the edge of the motherboard (10); The second cable (32) is connected at one end to the fifth signal connector (34) and at the other end to the second signal connector (12). The fifth signal connector (34) is connected to the fourth signal connector (33). The second signal connector (12) is connected to the second cable (32) corresponding to one of the first signal connectors (11) of each of the at least two motherboards (10).

3. The server according to claim 2, characterized in that, The fifth signal connector (34) corresponding to one of the first signal connectors (11) of a single motherboard (10) is connected to N second cables (32), where N is a positive integer greater than or equal to 2; A single second signal connector (12) is connected to at least one second cable (32) corresponding to one of the first signal connectors (11) of each of the at least two motherboards (10).

4. The server according to claim 3, characterized in that, The first signal connector (11) and the fifth signal connector (34) are both xL signal connectors, the second signal connector (12) is an xP signal connector, and the number of second cables (32) connected to a single second signal connector (12) is K. Therefore: ； Where L, P and K are all positive integers.

5. The server according to claim 2, characterized in that, The first signal connector (11), the third signal connector, the fourth signal connector (33), the fifth signal connector (34) and the second signal connector (12) are all blind-plug quick-release connectors; the second signal connector (12) is used for hot-plug connection with the preset device (20).

6. The server according to claim 5, characterized in that, Also includes: The cable quick-release module bracket is detachably disposed inside the chassis, and the fifth signal connector (34) and the second signal connector (12) are respectively disposed on the corresponding cable quick-release module bracket.

7. The server according to any one of claims 2-6, characterized in that, The fourth signal connector (33) is fixed to the edge of the motherboard (10) by a fastener (40).

8. The server according to claim 7, characterized in that, One of the fourth signal connector (33) and the fixing member (40) is provided with a protrusion (331), and the other is provided with a groove (411) that mates with the protrusion (331); there is a preset gap between the protrusion (331) and the groove (411).

9. The server according to claim 7, characterized in that, The fastener (40) includes: A crossbeam (41) spans above the fourth signal connector (33) and is used to press against the fourth signal connector (33); At least two vertical beams (42) are perpendicularly connected to the horizontal beam (41), and a space for accommodating the fourth signal connector (33) is formed between any two adjacent vertical beams (42); A fixed flange (43) is provided at the bottom of the vertical beam (42) and is provided with a mounting part for fixing to the main board (10).

10. The server according to any one of claims 1-6, characterized in that, The second signal connector (12) is used to connect to the second expansion board, which is used to connect to the data processor; and / or, The first expansion board has at least two types of signal slots.

11. The server according to any one of claims 1-6, characterized in that, Each of the motherboards (10) includes at least two of the first signal connectors (11), and the server also includes an eighth signal connector, which is connected to at least two of the first signal connectors (11) of one of the motherboards (10) via a third cable.

12. The server according to any one of claims 1-6, characterized in that, The number of the second signal connectors (12) is M, the number of the motherboards (10) is at least 2M, the second signal connectors (12) are connected to one of the first signal connectors (11) of each of the i motherboards (10) via the cable (30), different second signal connectors (12) are connected to different motherboards (10), M is a positive integer greater than or equal to 2, and i is a positive integer greater than or equal to 2 and less than or equal to M.

13. The server according to any one of claims 1-6, characterized in that, The number of the second signal connector (12) is one, and the number of the motherboards (10) is four. The second signal connector (12) is connected to one of the first signal connectors (11) of each of the four motherboards (10) via the cable (30).

14. A server system, characterized in that, Includes at least two servers as described in any one of claims 1-13.

15. The server system according to claim 14, characterized in that, The second signal connector (12) of one of the servers is connected to one of the first signal connectors (11) of the motherboard (10) of at least one of the other servers.

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