High-order HDI circuit board test structure
By setting test pads on the circuit board, including test vias and blind vias, the problem of interlayer connection misalignment in high-end HDI circuit boards is solved, enabling fast and accurate via location detection and avoiding destructive testing and increased costs.
Patent Information
- Application Number
- CN202423084184.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-13
- Publication Date
- 2025-12-02
- Estimated Expiration
- 2034-12-13
AI Technical Summary
During the manufacturing process of high-end HDI circuit boards, misalignment of interlayer connections may occur, leading to quality problems. Traditional cross-sectional inspection is inefficient and easily affected by orientation, making it difficult to conduct comprehensive inspection.
Test PADs are set outside the effective area of the circuit board. The test PADs include test through holes and test blind holes surrounding the through holes. The hole diameter is the same as the minimum hole diameter of the circuit board. The spacing between the through holes and blind holes is 0.05mm to 0.0635mm. The test PADs are distributed at the four corners or edges of the circuit board. The blind holes are arranged in a circular array to ensure the judgment of deviation in different directions.
It enables rapid and accurate determination of hole position deviation without destructive testing, reducing material costs and improving testing efficiency and result accuracy.
Smart Images
Figure CN223624374U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of circuit board technology, specifically to a high-order HDI circuit board test structure. Background Technology
[0002] PCB (Printed Circuit Board), also known as a printed circuit board, is an important electronic component. It serves as the support for electronic components and the carrier for their electrical interconnection. Because it is manufactured using electronic printing techniques, it is called a "printed" circuit board. Common types of circuit boards include single-sided, double-sided, and multi-layer boards. Currently, as various electronic devices are increasingly developing towards high performance, multi-functionality, and miniaturization, the requirements for circuit boards are also becoming higher. To meet these needs, high-density interconnect (HDI) circuit boards have developed rapidly. Nowadays, as the order of HDI circuit boards increases, the order of vias and blind vias also increases. During the manufacturing process of high-order circuit boards, factors such as board expansion and contraction and the precision of processing equipment can cause misalignment between different layers, leading to misalignment of vias and blind vias. This can affect interlayer connections and cause quality problems on the circuit board. In traditional processing, HDI circuit boards are typically inspected by slicing. However, slicing inspection is inefficient, is destructive testing, and cannot comprehensively inspect every circuit board. Furthermore, the results of slicing inspection are easily affected by the slicing direction. Utility Model Content
[0003] To address the aforementioned issues, this invention provides a high-order HDI circuit board testing structure.
[0004] This utility model is achieved using the following solution:
[0005] A high-order HDI circuit board test structure includes a circuit board, a test PAD is disposed outside the effective area of the circuit board, the test PAD includes a test through hole, and a plurality of test blind holes are disposed around the test through hole, with a gap between the test through hole and the test blind hole; the diameter of the test through hole is equal to the diameter of the smallest through hole in the circuit board, and the diameter of the test blind hole is equal to the diameter of the smallest blind hole in the circuit board.
[0006] Furthermore, the distance between the through hole and the blind hole is 0.05mm to 0.0635mm.
[0007] Furthermore, four test PADs are provided, with each test PAD positioned at one of the four corners of the circuit board.
[0008] Furthermore, four test PADs are provided, and the four test PADs are respectively located on the four edges of the circuit board.
[0009] Furthermore, the diameter of the coverage area of the test PAD is 1 mm.
[0010] Furthermore, the test blind holes are arranged in a circular array with the center of the test through holes as the reference.
[0011] Furthermore, the test blind hole is provided with 8 holes.
[0012] Furthermore, the distance between the test PAD and the edge of the effective area of the circuit board is greater than 5mm.
[0013] Compared with the prior art, the present invention has the following advantages:
[0014] This invention features a test PAD outside the effective area of the circuit board. The test PAD includes test through-holes and several test blind holes surrounding the through-holes. The diameter of the test through-holes is the same as the minimum diameter of the through-holes on the circuit board, and the diameter of the test blind holes is the same as the minimum diameter of the blind holes on the circuit board. This allows for rapid determination of hole misalignment during AOI testing without destructive testing or increased material costs. Furthermore, the blind holes surrounding the through-holes are positioned in different directions, allowing for the assessment of misalignment in different directions and ensuring the accuracy of the test results. Attached Figure Description
[0015] Figure 1 This is a schematic diagram of a test PAD for a high-end HDI circuit board test structure provided by this utility model.
[0016] Figure 2 This is a schematic diagram of the circuit board for embodiments 1 and 2 of this utility model.
[0017] Figure 3 This is a schematic diagram of the circuit board of Embodiment 3 of this utility model.
[0018] The image includes:
[0019] Circuit board 1, test PAD 2, test through hole 21, test blind hole 22. Detailed Implementation
[0020] To facilitate understanding of this utility model by those skilled in the art, the present utility model will be further described in detail below with reference to specific embodiments and accompanying drawings.
[0021] Example 1
[0022] Reference Figure 1-2This utility model provides a high-order HDI circuit board test structure, including a circuit board. A test PAD is disposed outside the effective area of the circuit board. The test PAD includes a test through-hole, and a plurality of test blind vias are disposed around the test through-hole. There is a gap between the test through-hole and the test blind vias. The diameter of the test through-hole is equal to the diameter of the smallest through-hole in the circuit board, and the diameter of the test blind via is equal to the diameter of the smallest blind via in the circuit board.
[0023] The spacing between the through holes and blind holes is 0.05mm to 0.0635mm. In this embodiment, the detection position of the through holes and blind holes is 0.05mm, i.e. 2mil. The minimum ring length of the blind holes in the effective area of the circuit board is 2.5mil. Setting the spacing to 0.05mm can ensure that there is still a ring within 2mil of the offset.
[0024] In this embodiment, the diameter of the coverage area of the test PAD is 1mm, and the distance between the test PAD and the edge of the effective area of the circuit board is greater than 5mm, for example, it can be 5.5mm.
[0025] In this embodiment, four test PADs are provided, each positioned at one of the four corners of the circuit board. Using four test PADs allows for verification of the alignment accuracy of through-holes and blind vias in four different areas, ensuring the accuracy of the test results.
[0026] Example 2
[0027] Reference Figure 1-2 This utility model provides a high-order HDI circuit board test structure, including a circuit board. A test PAD is disposed outside the effective area of the circuit board. The test PAD includes a test through-hole, and a plurality of test blind vias are disposed around the test through-hole. There is a gap between the test through-hole and the test blind vias. The diameter of the test through-hole is equal to the diameter of the smallest through-hole in the circuit board, and the diameter of the test blind via is equal to the diameter of the smallest blind via in the circuit board.
[0028] The spacing between the through holes and blind holes is 0.05mm to 0.0635mm. In this embodiment, the detection position of the through holes and blind holes is 0.05mm, i.e. 2mil. The minimum ring length of the blind holes in the effective area of the circuit board is 2.5mil. Setting the spacing to 0.05mm can ensure that there is still a ring within 2mil of the offset.
[0029] In this embodiment, the diameter of the coverage area of the test PAD is 1mm, and the distance between the test PAD and the edge of the effective area of the circuit board is greater than 5mm, for example, it can be 5.5mm.
[0030] In this embodiment, four test PADs are provided, each positioned at one of the four corners of the circuit board. Using four test PADs allows for verification of the alignment accuracy of through-holes and blind vias in four different areas, ensuring the accuracy of the test results.
[0031] The test blind vias are arranged in a circular array with the center of the test through-hole as the reference. In this embodiment, eight test blind vias are provided, distributed in eight different directions, avoiding the problem of a single direction affecting the test results and ensuring the accuracy of the test results. Of course, in specific implementations, the number of test blind vias is not limited to eight, and can be adaptively set according to the specific order of the circuit board and the circuit design.
[0032] Example 3
[0033] Reference Figure 1 , Figure 3 This utility model provides a high-end HDI circuit board test structure, including a circuit board, a test PAD is provided outside the effective area of the circuit board, the test PAD includes a test through hole, and a plurality of test blind holes are provided around the test through hole, with a gap between the test through hole and the test blind hole; the diameter of the test through hole is equal to the diameter of the smallest through hole in the circuit board, and the diameter of the test blind hole is equal to the diameter of the smallest blind hole in the circuit board.
[0034] The spacing between the through holes and blind holes is 0.05mm to 0.0635mm. In this embodiment, the detection position of the through holes and blind holes is 0.05mm, i.e. 2mil. The minimum ring length of the blind holes in the effective area of the circuit board is 2.5mil. Setting the spacing to 0.05mm can ensure that there is still a ring within 2mil of the offset.
[0035] In this embodiment, the diameter of the coverage area of the test PAD is 1mm, and the distance between the test PAD and the edge of the effective area of the circuit board is greater than 5mm, for example, it can be 5.5mm.
[0036] In this embodiment, four test PADs are provided, each positioned at one of the four edges of the circuit board. Using four test PADs allows for verification of the alignment accuracy of vias and blind vias in four different areas, ensuring the accuracy of the test results. However, in practice, the number of test PADs is not limited to four; additional numbers can be used depending on the specific circuit board design and circuit level. Furthermore, test PADs can be simultaneously positioned at the four corners and four edges of the circuit board.
[0037] The test blind vias are arranged in a circular array with the center of the test through-hole as the reference. In this embodiment, eight test blind vias are provided, distributed in different directions, avoiding the problem of a single direction affecting the test results and ensuring the accuracy of the test results. Of course, in specific implementations, the number of test blind vias is not limited to eight, and can be adaptively set according to the specific order of the circuit board and the circuit design.
[0038] This invention features a test PAD outside the effective area of the circuit board. The test PAD includes test through-holes and several test blind holes surrounding the through-holes. The diameter of the test through-holes is the same as the minimum diameter of the through-holes on the circuit board, and the diameter of the test blind holes is the same as the minimum diameter of the blind holes on the circuit board. This allows for rapid determination of hole misalignment during AOI testing without destructive testing or increased material costs. Furthermore, the blind holes surrounding the through-holes are positioned in different directions, allowing for the assessment of misalignment in different directions and ensuring the accuracy of the test results.
[0039] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this utility model, "a plurality of" means two or more, unless otherwise explicitly specified.
[0040] In this utility model, unless otherwise explicitly specified and limited, the terms "connection," "fixed," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.
[0041] Although the description of this utility model has been given in conjunction with the specific embodiments described above, it is obvious to those skilled in the art that many substitutions, modifications, and variations can be made based on the above description. Therefore, all such substitutions, modifications, and variations are included within the scope of the appended claims.
Claims
1. A high-end HDI circuit board test structure, comprising a circuit board, characterized in that, A test PAD is provided outside the effective area of the circuit board. The test PAD includes a test through hole and a plurality of test blind holes are provided around the test through hole. There is a gap between the test through hole and the test blind hole. The diameter of the test through hole is equal to the diameter of the smallest through hole in the circuit board, and the diameter of the test blind hole is equal to the diameter of the smallest blind hole in the circuit board.
2. The high-order HDI circuit board test structure according to claim 1, characterized in that, The spacing between the through holes and blind holes is 0.05mm to 0.0635mm.
3. The high-order HDI circuit board test structure according to claim 2, characterized in that, There are four test PADs, which are respectively located at the four corners of the circuit board.
4. The high-order HDI circuit board test structure according to claim 1, characterized in that, There are four test PADs, which are respectively located on the four edges of the circuit board.
5. The high-order HDI circuit board test structure according to claim 1, characterized in that, The test PAD has a coverage area diameter of 1 mm.
6. The high-order HDI circuit board test structure according to claim 1, characterized in that, The test blind holes are arranged in a circular array with the center of the test through holes as the reference.
7. The high-order HDI circuit board test structure according to claim 1, characterized in that, There are 8 blind holes for testing.
8. The high-order HDI circuit board test structure according to claim 7, characterized in that, The distance between the test PAD and the edge of the effective area of the circuit board is greater than 5mm.