Storage battery effectiveness detection device

Abstract

The utility model provides a storage battery effectiveness detection device, and belongs to the field of storage battery detection. The storage battery effectiveness detection device comprises a power supply switching circuit, a voltage detection circuit, a first selection circuit, a battery capacity detection circuit and a processor, the first end of the power switching circuit is connected with the anode of the DC bus, the second end of the power switching circuit is connected with the anode of the storage battery pack, and the cathode of the storage battery pack is connected with the cathode of the DC bus; the first end of the voltage detection circuit is connected with the anode of the storage battery pack; the second end of the voltage detection circuit is connected with the processor; the selection end of the first selection circuit is used for selecting single batteries of the storage battery pack, the output end of the first selection circuit is connected with the processor, and the control end of the first selection circuit is connected with the processor. The utility model provides a storage battery effectiveness detection device to improve the precision of capacity detection of a single battery.

Description

Technical Field

[0001] This disclosure relates to the field of battery testing technology, and in particular to a battery effectiveness testing device. Background Technology

[0002] As the core equipment of a DC power supply system, the battery bank is the last line of defense to ensure the normal operation of electrical equipment. In emergencies such as AC power failure or charger malfunction, the battery bank will switch from backup power to primary power, becoming the sole power supplier for the DC system, providing power to important DC loads such as circuit breaker opening and closing mechanisms, disconnect switches, relay protection devices, and monitoring and control devices. Therefore, the effectiveness of the battery bank plays a crucial role in the safe operation of the substation, is an important guarantee for the safe and reliable operation of the substation, and is also related to the safety of the entire power grid.

[0003] A battery pack is composed of multiple individual cells. During manufacturing, it's impossible to guarantee that the individual cells have completely identical capacities. This inconsistency means that some cells will not be fully charged or discharged during the charging and discharging process, resulting in a capacity loss where the actual usable capacity of the battery pack is less than the sum of the capacities of all individual cells. This capacity loss worsens with usage time. Significant differences in capacity between individual cells degrade the performance of the battery pack, eventually leading to its failure. Therefore, regular capacity testing of individual cells is crucial. Current methods for testing individual cell capacity are complex and suffer from poor accuracy. Utility Model Content

[0004] This disclosure provides a battery effectiveness detection device to improve the accuracy of single-cell battery capacity detection.

[0005] This disclosure provides a battery effectiveness detection device, including: a power switching circuit, a voltage detection circuit, a first selection circuit, a battery capacity detection circuit, and a processor;

[0006] The first terminal of the power switching circuit is used to connect to the positive terminal of the DC bus, the second terminal of the power switching circuit is connected to the positive terminal of the battery pack, and the negative terminal of the battery pack is used to connect to the negative terminal of the DC bus.

[0007] The first terminal of the voltage detection circuit is connected to the positive terminal of the battery pack, and the second terminal of the voltage detection circuit is connected to the processor.

[0008] The selection terminal of the first selection circuit is used to select a single cell of the battery pack, the output terminal of the first selection circuit is connected to the processor, and the control terminal of the first selection circuit is connected to the processor.

[0009] In one exemplary embodiment of this disclosure, a control switch, a current detection circuit, a second selection circuit, and a load are also included.

[0010] The first terminal of the control switch is connected to the positive terminal of the battery pack, the control terminal of the control switch is connected to the processor, and the second terminal of the control switch is connected to the load.

[0011] The first terminal of the current detection circuit is connected to the second terminal of the control switch, and the second terminal of the current detection circuit is connected to the processor.

[0012] The control terminal of the second selection circuit is connected to the processor, and the selection terminal of the second selection circuit is connected to the load.

[0013] In one exemplary embodiment of this disclosure, a wireless communication circuit is also included;

[0014] The processor communicates with the terminal via the wireless communication circuit.

[0015] In one exemplary embodiment of this disclosure, the battery pack includes individual cells B1, B2, and B3.

[0016] The positive terminal of the single cell B1 is connected to the second terminal of the power switching circuit, the negative terminal of the single cell B1 is connected to the positive terminal of the single cell B2, the negative terminal of the single cell B2 is connected to the positive terminal of the single cell B3, and the negative terminal of the single cell B3 is grounded.

[0017] In one exemplary embodiment of this disclosure, the first selection circuit includes a first analog switch U1 and a second analog switch U2;

[0018] The first selection terminal of the first analog switch U1 is connected to the positive terminal of the single battery B1, the second selection terminal of the first analog switch U1 is connected to the negative terminal of the single battery B1, the third selection terminal of the first analog switch U1 is connected to the negative terminal of the single battery B2, the first control terminal and the second control terminal of the first analog switch U1 are both connected to the processor, and the output terminal of the first analog switch U1 is connected to the battery capacity detection circuit.

[0019] The first selection terminal of the second analog switch U2 is connected to the negative terminal of the single cell B1, the second selection terminal of the second analog switch U2 is connected to the negative terminal of the single cell B2, the third selection terminal of the second analog switch U2 is grounded, the first control terminal and the second control terminal of the second analog switch U2 are both connected to the processor, and the output terminal of the second analog switch U2 is connected to the battery capacity detection circuit.

[0020] In one exemplary embodiment of this disclosure, the battery capacity detection circuit includes resistors R2, R3, R1, amplifier U3, R4, R5, R6, and amplifier U4.

[0021] The first end of the resistor R2 is connected to the output terminal of the first analog switch U1, the second end of the resistor R2 is connected to the inverting input terminal of the amplifier U3, the non-inverting input terminal of the amplifier U3 is grounded through the resistor R3, the output terminal of the amplifier U3 is connected to the inverting input terminal of the amplifier U3 through the resistor R1, and the output terminal of the amplifier U3 is connected to the inverting input terminal of the amplifier U4 through the resistor R4.

[0022] The inverting input terminal of the amplifier U4 is connected to the output terminal of the second analog switch U2 through the resistor R5. The output terminal of the amplifier U4 is grounded through the resistor R6. The output terminal of the amplifier U4 is connected to the inverting input terminal of the amplifier U4 through the resistor R13. The output terminal of the amplifier U4 is connected to the processor.

[0023] In one exemplary embodiment of this disclosure, the battery capacity detection circuit further includes a resistor R7 and a capacitor C4;

[0024] The first end of the resistor R7 is connected to the output terminal of the amplifier U4, the second end of the resistor R7 is grounded through the capacitor C4, and the second end of the resistor R7 is connected to the processor.

[0025] In one exemplary embodiment of this disclosure, the second selection circuit includes relay K1, relay K2, transistor Q1, and transistor Q2;

[0026] The load includes resistors R8, R9, and R10;

[0027] The first end of the resistor R8 is connected to the second end of the control switch, the second end of the resistor R8 is connected to the first end of the resistor R10 through the resistor R9, and the second end of the resistor R10 is grounded.

[0028] The base of transistor Q1 is connected to the processor, the collector of transistor Q1 is connected to the VCC power supply, the emitter of transistor Q1 is connected to the first input terminal of relay K1, the second input terminal of relay K1 is grounded, the first terminal of relay K1 is connected to the first terminal of resistor R8, and the second terminal of relay K1 is connected to the second terminal of resistor R8.

[0029] The base of transistor Q2 is connected to the processor, the collector of transistor Q2 is connected to the VCC power supply, the emitter of transistor Q2 is connected to the first input terminal of relay K2, the second input terminal of relay K2 is grounded, the first terminal of relay K2 is connected to the second terminal of resistor R8, the second terminal of relay K2 is connected to the first terminal of resistor R10, and the second terminal of relay K1 is connected to the first terminal of relay K2.

[0030] The beneficial effects of the battery effectiveness detection device provided in this embodiment are as follows:

[0031] The voltage detection circuit monitors the voltage status of the battery pack in real time, providing crucial data for evaluating battery performance. The first selection circuit allows the processor to accurately select and detect individual cells within the battery pack, effectively identifying potential faults or performance degradation. The battery capacity detection circuit further enhances the depth of detection, helping to predict battery lifespan. The processor, as the core of the entire system, automates and intelligently performs the detection, significantly improving efficiency and accuracy. By comparing the capacity differences of individual cells, it assesses the overall performance of the battery pack and predicts potential faults, effectively preventing battery pack failure. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a schematic diagram of the structure of a battery effectiveness detection device provided in an embodiment of this disclosure;

[0034] Figure 2 This is a circuit diagram of an embodiment of a battery effectiveness detection device provided in this disclosure;

[0035] Figure 3 This is a circuit diagram of another embodiment of a battery effectiveness detection device provided in this disclosure. Detailed Implementation

[0036] To enable those skilled in the art to better understand this solution, the technical solutions in the embodiments of this solution will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this solution, not all of them. Based on the embodiments of this solution, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this solution.

[0037] The term "comprising" and any other variations thereof in the specification, claims, and accompanying drawings of this invention mean "including but not limited to," and are intended to cover a non-exclusive inclusion, not limited to the examples listed herein. Furthermore, the terms "first" and "second," etc., are used to distinguish different objects, not to describe a specific order.

[0038] The implementation of this disclosure will be described in detail below with reference to the specific accompanying drawings:

[0039] Figure 1 This is a schematic diagram of a battery effectiveness detection device provided in an embodiment of this disclosure. (Refer to...) Figure 1 The battery effectiveness detection device includes: a power switching circuit, a voltage detection circuit, a first selection circuit, a battery capacity detection circuit, and a processor; the first terminal of the power switching circuit is connected to the positive terminal of the DC bus, the second terminal of the power switching circuit is connected to the positive terminal of the battery pack, and the negative terminal of the battery pack is connected to the negative terminal of the DC bus; the first terminal of the voltage detection circuit is connected to the positive terminal of the battery pack, and the second terminal of the voltage detection circuit is connected to the processor; the selection terminal of the first selection circuit is used to select individual cells of the battery pack, the output terminal of the first selection circuit is connected to the processor, and the control terminal of the first selection circuit is connected to the processor.

[0040] In this embodiment, the main function of the power switching circuit is to control the connection status between the DC bus and the battery pack. When the DC bus is supplying power normally, the power switching circuit may disconnect the positive terminal of the DC bus from the positive terminal of the battery pack, putting the battery pack in standby mode. However, when the DC bus loses power or the charger malfunctions and stops operating, the power switching circuit will quickly connect the positive terminal of the battery pack to the positive terminal of the DC bus, turning the battery pack into the main power source to provide power to important DC loads.

[0041] A voltage detection circuit continuously monitors the total voltage of the battery pack. The first terminal of this circuit is connected to the positive terminal of the battery pack, and the second terminal is connected to the processor. The voltage detection circuit transmits the detected voltage signal to the processor, which can then use this signal to determine the overall voltage state of the battery pack and thus assess its health.

[0042] The first selection circuit is used to select specific individual cells in the battery pack for testing. Its selection terminal is controlled by the processor, which can issue instructions to select different individual cells. The signal from the selected individual cell is transmitted to the processor through the output of the first selection circuit. The battery capacity detection circuit is responsible for detecting the capacity of the selected individual cell. The battery capacity detection circuit transmits the detected capacity information to the processor.

[0043] The processor receives information from the voltage detection circuit and the battery capacity detection circuit, and assesses the health status of the battery pack and individual cells based on this information. The processor can also control a first selection circuit to select different individual cells for testing. Furthermore, the processor can evaluate the overall performance of the battery pack by comparing the capacity differences of individual cells and predict potential failures.

[0044] As can be seen from the above, the voltage detection circuit monitors the voltage state of the battery pack in real time, providing crucial data for evaluating battery performance. The first selection circuit allows the processor to accurately select and detect individual cells in the battery pack, effectively identifying potential faults or performance degradation issues. The battery capacity detection circuit further enhances the depth of detection, helping to predict battery lifespan. The processor, as the core of the entire system, automates and intelligently performs the detection, greatly improving efficiency and accuracy. By comparing the capacity differences of individual cells, it evaluates the overall performance of the battery pack and predicts potential faults, effectively preventing battery pack failure.

[0045] like Figure 1 As shown in the embodiments of this disclosure, a battery effectiveness detection device further includes a control switch, a current detection circuit, a second selection circuit, and a load; the first terminal of the control switch is connected to the positive terminal of the battery pack, the control terminal of the control switch is connected to the processor, and the second terminal of the control switch is connected to the load; the first terminal of the current detection circuit is connected to the second terminal of the control switch, and the second terminal of the current detection circuit is connected to the processor; the control terminal of the second selection circuit is connected to the processor, and the selection terminal of the second selection circuit is connected to the load.

[0046] In this embodiment, the control switch, under the control of the processor, controls the current path between the battery pack and the load. The load in this embodiment can be a resistor, used for discharging the battery. When a discharge test is required, the processor activates the control switch, allowing the battery pack to supply power to the load through the control switch. Simultaneously, the current detection circuit monitors the current flowing from the battery pack to the load in real time and transmits the detected current data to the processor. Furthermore, the second selection circuit, under the control of the processor, can select resistors of different resistance values, thereby enabling switching or disconnection of different loads. Under different load tests, the processor, based on the received voltage, current, and other data, combined with the results of the battery capacity detection circuit, comprehensively evaluates the effectiveness of the battery pack, providing users with accurate test results and corresponding maintenance suggestions.

[0047] The battery effectiveness testing device in this embodiment significantly improves the accuracy and flexibility of battery pack performance evaluation by integrating a control switch, current detection circuit, second selection circuit, and a load with switchable resistance values. The device can simulate actual discharge processes, using a processor to control loads with different resistance values ​​to perform diverse discharge tests on the battery pack. The current detection circuit monitors the discharge current in real time to ensure data accuracy. The processor combines voltage, current, and battery capacity detection data to perform a comprehensive evaluation of the battery pack, providing users with accurate test results and maintenance recommendations. This not only helps to promptly identify potential battery problems but also effectively extends its service life and improves the stability and reliability of the entire system.

[0048] like Figure 1 As shown in this embodiment, a battery effectiveness detection device further includes a wireless communication circuit; the processor communicates with the terminal through the wireless communication circuit.

[0049] In this embodiment, the battery effectiveness detection device of this disclosure has higher practicality and convenience. The wireless communication circuit enables the processor to communicate with a remote terminal, realizing remote transmission and real-time monitoring of the detection results. Users do not need to go to the site in person to check; they can obtain key data such as the voltage, current, and battery capacity of the battery pack, as well as the processor's evaluation results of the battery pack's effectiveness, through the terminal in real time. This not only greatly improves work efficiency but also reduces maintenance costs. In addition, the wireless communication circuit also enables remote monitoring and early warning of the battery. Once abnormal battery performance or impending failure is detected, the system can immediately send early warning information to the terminal through the wireless communication circuit, reminding the user to take timely maintenance measures to avoid potential safety hazards. Therefore, the addition of the wireless communication circuit further enhances the practicality and intelligence level of the battery effectiveness detection device.

[0050] like Figure 2As shown in the embodiment of this disclosure, the battery pack includes individual cells B1, B2, and B3; the positive terminal of individual cell B1 is connected to the second terminal of the power switching circuit, the negative terminal of individual cell B1 is connected to the positive terminal of individual cell B2, the negative terminal of individual cell B2 is connected to the positive terminal of individual cell B3, and the negative terminal of individual cell B3 is grounded.

[0051] In this embodiment, the battery pack can be composed of multiple individual cells connected in series and parallel. To facilitate understanding of the working principle of the subsequent circuit, the battery pack in this embodiment can be composed of three individual cells B1, B2, and B3 connected in series.

[0052] like Figure 2 As shown in this embodiment, the first selection circuit includes a first analog switch U1 and a second analog switch U2. The first selection terminal of the first analog switch U1 is connected to the positive terminal of the single battery B1, the second selection terminal of the first analog switch U1 is connected to the negative terminal of the single battery B1, the third selection terminal of the first analog switch U1 is connected to the negative terminal of the single battery B2, the first control terminal and the second control terminal of the first analog switch U1 are both connected to the processor, and the output terminal of the first analog switch U1 is connected to the battery capacity detection circuit. The first selection terminal of the second analog switch U2 is connected to the negative terminal of the single battery B1, the second selection terminal of the second analog switch U2 is connected to the negative terminal of the single battery B2, the third selection terminal of the second analog switch U2 is grounded, the first control terminal and the second control terminal of the second analog switch U2 are both connected to the processor, and the output terminal of the second analog switch U2 is connected to the battery capacity detection circuit.

[0053] In this embodiment, the first selection circuit includes a first analog switch U1 and a second analog switch U2. A multi-channel analog switch can be used as both the first analog switch U1 and the second analog switch U2. In this embodiment, two identical 4-to-1 analog switches are used as the first analog switch U1 and the second analog switch U2.

[0054] When it is necessary to detect the battery capacity of a single cell B1, the processor outputs two binary control signals, which are respectively applied to the two control terminals of the first analog switch U1 and the second analog switch U2. Assuming that when detecting the battery capacity of a single cell B1, the binary signals of the two control terminals of the first analog switch U1 are both 00, and the first selection terminal (NO2 pin) of the first analog switch U1 is active; similarly, the binary signals of the two control terminals of the second analog switch U2 are both 00, and the first selection terminal (NO2 pin) of the second analog switch U2 is active. Then, the voltages output by the first analog switch U1 and the second analog switch U2 are sent to the battery capacity detection circuit. The battery capacity detection circuit determines the battery capacity of a single cell B1 based on the magnitude of the voltages output by the first analog switch U1 and the second analog switch U2.

[0055] like Figure 2 As shown in this embodiment, the battery capacity detection circuit includes resistors R2, R3, and R1, amplifier U3, resistors R4, R5, and R6, and amplifier U4. The first end of resistor R2 is connected to the output of the first analog switch U1, the second end of resistor R2 is connected to the inverting input of amplifier U3, the non-inverting input of amplifier U3 is grounded through resistor R3, the output of amplifier U3 is connected to the inverting input of amplifier U3 through resistor R1, and the output of amplifier U3 is connected to the inverting input of amplifier U4 through resistor R4. The inverting input of amplifier U4 is connected to the output of the second analog switch U2 through resistor R5, the output of amplifier U4 is grounded through resistor R6, the output of amplifier U4 is connected to the inverting input of amplifier U4 through resistor R13, and the output of amplifier U4 is connected to the processor.

[0056] In this embodiment, when detecting the battery capacity of individual battery B1, the voltage at the output terminal of the first analog switch U1 is the total voltage of the battery pack, and the voltage at the output terminal of the second analog switch U2 is the total voltage of individual batteries B2 and B3 connected in series. Subtracting the voltage at the output terminal of the second analog switch U2 from the voltage at the output terminal of the first analog switch U1 gives the battery capacity of individual battery B1.

[0057] In this embodiment, assume the output voltage of the first analog switch U1 is V1, and the output voltage of the second analog switch U2 is V2. Amplifier U3 forms an inverting amplifier circuit, amplifying the output voltage of the first analog switch U1 inverted. The output voltage of amplifier U3 is V1. u31 ,

[0058] Amplifier U4 forms an inverting adder circuit, and the output voltage of amplifier U4 is V. u41 V u41 This indicates the battery capacity of a single cell, B1, in V. u41 The calculation formula is:

[0059] V u41 =V u31 -V2

[0060] Finally, the voltage output by amplifier U4 is sent to the processor, which determines the battery capacity of individual cell B1 based on the magnitude of the voltage output by amplifier U4.

[0061] like Figure 2 As shown in the embodiment of this disclosure, the battery capacity detection circuit further includes a resistor R7 and a capacitor C4; the first end of the resistor R7 is connected to the output terminal of the amplifier U4, the second end of the resistor R7 is grounded through the capacitor C4, and the second end of the resistor R7 is connected to the processor.

[0062] In this embodiment, resistor R7 and capacitor C4 form a filter circuit to filter out interference signals in the output voltage signal of amplifier U4. Finally, the filtered voltage signal is sent to the processor, thereby improving the detection accuracy.

[0063] like Figure 3 As shown in this embodiment, the second selection circuit includes relays K1 and K2, transistors Q1 and Q2; the load includes resistors R8, R9, and R10; the first end of resistor R8 is connected to the second end of the control switch, the second end of resistor R8 is connected to the first end of resistor R10 through resistor R9, and the second end of resistor R10 is grounded; the base of transistor Q1 is connected to the processor, the collector of transistor Q1 is connected to the VCC power supply, the emitter of transistor Q1 is connected to the first input terminal of relay K1, the second input terminal of relay K1 is grounded, the first end of relay K1 is connected to the first end of resistor R8, and the second end of relay K1 is connected to the second end of resistor R8; the base of transistor Q2 is connected to the processor, the collector of transistor Q2 is connected to the VCC power supply, the emitter of transistor Q2 is connected to the first input terminal of relay K2, the second input terminal of relay K2 is grounded, the first end of relay K2 is connected to the second end of resistor R8, the second end of relay K2 is connected to the first end of resistor R10, and the second end of relay K1 is connected to the first end of relay K2.

[0064] In this embodiment, the load consists of resistors R8, R9, and R10. To conduct a reasonable effectiveness test on the battery pack, resistors with different resistance values ​​are connected. Then, the current detection circuit detects the magnitude of the current generated by the battery pack when different resistance values ​​are connected. The current detection circuit converts the current output by the battery pack into a voltage signal and sends it to the processor. The processor judges the overall effectiveness of the battery pack based on the magnitude of the voltage signal.

[0065] The processor controls the second selection circuit to select loads with different resistance values ​​to be connected to the test circuit. Assuming that only resistor R10 is connected, the processor outputs two high-level signals, which are applied to the bases of transistors Q1 and Q2 respectively. Both transistors Q1 and Q2 are turned on, and both relays K1 and K2 are energized and engaged. At this time, resistors R8 and R9 are short-circuited, and the electrical signal output from the second terminal of the control switch only passes through resistor R10.

[0066] Assuming that resistors R9 and R10 are connected simultaneously, the processor outputs a high-level signal to the base of transistor Q1, and simultaneously outputs a low-level signal to the base of transistor Q2. Transistor Q1 is turned on, relay K1 is energized and activated, transistor Q2 is turned off, relay K2 does not operate, therefore, resistor R8 is short-circuited, and the electrical signal output from the second terminal of the control switch passes through resistors R9 and R10 in sequence.

[0067] Assuming resistors R8, R9, and R10 are simultaneously connected, the processor outputs two low-level signals, which are applied to the bases of transistors Q1 and Q2 respectively. Both transistors Q1 and Q2 are cut off, and relays K1 and K2 do not operate. At this time, no resistors are short-circuited, and the electrical signal output from the second terminal of the control switch passes sequentially through resistors R8, R9, and R10. This allows for the connection of loads with different resistance values.

[0068] The above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit it. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A battery effectiveness testing device, characterized in that, include: Power switching circuit, voltage detection circuit, first selection circuit, battery capacity detection circuit, processor; The first terminal of the power switching circuit is used to connect to the positive terminal of the DC bus, the second terminal of the power switching circuit is connected to the positive terminal of the battery pack, and the negative terminal of the battery pack is used to connect to the negative terminal of the DC bus. The first terminal of the voltage detection circuit is connected to the positive terminal of the battery pack, and the second terminal of the voltage detection circuit is connected to the processor. The selection terminal of the first selection circuit is used to select a single cell of the battery pack, the output terminal of the first selection circuit is connected to the processor, and the control terminal of the first selection circuit is connected to the processor.

2. The battery effectiveness testing device as described in claim 1, characterized in that, It also includes a control switch, a current detection circuit, a second selection circuit, and a load; The first terminal of the control switch is connected to the positive terminal of the battery pack, the control terminal of the control switch is connected to the processor, and the second terminal of the control switch is connected to the load. The first terminal of the current detection circuit is connected to the second terminal of the control switch, and the second terminal of the current detection circuit is connected to the processor. The control terminal of the second selection circuit is connected to the processor, and the selection terminal of the second selection circuit is connected to the load.

3. The battery effectiveness testing device as described in claim 1, characterized in that, It also includes wireless communication circuits; The processor communicates with the terminal via the wireless communication circuit.

4. The battery effectiveness testing device as described in claim 1, characterized in that, The battery pack includes individual cells B1, B2 and B3. The positive terminal of the single cell B1 is connected to the second terminal of the power switching circuit, the negative terminal of the single cell B1 is connected to the positive terminal of the single cell B2, the negative terminal of the single cell B2 is connected to the positive terminal of the single cell B3, and the negative terminal of the single cell B3 is grounded.

5. The battery effectiveness testing device as described in claim 1, characterized in that, The first selection circuit includes a first analog switch U1 and a second analog switch U2; The first selection terminal of the first analog switch U1 is connected to the positive terminal of the single battery B1, the second selection terminal of the first analog switch U1 is connected to the negative terminal of the single battery B1, the third selection terminal of the first analog switch U1 is connected to the negative terminal of the single battery B2, the first control terminal and the second control terminal of the first analog switch U1 are both connected to the processor, and the output terminal of the first analog switch U1 is connected to the battery capacity detection circuit. The first selection terminal of the second analog switch U2 is connected to the negative terminal of the single cell B1, the second selection terminal of the second analog switch U2 is connected to the negative terminal of the single cell B2, the third selection terminal of the second analog switch U2 is grounded, the first control terminal and the second control terminal of the second analog switch U2 are both connected to the processor, and the output terminal of the second analog switch U2 is connected to the battery capacity detection circuit.

6. The battery effectiveness testing device as described in claim 5, characterized in that, The battery capacity detection circuit includes resistors R2, R3, R1, amplifier U3, R4, R5, R6, and amplifier U4. The first end of the resistor R2 is connected to the output terminal of the first analog switch U1, the second end of the resistor R2 is connected to the inverting input terminal of the amplifier U3, the non-inverting input terminal of the amplifier U3 is grounded through the resistor R3, the output terminal of the amplifier U3 is connected to the inverting input terminal of the amplifier U3 through the resistor R1, and the output terminal of the amplifier U3 is connected to the inverting input terminal of the amplifier U4 through the resistor R4. The inverting input terminal of the amplifier U4 is connected to the output terminal of the second analog switch U2 through the resistor R5. The output terminal of the amplifier U4 is grounded through the resistor R6. The output terminal of the amplifier U4 is connected to the inverting input terminal of the amplifier U4 through the resistor R13. The output terminal of the amplifier U4 is connected to the processor.

7. The battery effectiveness testing device as described in claim 6, characterized in that, The battery capacity detection circuit also includes a resistor R7 and a capacitor C4; The first end of the resistor R7 is connected to the output terminal of the amplifier U4, the second end of the resistor R7 is grounded through the capacitor C4, and the second end of the resistor R7 is connected to the processor.

8. The battery effectiveness testing device as described in claim 2, characterized in that, The second selection circuit includes relay K1, relay K2, transistor Q1, and transistor Q2; The load includes resistors R8, R9, and R10; The first end of the resistor R8 is connected to the second end of the control switch, the second end of the resistor R8 is connected to the first end of the resistor R10 through the resistor R9, and the second end of the resistor R10 is grounded. The base of transistor Q1 is connected to the processor, the collector of transistor Q1 is connected to the VCC power supply, the emitter of transistor Q1 is connected to the first input terminal of relay K1, the second input terminal of relay K1 is grounded, the first terminal of relay K1 is connected to the first terminal of resistor R8, and the second terminal of relay K1 is connected to the second terminal of resistor R8. The base of transistor Q2 is connected to the processor, the collector of transistor Q2 is connected to the VCC power supply, the emitter of transistor Q2 is connected to the first input terminal of relay K2, the second input terminal of relay K2 is grounded, the first terminal of relay K2 is connected to the second terminal of resistor R8, the second terminal of relay K2 is connected to the first terminal of resistor R10, and the second terminal of relay K1 is connected to the first terminal of relay K2.

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