Electronic circuit and device

Abstract

The utility model relates to an electronic circuit and a device. The electronic circuit includes: a first die including: a GaN transistor having a control node and a conductive node; a first node coupled to the conductive node; and a second node coupled to the control node; and a second die stacked with the first die and including elements electrically coupling the first node to the conductive node and electrically coupling the second node to the control node. In one embodiment, a device includes: a first die including: a first GaN transistor including a control node and a conductive node; and a first surface; a first conductive track coupled to the conductive node and exposed at the first surface; and a second conductive track coupled to the control node and exposed at the first surface; and a second die including: a second surface mounted to the first surface of the first die; and a third conductive track exposed at the second surface and electrically coupled to the first conductive track and the second conductive track.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to French patent application number 2310184 entitled “Circuitélectronique”, filed on September 26, 2023, which is hereby incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] This disclosure generally relates to electronic circuits and related methods. Background Technology

[0004] In the manufacture of electronic circuits, it is useful to test certain components of the circuit before it is fully completed or assembled with other circuits. Utility Model Content

[0005] Providing electronic circuits with components that can be tested during manufacturing would be beneficial, while also reducing manufacturing and design costs.

[0006] The embodiments of this disclosure overcome all or part of the disadvantages of known circuits.

[0007] One embodiment provides an electronic circuit including a first die and a second die having a GaN transistor, the first die and the second die being stacked such that elements of the second die are electrically connected to a first node and a second node of the first die, the first node and the second node being coupled to a conductive node and a control node of the GaN transistor, respectively.

[0008] One embodiment provides a method for manufacturing an electronic circuit, comprising:

[0009] A first die and a second die having GaN transistors are stacked such that the components of the second die are electrically connected to a first node and a second node of the first die, the first node and the second node being coupled to the conductive node and the control node of the GaN transistor, respectively.

[0010] According to an embodiment, an electronic circuit is provided, comprising: a first die including: a GaN transistor having a control node and a conductive node; a first node coupled to the conductive node; and a second node coupled to the control node; and a second die stacked with the first die and including elements electrically coupling the first node to the conductive node and the second node to the control node; wherein the elements of the second die include conductive tracks disposed on a first surface of the second die.

[0011] According to an embodiment, a method for manufacturing an electronic circuit is provided, comprising: stacking a first die and a second die, wherein the stacking includes: electrically coupling a first node of the first die to a conductive node of a GaN transistor of the first die using elements of the second die; and electrically coupling a second node of the first die to a control node of the GaN transistor using the elements; wherein the elements of the second die include conductive tracks disposed on a first surface of the second die.

[0012] According to an embodiment, the second die is a silicon-based die.

[0013] According to an embodiment, the second die includes at least one transistor.

[0014] According to the embodiment, the transistor of the second die is of the MOS type, and the GaN transistor of the first die is of the HEMT type.

[0015] According to an embodiment, the transistor of the second die has:

[0016] A first conductive node is connected via the element to a first node of the first die; and

[0017] The second conductive node is connected to the control node of the transistor in the first die via another component.

[0018] According to an embodiment, the electrical contact between the element of the second die and the first node and the second node of the first die is a weld or solder.

[0019] According to an embodiment, the second node of the first die is coupled to the control node of the GaN transistor via electronic components.

[0020] According to an embodiment, the electronic component may be active or passive.

[0021] According to an embodiment, the electronic component is configured to allow the establishment of an automatic operating point for the GaN transistor.

[0022] According to an embodiment, the electronic component is a resistor.

[0023] According to an embodiment, before stacking the first die and the second die, the first node and the second node of the first die are disconnected from each other.

[0024] According to an embodiment, testing of the electronic components is performed before stacking the first die and the second die.

[0025] In one embodiment, the electronic circuit includes a first die. The first die includes a GaN transistor having a control node and a conductive node. The first die includes a first node coupled to the conductive node and a second node coupled to the control node. The electronic circuit includes a second die stacked with the first die and includes elements for electrically coupling the first node to the conductive node and the second node to the control node.

[0026] In one embodiment, a method of manufacturing an electronic circuit includes stacking a first die and a second die. The stack includes using elements of the second die to electrically couple a first node of the first die to a conductive node of a GaN transistor on the first die, and using elements to electrically couple a second node of the first die to a control node of the GaN transistor.

[0027] In one embodiment, the device includes a first die. The first die includes: a first GaN transistor including a control node and a conductive node; a first surface; a first conductive track coupled to the conductive node and exposed at the first surface; and a second conductive track coupled to the control node and exposed at the first surface. The device also includes a second die. The second die includes a second surface mounted to the first surface of the first die and a third conductive track exposed at the second surface and electrically coupled to the first and second conductive tracks.

[0028] According to one aspect of this disclosure, an electronic circuit is provided, comprising: a first die including: a GaN transistor having a control node and a conductive node; a first node coupled to the conductive node; and a second node coupled to the control node; and a second die stacked with the first die and including elements for electrically coupling the first node to the conductive node and the second node to the control node.

[0029] According to an embodiment of the present disclosure, the elements of the second die include conductive tracks disposed on a first surface of the second die.

[0030] According to embodiments of this disclosure, the second die is a silicon-based die.

[0031] According to embodiments of this disclosure, the second die includes at least one transistor.

[0032] According to embodiments of this disclosure, the transistor of the second die is of the MOS type, and the GaN transistor of the first die is of the HEMT type.

[0033] According to an embodiment of the present disclosure, the transistor of the second die includes: a first conductive node connected to a first node of the first die via the element; and a second conductive node connected to a control node of the transistor of the first die via a second element.

[0034] According to embodiments of this disclosure, the electrical contact between the elements of the second die and the first and second nodes of the first die is a weld or solder.

[0035] According to embodiments of this disclosure, a second node of the first die is coupled to a control node of the GaN transistor via electronic components.

[0036] According to embodiments of this disclosure, the electronic component may be active or passive.

[0037] According to embodiments of this disclosure, the electronic component is configured to allow the establishment of an automatic operating point for the GaN transistor.

[0038] According to embodiments of this disclosure, the electronic component is a resistor.

[0039] According to another aspect of this disclosure, a method of manufacturing an electronic circuit is provided, comprising: stacking a first die and a second die, wherein the stacking comprises: electrically coupling a first node of the first die to a conductive node of a GaN transistor of the first die using elements of the second die; and electrically coupling a second node of the first die to a control node of the GaN transistor using the elements.

[0040] According to an embodiment of this disclosure, the first node and the second node of the first die are disconnected from each other before the first die and the second die are stacked.

[0041] According to an embodiment of this disclosure, after the stacking, a second node of the first die is coupled to a control node of the GaN transistor via electronic components.

[0042] According to embodiments of this disclosure, the method includes performing tests on the electronic components before stacking the first die and the second die.

[0043] According to another aspect of this disclosure, a device is provided, comprising: a first die including: a first GaN transistor including a control node and a conductive node; and a first surface; a first conductive track coupled to the conductive node and exposed at the first surface; and a second conductive track coupled to the control node and exposed at the first surface; and a second die including: a second surface mounted to the first surface of the first die; and a third conductive track exposed at the second surface and electrically coupled to the first conductive track and the second conductive track.

[0044] According to an embodiment of this disclosure, the second die includes a second transistor.

[0045] According to embodiments of this disclosure, the second transistor includes a conductive node electrically coupled to a third conductive track.

[0046] According to embodiments of this disclosure, the device includes an adhesive film located between a third conductive track and a first conductive track and a second conductive track.

[0047] According to an embodiment of the present disclosure, the first die includes a fourth conductive track coupled to a conductive node, wherein the fourth conductive track is exposed at a first surface and electrically coupled to a third conductive track. Attached Figure Description

[0048] The foregoing features and advantages, as well as other features and advantages, will be described in detail with reference to the accompanying drawings, in which:

[0049] Figure 1 A portion of the electronic circuit according to an embodiment is schematically illustrated;

[0050] Figure 2 The diagram shows Figure 1 A top view of the electronic circuit portion of an embodiment;

[0051] Figure 3 A top view of an embodiment of the electronic circuit is schematically illustrated;

[0052] Figure 4 schematically illustrated Figure 3 A cross-sectional view AA of the electronic circuit portion of the embodiment;

[0053] Figure 5 A schematic illustration of an embodiment Figure 3 Electronic circuits; and

[0054] Figure 6 The diagram shows Figure 3 The manufacturing method of electronic circuits. Detailed Implementation

[0055] Identical features in all figures are indicated by the same reference numerals. In particular, common structural and / or functional features in various embodiments may have the same reference numerals and may have the same structure, dimensions, and material properties.

[0056] For clarity, only detailed illustrations and descriptions are provided to aid in understanding the embodiments.

[0057] Unless otherwise stated, when referring to two elements connected together, it means that there is no direct connection between them except for the conductor, and when referring to two elements coupled together, it means that the two elements can be connected or they can be coupled via one or more other elements.

[0058] In the following description, when referring to terms that define absolute position (such as the terms "front", "back", "top", "bottom", "left", "right", etc.), or terms that define relative position (such as the terms "above", "below", "upper", "lower", etc.), or terms that define direction (such as the terms "horizontal", "vertical", etc.), reference is made to the orientation of the accompanying drawings unless otherwise stated.

[0059] Unless otherwise stated, the expressions “approximately,” “about,” “substantially,” and “about” indicate a plus or minus 10%, preferably a plus or minus 5%.

[0060] Figure 1 An electronic circuit 170 according to an embodiment is schematically illustrated.

[0061] More specifically, Figure 1 A first circuit of an electronic circuit 170 formed in a first die 100 is shown, which includes a GaN transistor 102. A first node N1 of the first die 100 is coupled to conductive nodes 142, 144 (e.g., source) of the GaN transistor 102. A second node N2 of the first die 100 is coupled to control nodes 130, 132 (e.g., gate) of the GaN transistor 102. The transistor 102 also includes another conductive node 110 (e.g., drain).

[0062] In the example shown, conductive nodes 142, 144 and control nodes 130, 132 each include two tracks; however, it is conceivable that they each have a single track.

[0063] In the example, GaN transistors are high electron mobility type (HEMT).

[0064] The term "GaN transistor" refers to a transistor whose substrate is a gallium nitride-based alloy (but other elements may also be incorporated into this basic alloy). This specifically includes transistors containing one or more heterojunctions formed from alloys such as AlGaN / InGaN, AlInAs / GaInAs, GaInAs / AlGaAs, and AlGaAs / AlGa.

[0065] In the illustrated example, the second node N2 of the first die 100 is coupled to the control node 132 of the GaN transistor via electronic component 120. In this example, electronic component 120 is configured to allow the establishment of an automatic operating point for the GaN transistor. In another example, electronic component 120 may be an active or passive component. Electronic component 120 is, for example, a resistor.

[0066] In the example shown, nodes N1 and N2 are disconnected; in other words, there is no direct connection. This allows for the performance of test measurements, such as to determine the physical parameters of component 120, such as its resistance, and / or the leakage current of the gate 132 of transistor 102.

[0067] Figure 2 The diagram shows Figure 1 A top view of a portion of the electronic circuit 170 in an embodiment. More specifically, Figure 2 A first die 100 is shown. In the illustrated example, the connection pads for the conductive nodes 110 (e.g., drains) of the GaN transistor 102 are arranged on the high portion of the die 100 in a rectangular form, for example, arranged inside and / or on top of the substrate 202 (e.g., made of GaN). Connection pads coupled to the tracks 130, 132 forming control nodes are arranged on the same surface of the substrate 202 opposite to the corners of the conductive nodes 110. Connection pads coupled to the tracks 142, 144 forming the sources of the transistor 102 are arranged, for example, inside and / or on top of the same surface of the substrate 202, and this is between the pads coupled to tracks 130 and 132. An electronic component 120 is located between the connection pads coupled to tracks 142, 144, which in this example is a resistor arranged on the same surface of the substrate 202. On the first die 100, the electronic component 120 is electrically insulated from the connection pads coupled to tracks 142, 144. In a manner not shown, electronic component 120 is coupled to tracks 130 and 132, for example, through vias and / or conductive tracks in substrate 202.

[0068] Figure 1 and Figure 2 The example allows for the measurement of one or more physical parameters, such as those of electronic component 120. However, in the event of a measurement or test, nodes N1 and N2 must be electrically connected, for example, to form a complete circuit. This is, for example, the case when a cascode structure is desired from the first die 100.

[0069] This connection can be formed by performing a wire bonding between nodes N1 and N2. However, this is expensive and can lead to reliability issues, as well as potentially introducing parasitics into the signal.

[0070] The described embodiment provides a second die as a supplement to the first die 100, which is stacked with the first die such that the components of the second die are electrically connected to a first node N1 and a second node N2 of the first die. This enables measurements to be performed on the first die (e.g., electronic component 120) and allows for the acquisition of complete circuits, such as cascode circuits, when forming assemblies using the second die. Another advantage is that the presence of parasitic elements of the "RLC" type is limited, as is the case with wire bonding. This further results in better stability during signal transitions and limits costs associated with solder joints and additional materials.

[0071] Figure 3 A top view of an embodiment of electronic circuit 370 is schematically illustrated.

[0072] Circuit 370 includes similar Figure 1 and Figure 2 The first die 100 and the second die 300 are described in the diagram. The first die and the second dies 100 and 300 are stacked. In one example, the second die 300 is a silicon- or semiconductor-based die. In another example, the second die 300 includes at least one circuit having a transistor.

[0073] In the illustrated example, a second die 300 is stacked on top of a first die. The second die 300 includes an element 350 disposed on a surface of the second die 300 facing a surface located at the front of the first die 100. The element 350 of the second die includes, for example, conductive tracks, which are, for example, metallic or made of heavily doped semiconductor. These conductive tracks are formed or connected to, for example, the drain, source, or gate of a transistor of the second die 300.

[0074] exist Figure 3 In the example, the transparency shows that the second die covers the connection pads coupled to tracks 142 and 144, as well as the electronic component 120.

[0075] In the example shown, component 350 partially covers the connection pads coupled to tracks 142, 144. In another example, component 350 completely covers these pads. Figure 1As shown, in one embodiment, the source of transistor 102 is divided into two portions 142 and 144, both of which are connected to node N1. Component 350 electrically connects the first node N1 and the second node N2 of the first die 100; in other words, component 350 electrically connects the source of transistor 102 to the second node N2, which itself is connected to electronic component 120. In an example where the source of transistor 102 is formed by a single conductive track, component 350 electrically connects that track to the second node N2, thereby electrically connecting the source of transistor 102 to the second node N2.

[0076] In one example, the electrical contact between the elements of the second die 300 and the first and second nodes N1, N2 of the first die is formed by welding or soldering. In another example, the electrical contact is formed via a die attachment adhesive film, which may contain, for example, silver and / or nickel, and / or copper and / or gold and / or palladium. In one embodiment, a heat treatment with or without applied pressure is also used to form the contact.

[0077] In contrast to wire connections that have a smaller contact surface area and are more fragile, Figure 3 The example makes it possible to increase the contact surface area between the first die and the second die to form a contact between nodes N1 and N2.

[0078] Figure 4 schematically illustrated Figure 3 The AA cross-sectional view shows a portion of the electronic circuitry in the embodiment. The AA cross-section cuts through the first die 100 and the second die 300 at the connection pads of source 142, 144 and the layers of electronic components 120 and element 350.

[0079] In the illustrated example, the pads of source 142, 144 are arranged on substrate 202 from the surface of the first die 100 facing the second die 300. Component 350 is arranged on substrate 402 of the second die 300 from the surface of the second die facing the first die. Component 350 partially covers the pads of source 142, 144 of transistor 102 of the first die 100 at node N1, which is distributed on the pads of source 142, 144. Component 350 also covers component 120 at node N2, which is distributed on the surface of component 120. This coverage, and possibly associated solder joints or solder, form electrical contacts between the sources 142, 144 of transistor 102 and the second node N2 connected to the gate of transistor 102.

[0080] In the example, element 350 is a portion of the conductive node (e.g., drain 340) of the transistor in the second die. This allows for limiting the connection length as much as possible.

[0081] Figure 5 A schematic illustration of an embodiment Figure 3 Electronic circuits.

[0082] In the example shown, the first die 100 includes... Figure 1 Similar to the circuit, element 350 of the second die 300 is part of the drain 340 of transistor 502 of the second die 300. In this example, transistor 502 of the second die 300 is of the MOS (Metal-Oxide-Semiconductor) type, and substrate 402 is silicon-based.

[0083] In the illustrated example, the source 542 of transistor 502 is coupled (preferably connected) to control nodes 130, 132 of the GaN transistor 102 of the first die 100. This connection is performed, for example, similar to the connection between the first node and the second nodes N1, N2. In this example, the source 542 of transistor 502 is connected to the substrate of transistor 502. The drain 340 of transistor 502 is connected to element 350, and thus also to nodes N1 and N2. Transistor 502 also includes a control node 530.

[0084] therefore, Figure 5 The example forms a common-source, common-gate circuit, in which the source 142, 144 of GaN transistor 102 is connected in series with the drain 340 of transistor 502, and the gate 130, 132 of transistor 102 is connected to the source 542 of transistor 502.

[0085] Figure 6 The diagram illustrates the manufacturing process. Figure 3 Methods for electronic circuits.

[0086] In the first step 600 (stacking GaN dies and MOS dies), the first die and the second dies 100, 300 are stacked, for example, to place the component 350 in front of the pads of the source 142, 144 and the surface of the electronic component 120. Nodes N1 and N2 are disconnected at this stage.

[0087] In the second step 602 (connecting the first and second nodes of the GaN die to the elements of the second die), nodes N1 and N2 of the first die 100 are electrically connected via elements 350 of the second die. This connection may be direct, or via solder or weldment and / or via alloy and / or by applying heat treatment and / or applying pressure.

[0088] Before step 600, nodes N1 and N2 are disconnected, allowing for testing of, for example, the resistance of component 120 and / or the leakage current of the gate of GaN transistor 102.

[0089] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations can be combined, and other variations will occur to those skilled in the art. In particular, in some embodiments, element 350 is formed from a plurality of points or conductive surfaces.

[0090] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variations is within the capabilities of those skilled in the art. Specifically, in one embodiment, element 350 is a conductive track, or it may also be implemented by a conductive or control node, or a control node of the rear gate of the transistor 502 of the second die 300. In one embodiment, element 350 may also be implemented by a portion of electronic components, such as, for example, nodes of diodes, nodes of inductors, or nodes of capacitive elements.

[0091] In the described example, the second die 300 is stacked on the first die 100. However, in one embodiment, the first die 100 is stacked on the second die 300.

[0092] In one embodiment, the electronic circuitry is implemented in automotive applications or in other applications that use electricity.

[0093] In one embodiment, the electronic circuit (370) includes a first die (100) having a GaN transistor (102) and a second die (300), the first die (100) and the second die (300) being stacked such that the elements (350) of the second die (300) are electrically connected to a first node (N1) and a second node (N2) of the first die (100), the first node (N1) and the second node (N2) being coupled to the conductive nodes (140, 142) and the control nodes (130, 132) of the GaN transistor (102), respectively.

[0094] In one embodiment, a method of manufacturing an electronic circuit (370) stacks a first die (100) having a GaN transistor (102) and a second die (300) such that the elements (350) of the second die (100) are electrically connected to a first node (N1) and a second node (N2) of the first die, the first node (N1) and the second node (N2) being coupled to the conductive nodes (142, 144) and the control nodes (130, 132) of the GaN transistor (102), respectively.

[0095] In one embodiment, an element (350) of the second die (300) includes a conductive track disposed on a first surface of the second die (300).

[0096] In one embodiment, the second die (300) is a silicon-based die.

[0097] In one embodiment, the second die (300) includes at least one transistor (502).

[0098] In one embodiment, the transistor (502) of the second die (300) is of the MOS type, and the GaN transistor (102) of the first die (100) is of the HEMT type.

[0099] In one embodiment, the transistor (502) of the second die (300) includes: a first conductive node (340) connected to a first node (N1) of the first die (100) via the element (350); and a second conductive node (542) connected to a control node (130, 132) of the transistor (102) of the first die (100) via another element.

[0100] In one embodiment, the electrical contact between the element (350) of the second die and the first and second nodes (N1, N2) of the first die (100) is a weld or solder.

[0101] In one embodiment, the second node (N2) of the first die is coupled to the control node of the GaN transistor (102) via an electronic component (120).

[0102] In one embodiment, the electronic component (120) is active or passive.

[0103] In one embodiment, the electronic component (120) is configured to allow the establishment of an automatic operating point for the GaN transistor (102).

[0104] In one embodiment, the electronic component (120) is a resistor.

[0105] In one embodiment, before stacking the first die and the second die (100, 300), the first node and the second node (N1, N2) of the first die (100) are disconnected from each other.

[0106] In one embodiment, the electronic component (350) is tested before the first die and the second die (100, 300) are stacked.

[0107] Based on the detailed description above, these and other modifications can be made to the embodiments. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full scope of the equivalents conferred by these claims. Therefore, the claims are not limited to the disclosure.

Claims

1. An electronic circuit, characterized in that, include: The first die includes: A GaN transistor with control nodes and conductive nodes; The first node coupled to the conductive node; and The second node coupled to the control node; and The second die, stacked with the first die, includes elements that electrically couple the first node to a conductive node and the second node to a control node.

2. The electronic circuit according to claim 1, characterized in that, The components of the second die include conductive tracks arranged on the first surface of the second die.

3. The electronic circuit according to claim 1, characterized in that, The second die is a silicon-based die.

4. The electronic circuit according to claim 1, characterized in that, The second die includes at least one transistor.

5. The electronic circuit according to claim 4, characterized in that, The transistor in the second die is of the MOS type, and the GaN transistor in the first die is of the HEMT type.

6. The electronic circuit according to claim 4, characterized in that, The transistors in the second die include: A first conductive node is connected via the element to a first node of the first die; and The second conductive node is connected to the control node of the transistor in the first die via a second element.

7. The electronic circuit according to claim 1, characterized in that, The electrical contact between the components of the second die and the first and second nodes of the first die is a welded part or solder.

8. The electronic circuit according to claim 1, characterized in that, The second node of the first die is coupled to the control node of the GaN transistor via electronic components.

9. The electronic circuit according to claim 8, characterized in that, The electronic components described therein may be active or passive.

10. The electronic circuit according to claim 8, characterized in that, The electronic components are configured to allow for the establishment of automatic operating points for GaN transistors.

11. The electronic circuit according to claim 8, characterized in that, The electronic component mentioned above is a resistor.

12. A device, characterized in that, include: The first die includes: A first GaN transistor, including a control node and a conductive node; and First surface; A first conductive track, coupled to a conductive node and exposed at a first surface; and A second conductive track, coupled to the control node and exposed at the first surface; and The second die includes: The second surface is mounted onto the first surface of the first die; and The third conductive track is exposed at the second surface and electrically coupled to the first and second conductive tracks.

13. The device according to claim 12, characterized in that, The second die includes a second transistor.

14. The device according to claim 13, characterized in that, The second transistor includes a conductive node electrically coupled to a third conductive track.

15. The device according to claim 12, characterized in that, It includes an adhesive film located between the third conductive track and the first and second conductive tracks.

16. The device according to claim 12, characterized in that, The first die includes a fourth conductive track coupled to a conductive node, wherein the fourth conductive track is exposed at a first surface and electrically coupled to a third conductive track.

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