Static var generator circuit

Abstract

The utility model discloses a static var generator circuit, which is characterized in that a bus voltage detector and an inverter bridge arm current detector are arranged in the static var generator circuit to measure the voltage of a positive bus capacitor, the voltage of a negative bus capacitor and the output current of a three-phase inverter bridge arm, and the capacitance value of the bus capacitor can be calculated according to the voltage of the positive bus capacitor, the voltage of the negative bus capacitor and the output current of the three-phase inverter bridge arm. And monitoring of the capacitance value of the bus capacitor is realized. In order to ensure the normal operation of the three-level static var generator, the voltage of a positive bus capacitor, the voltage of a negative bus capacitor and the output current of a three-phase inverter bridge arm generally need to be measured even if the capacitance value of the bus capacitor does not need to be monitored, so that the voltage of the positive bus capacitor and the voltage of the negative bus capacitor are not required to be measured. According to the static var generator circuit disclosed by the utility model, a current sensor of the bus capacitor is not additionally arranged, so that the capacitance value of the bus capacitor is monitored without increasing extra cost or increasing the risk of a system.

Description

Technical Field

[0001] This utility model relates to the field of static var generator technology, and in particular to a static var generator circuit. Background Technology

[0002] In current low-voltage electrical systems, three-level inverter circuits are the mainstream choice for static var generator (SVR) circuit topologies. However, it is worth noting that most SVRs do not have bus capacitance monitoring capabilities. Monitoring the bus capacitance is crucial for assessing capacitor degradation and determining its normal operating condition. Since directly measuring the capacitance of an operating capacitor is difficult, current technology typically relies on adding sensors to measure the capacitor current and combining this with data on capacitor voltage fluctuations to calculate the bus capacitance.

[0003] Current methods for measuring bus capacitance current using sensors have several drawbacks. First, this approach requires additional cost. Especially for three-level circuits, the difference between the positive and negative bus currents necessitates the installation of two sensors, further increasing costs. Second, these additional sensors need to be connected in series in the circuit, which not only increases the loop length between the power devices and the bus capacitance but may also introduce additional impedance. This increased impedance can lead to increased voltage stress on the power devices or trigger resonance between the bus capacitance and the parasitic capacitance of the power devices, thereby increasing the system's risk. Utility Model Content

[0004] The technical problem to be solved by this utility model is that, in the monitoring of bus capacitance value, the current solution of using sensors to measure bus capacitance current is costly and increases the risk of the system.

[0005] To solve the above-mentioned technical problems, this utility model discloses a static var generator circuit, the circuit comprising:

[0006] Positive bus capacitor, negative bus capacitor, A-phase inverter circuit, B-phase inverter circuit, C-phase inverter circuit, bus voltage detector, inverter bridge arm current detector, among which,

[0007] The positive bus of the DC system is connected to the first terminal of the positive bus capacitor and the first terminal of the A-phase inverter circuit; the negative bus of the DC system is connected to the first terminal of the negative bus capacitor and the first terminal of the C-phase inverter circuit; and the neutral bus of the DC system is connected to the first terminal of the B-phase inverter circuit.

[0008] The second terminal of the positive bus capacitor is connected to the second terminals of the A-phase inverter circuit, the B-phase inverter circuit, and the C-phase inverter circuit, and the second terminal of the negative bus capacitor is connected to the third terminal of the A-phase inverter circuit, the B-phase inverter circuit, and the C-phase inverter circuit.

[0009] The bus voltage detector is connected to the positive and negative buses of the DC system to detect the voltage of the positive and negative buses.

[0010] The inverter bridge arm current detector is connected to the A-phase inverter circuit, B-phase inverter circuit, and C-phase inverter circuit, and is used to detect the output current of the A-phase inverter circuit, B-phase inverter circuit, and C-phase inverter circuit.

[0011] In an optional embodiment, the A-phase inverter circuit includes:

[0012] First switching transistor, second switching transistor, third switching transistor, fourth switching transistor, first diode, second diode, third diode, fourth diode, fifth diode, sixth diode;

[0013] The second terminal of the positive bus capacitor is connected to the first terminal of the first switch and the first diode. The second terminal of the first switch and the first diode is connected to the first terminal of the second diode, the fifth diode, and the second switch. The second terminal of the fifth diode is connected to the first terminal of the positive bus capacitor, the negative bus capacitor, and the sixth diode. The second terminal of the fifth diode and the second switch is connected to the first terminal of the third switch and the third diode as the current output terminal. The second terminal of the sixth diode, the third switch, and the third diode is connected to the first terminal of the fourth switch and the fourth diode. The second terminal of the fourth switch and the fourth diode is connected to the second terminal of the negative bus capacitor.

[0014] In an optional embodiment, the A-phase inverter circuit includes:

[0015] First switching transistor, second switching transistor, third switching transistor, fourth switching transistor, first diode, second diode, third diode, fourth diode;

[0016] The second terminal of the positive bus capacitor is connected to the first terminal of the first switch and the first diode. The second terminal of the first switch and the first diode is connected to the first terminal of the second switch, the second diode, the fourth switch, and the fourth diode as the current output terminal. The second terminal of the fourth switch and the fourth diode is connected to the second terminal of the negative bus capacitor. The second terminal of the second switch and the second diode is connected to the first terminal of the third switch and the third diode. The second terminal of the third switch and the third diode is connected to the first terminal of the positive bus capacitor and the negative bus capacitor.

[0017] In an optional embodiment, the A-phase inverter circuit includes:

[0018] First switching transistor, second switching transistor, third switching transistor, fourth switching transistor, fifth switching transistor, sixth switching transistor, first diode, second diode, third diode, fourth diode, fifth diode, sixth diode;

[0019] The second terminal of the positive bus capacitor is connected to the first terminal of the first switch and the first diode. The second terminal of the first switch and the first diode is connected to the first terminal of the second switch, the second diode, the fifth switch, and the fifth diode. The second terminal of the second switch and the second diode is connected to the first terminal of the third switch and the third diode as a current output terminal. The second terminal of the fifth switch and the fifth diode is connected to the first terminal of the sixth switch and the sixth diode, the first terminal of the positive bus capacitor, and the first terminal of the negative bus capacitor. The second terminal of the third switch, the third diode, the sixth switch, and the sixth diode is connected to the first terminal of the fourth switch and the fourth diode. The second terminal of the fourth switch and the fourth diode is connected to the second terminal of the negative bus capacitor.

[0020] In an optional embodiment, the circuit further includes:

[0021] The filter circuit is connected to the fourth terminal of the A-phase inverter circuit, the B-phase inverter circuit, and the C-phase inverter circuit.

[0022] Compared with the prior art, the embodiments of this utility model have the following beneficial effects:

[0023] In this embodiment of the invention, by setting a bus voltage detector and an inverter arm current detector in the static var generator circuit, the voltage of the positive bus capacitor, the voltage of the negative bus capacitor, and the output current of the three-phase inverter arms are measured, and the capacitance value of the bus capacitor can be calculated accordingly, thus achieving monitoring of the bus capacitor value. Since a three-level static var generator generally requires measurement of the voltage of the positive bus capacitor, the voltage of the negative bus capacitor, and the output current of the three-phase inverter arms to ensure its normal operation, even if monitoring the bus capacitor value is not necessary, the static var generator circuit disclosed in this invention does not add an additional current sensor for the bus capacitor. This achieves monitoring of the bus capacitor value without increasing additional cost or system risk. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is an overall structural diagram of a static var generator circuit disclosed in an embodiment of this utility model;

[0026] Figure 2This is the first example of an inverter circuit in a static var generator circuit disclosed in this utility model embodiment;

[0027] Figure 3 This is a second example of an inverter circuit in a static var generator circuit disclosed in this utility model embodiment;

[0028] Figure 4 This is the third example of an inverter circuit in a static var generator circuit disclosed in this utility model embodiment. Detailed Implementation

[0029] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0030] The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this utility model are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, apparatus, product, or end that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or ends.

[0031] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the present invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0032] This utility model discloses a static var generator (SVA) circuit. By incorporating a bus voltage detector and an inverter arm current detector within the SVA circuit, it achieves the measurement of the positive bus capacitor voltage, the negative bus capacitor voltage, and the output current of the three-phase inverter arms. Based on this measurement, the capacitance value of the bus capacitor can be calculated, thus enabling monitoring of the bus capacitor value. Since a three-level SVA generator typically requires measurement of the positive bus capacitor voltage, the negative bus capacitor voltage, and the output current of the three-phase inverter arms to ensure normal operation, even if monitoring the bus capacitor value is not necessary, the SVA circuit disclosed in this utility model does not add an additional bus capacitor current sensor. This achieves bus capacitor value monitoring without incurring additional costs or increasing system risk. A detailed description follows.

[0033] Please see Figure 1 , Figure 1 This is an overall structural diagram of a static var generator circuit disclosed in an embodiment of this utility model. (See diagram below.) Figure 1 As shown, the static var generator circuit includes:

[0034] Positive bus capacitor C1, negative bus capacitor C2, A-phase inverter circuit, B-phase inverter circuit, C-phase inverter circuit, bus voltage detector (not shown), inverter bridge arm current detector (not shown), among which,

[0035] The positive bus of the DC system is connected to the first terminal of the positive bus capacitor C1 and the first terminal of the A-phase inverter circuit. The negative bus of the DC system is connected to the first terminal of the negative bus capacitor C2 and the first terminal of the C-phase inverter circuit. The neutral bus of the DC system is connected to the first terminal of the B-phase inverter circuit.

[0036] The second terminal of the positive bus capacitor C1 is connected to the second terminals of the A-phase inverter circuit, the B-phase inverter circuit, and the C-phase inverter circuit, and the second terminal of the negative bus capacitor C2 is connected to the third terminal of the A-phase inverter circuit, the B-phase inverter circuit, and the C-phase inverter circuit.

[0037] The bus voltage detector is connected to the positive and negative buses of the DC system to detect the voltage of the positive and negative buses.

[0038] The inverter bridge arm current detector is connected to the A-phase inverter circuit, B-phase inverter circuit, and C-phase inverter circuit, and is used to detect the output current of the A-phase inverter circuit, B-phase inverter circuit, and C-phase inverter circuit.

[0039] Figure 2 This is the first example of an inverter circuit in a static var generator circuit disclosed in this utility model embodiment.

[0040] like Figure 2As shown, the inverter circuit in a static var generator circuit may include:

[0041] First switch Q1, second switch Q2, third switch Q3, fourth switch Q4, first diode D1, second diode D2, third diode D3, fourth diode D4, fifth diode D5, sixth diode D6;

[0042] The second terminal of the positive bus capacitor C1 is connected to the first terminal of the first switch Q1 and the first diode D1. The second terminals of the first switch Q1 and the first diode D1 are connected to the first terminals of the second diode D2, the fifth diode D5, and the second switch Q2. The second terminal of the fifth diode D5 is connected to the first terminal of the positive bus capacitor C1, the negative bus capacitor C2, and the sixth diode D6. The second terminal of the fifth diode D5 and the second switch Q2 is connected to the first terminals of the third switch Q3 and the third diode D3 as the current output terminal. The second terminals of the sixth diode D6, the third switch Q3, and the third diode D3 are connected to the first terminals of the fourth switch Q4 and the fourth diode D4. The second terminal of the fourth switch Q4 and the fourth diode D4 is connected to the second terminal of the negative bus capacitor C2.

[0043] Figure 3 This is a second example of an inverter circuit in a static var generator circuit disclosed in this utility model embodiment.

[0044] like Figure 3 As shown, the inverter circuit in a static var generator circuit may include:

[0045] First switch Q1, second switch Q2, third switch Q3, fourth switch Q4, first diode D1, second diode D2, third diode D3, fourth diode D4;

[0046] The second terminal of the positive bus capacitor C1 is connected to the first terminal of the first switch Q1 and the first diode D1. The second terminal of the first switch Q1 and the first diode D1 is connected to the first terminal of the second switch Q2, the second diode D2, the fourth switch Q4, and the fourth diode D4 as the current output terminal. The second terminal of the fourth switch Q4 and the fourth diode D4 is connected to the second terminal of the negative bus capacitor C2. The second terminal of the second switch Q2 and the second diode D2 is connected to the first terminal of the third switch Q3 and the third diode D3. The second terminal of the third switch Q3 and the third diode D3 is connected to the first terminal of the positive bus capacitor C1 and the negative bus capacitor C2.

[0047] Figure 4 This is the third example of an inverter circuit in a static var generator circuit disclosed in this utility model embodiment.

[0048] like Figure 4 As shown, the inverter circuit in a static var generator circuit may include:

[0049] First switch Q1, second switch Q2, third switch Q3, fourth switch Q4, fifth switch Q5, sixth switch Q6, first diode D1, second diode D2, third diode D3, fourth diode D4, fifth diode D5, sixth diode D6;

[0050] The second terminal of the positive bus capacitor C1 is connected to the first terminal of the first switch Q1 and the first diode D1. The second terminal of the first switch Q1 and the first diode D1 is connected to the first terminal of the second switch Q2, the second diode D2, the fifth switch Q5, and the fifth diode D5. The second terminal of the second switch Q2 and the second diode D2 is connected to the first terminal of the third switch Q3 and the third diode D3 as the current output terminal. The second terminal of the fifth switch Q5 and the fifth diode D5 is connected to the first terminal of the sixth switch Q6 and the sixth diode D6, the positive bus capacitor C1, and the first terminal of the negative bus capacitor C2. The second terminal of the third switch Q3 and the third diode D3, the sixth switch Q6 and the sixth diode D6 is connected to the first terminal of the fourth switch Q4 and the fourth diode D4. The second terminal of the fourth switch Q4 and the fourth diode D4 is connected to the second terminal of the negative bus capacitor C2.

[0051] In an optional embodiment, the circuit further includes:

[0052] The filter circuit is connected to the fourth terminal of the A-phase inverter circuit, the B-phase inverter circuit, and the C-phase inverter circuit.

[0053] The output currents of the A-phase inverter circuit, B-phase inverter circuit, and C-phase inverter circuit are filtered by the filter circuit before being output.

[0054] The following explains the calculation principle of the bus capacitor value:

[0055] Regardless of which of the three inverter circuits mentioned above is used, there are corresponding three-level external transistors, namely the first switch Q1 and the fourth switch Q4. The duty cycles of the three-phase first switch Q1 are D1a, D1b, and D1c, respectively, and the duty cycles of the three-phase fourth switch Q4 are D4a, D4b, and D4c, respectively.

[0056] Multiplying the output current of each of the three phase bridge arms by the duty cycle of the first switching transistor Q1, we can obtain the current flowing from the positive bus capacitor C1 to the inverter bridge arm, which are Ia*D1a, Ib*D1b, and Ic*D1c, respectively. Their sum is the current value of the positive bus capacitor C1, Ic1=Ia*D1a+Ib*D1b+Ic*D1c.

[0057] Similarly, the current of the negative bus capacitor C2 can be obtained as Ic2=Ia*D4a+Ib*D4b+Ic*D4c.

[0058] Since the positive bus capacitor voltage Uc1 is constantly being measured, the effective value of the AC component of the voltage Uc1ac can be calculated using the sampled value of Uc1.

[0059] The capacitance value of the positive bus capacitor C1 can be calculated by C1 = Ic1 / Uc1ac * 2πf. For a three-phase inverter circuit, the bus voltage fluctuation is mainly three times the power frequency. Therefore, for a 50Hz inverter output, f is 150Hz.

[0060] Similarly, the capacitance value of the negative bus capacitor C2 can be calculated using C2 = Ic2 / Uc2ac * 2πf.

[0061] Using the above calculation method, the static var generator circuit disclosed in this utility model embodiment does not require additional cost or line impedance of the bus and power devices. It can use existing sampling data to calculate the bus capacitance value and determine whether the bus capacitance is still at a normal level.

[0062] As can be seen, the static var generator circuit disclosed in this utility model, by setting a bus voltage detector and an inverter arm current detector in the static var generator circuit, realizes the measurement of the positive bus capacitor voltage, the negative bus capacitor voltage, and the output current of the three-phase inverter arm, and can calculate the capacitance value of the bus capacitor accordingly, thus realizing the monitoring of the bus capacitor capacitance value. Since a three-level static var generator generally needs to measure the positive bus capacitor voltage, the negative bus capacitor voltage, and the output current of the three-phase inverter arm to ensure its normal operation, even if it is not necessary to monitor the bus capacitor capacitance value, it is generally necessary to measure the positive bus capacitor voltage, the negative bus capacitor voltage, and the output current of the three-phase inverter arm. Therefore, the static var generator circuit disclosed in this utility model does not add an additional bus capacitor current sensor, thus realizing the monitoring of the bus capacitor capacitance value without increasing additional costs or system risks.

Claims

1. A static var generator circuit, characterized in that, The circuit includes: Positive bus capacitor, negative bus capacitor, A-phase inverter circuit, B-phase inverter circuit, C-phase inverter circuit, bus voltage detector, inverter bridge arm current detector, among which, The positive bus of the DC system is connected to the first terminal of the positive bus capacitor and the first terminal of the A-phase inverter circuit; the negative bus of the DC system is connected to the first terminal of the negative bus capacitor and the first terminal of the C-phase inverter circuit; and the neutral bus of the DC system is connected to the first terminal of the B-phase inverter circuit. The second terminal of the positive bus capacitor is connected to the second terminals of the A-phase inverter circuit, the B-phase inverter circuit, and the C-phase inverter circuit, and the second terminal of the negative bus capacitor is connected to the third terminal of the A-phase inverter circuit, the B-phase inverter circuit, and the C-phase inverter circuit. The bus voltage detector is connected to the positive and negative buses of the DC system to detect the voltage of the positive and negative buses. The inverter bridge arm current detector is connected to the A-phase inverter circuit, B-phase inverter circuit, and C-phase inverter circuit, and is used to detect the output current of the A-phase inverter circuit, B-phase inverter circuit, and C-phase inverter circuit.

2. The static var generator circuit according to claim 1, characterized in that, Phase A inverter circuit includes: First switching transistor, second switching transistor, third switching transistor, fourth switching transistor, first diode, second diode, third diode, fourth diode, fifth diode, sixth diode; The second terminal of the positive bus capacitor is connected to the first terminal of the first switch and the first diode. The second terminal of the first switch and the first diode is connected to the first terminal of the second diode, the fifth diode, and the second switch. The second terminal of the fifth diode is connected to the first terminal of the positive bus capacitor, the negative bus capacitor, and the sixth diode. The second terminal of the fifth diode and the second switch is connected to the first terminal of the third switch and the third diode as the current output terminal. The second terminal of the sixth diode, the third switch, and the third diode is connected to the first terminal of the fourth switch and the fourth diode. The second terminal of the fourth switch and the fourth diode is connected to the second terminal of the negative bus capacitor.

3. The static var generator circuit according to claim 1, characterized in that, Phase A inverter circuit includes: First switching transistor, second switching transistor, third switching transistor, fourth switching transistor, first diode, second diode, third diode, fourth diode; The second terminal of the positive bus capacitor is connected to the first terminal of the first switch and the first diode. The second terminal of the first switch and the first diode is connected to the first terminal of the second switch, the second diode, the fourth switch, and the fourth diode as the current output terminal. The second terminal of the fourth switch and the fourth diode is connected to the second terminal of the negative bus capacitor. The second terminal of the second switch and the second diode is connected to the first terminal of the third switch and the third diode. The second terminal of the third switch and the third diode is connected to the first terminal of the positive bus capacitor and the negative bus capacitor.

4. The static var generator circuit according to claim 1, characterized in that, Phase A inverter circuit includes: First switching transistor, second switching transistor, third switching transistor, fourth switching transistor, fifth switching transistor, sixth switching transistor, first diode, second diode, third diode, fourth diode, fifth diode, sixth diode; The second terminal of the positive bus capacitor is connected to the first terminal of the first switch and the first diode. The second terminal of the first switch and the first diode is connected to the first terminal of the second switch, the second diode, the fifth switch, and the fifth diode. The second terminal of the second switch and the second diode is connected to the first terminal of the third switch and the third diode as a current output terminal. The second terminal of the fifth switch and the fifth diode is connected to the first terminal of the sixth switch and the sixth diode, the first terminal of the positive bus capacitor, and the first terminal of the negative bus capacitor. The second terminal of the third switch, the third diode, the sixth switch, and the sixth diode is connected to the first terminal of the fourth switch and the fourth diode. The second terminal of the fourth switch and the fourth diode is connected to the second terminal of the negative bus capacitor.

5. The static var generator circuit according to any one of claims 1-4, characterized in that, The circuit also includes: The filter circuit is connected to the fourth terminal of the A-phase inverter circuit, the B-phase inverter circuit, and the C-phase inverter circuit.

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