IRM digital chip high-speed test system
By designing a high-speed testing system for IRM digital chips and employing technologies such as USB 3.0 bus and attenuation circuits, the problem of insufficient signal processing capability in traditional testing methods is solved, achieving high-speed testing and improved stability of IRM digital chips.
Patent Information
- Application Number
- CN202520317156.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-26
- Publication Date
- 2025-12-05
- Estimated Expiration
- 2035-02-26
AI Technical Summary
Traditional IRM digital chip testing methods cannot adapt to the ever-changing signal requirements. They suffer from problems such as insufficient high-frequency signal processing capabilities, mismatched data acquisition rates, and resource contention, which limit their comprehensive evaluation in practical applications.
A high-speed testing system for IRM digital chips was designed, which uses a USB 3.0 bus as the data channel and combines an IRM communication protocol program editing module, a waveform output format configuration module, a data transceiver module, and an attenuation circuit to achieve high-speed test data transmission and improve stability.
High-speed testing of IRM digital chips has been achieved, improving the stability and flexibility of the testing system and ensuring testing speed and detection stability.
Smart Images
Figure CN223637667U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to electronic testing and measurement technical field especially relates to a kind of IRM digital chip high-speed test system. BACKGROUND
[0002] In modern lighting technology, IRM (Integrated Resource Management) digital chip is widely used in home, commercial and industrial lighting systems as the core component of intelligent LED lamp. Through digital signal control, IRM digital chip can accurately adjust the brightness, color and other characteristics of the lamp, so as to realize more efficient and flexible lighting management. This technology not only improves energy efficiency, but also provides users with a richer lighting experience. However, as the application of IRM digital chip becomes increasingly popular, the demand for its performance and reliability testing is increasing. Traditional testing methods often cannot adapt to changing signal requirements, facing challenges such as insufficient high-frequency signal processing capability, mismatched data acquisition rate and resource competition. These problems limit the comprehensive evaluation of IRM digital chip in practical applications.
[0003] Therefore, it is urgent to develop an efficient, flexible and modular test system to cope with the complexity and diversity of IRM digital chip in functional testing; provide an advanced testing solution for IRM digital chip to ensure its stability and reliability in practical applications. SUMMARY
[0004] The utility model overcomes the insufficient of prior art, provides a kind of IRM digital chip high-speed test system with good stability, high flexibility and fast test speed.
[0005] To achieve the above purpose, the utility model adopts the technical scheme: a kind of IRM digital chip high-speed test system, comprising: drive part, drive part is connected with hardware part by bus;Drive part includes: data transceiver module, data transceiver module is connected with hardware part by bus, IRM communication protocol program editing module and waveform output format configuration module are connected with data transceiver module by data packing module, and data transceiver module is further connected with IRM test result feedback module;
[0006] Hardware part includes: IRM digital chip, IRM digital chip is connected with bus by digital circuit and analog circuit, and power supply system is powered to digital circuit and analog circuit.
[0007] In a preferred embodiment of the utility model, the digital circuit comprises an instruction analysis module, the instruction analysis module is connected with the bus through an FX3 module, the instruction analysis module is connected with a control signal driving circuit, the control signal driving circuit is connected with an analog circuit, the instruction analysis module is also connected with the analog circuit through a DAC module one, a DAC module two, a DAC module three and an ADC module respectively.
[0008] In a preferred embodiment of the utility model, the analog circuit comprises a PWM module connected with the control signal driving circuit, an Input constant voltage source, an Input constant current source and an Output constant voltage source connected with the DAC module one, the DAC module two and the DAC module three respectively, and an attenuation circuit connected with the ADC module.
[0009] In a preferred embodiment of the utility model, an IRM communication protocol program editing module is used for editing the communication protocol program of the to-be-tested IRM product, the IRM communication protocol program editing module is connected with a data packaging module, and the data packaging module is connected with a data transceiving module.
[0010] In a preferred embodiment of the utility model, a waveform output format configuration module is used for configuring the program data programmed by the IRM communication protocol program editing module.
[0011] Specifically, the bus is a USB3.0 bus, and the transmission speed of the bus is greater than or equal to 120MB / s.
[0012] In a preferred embodiment of the utility model, the Input constant current source comprises an Input constant current source excitation circuit, and the Input constant current source excitation circuit comprises a first operational amplifier X1, a positive input end of the first operational amplifier X1 is connected with the DAC module one, an output end of the first operational amplifier X1 is connected with a base of a first transistor Q1 through a first resistor R1, a collector of the first transistor Q1 is connected with a power supply VCC through a third resistor RL, an emitter of the first transistor Q1 is grounded through a second resistor R2, a negative input end of the first operational amplifier X1 is connected with the emitter of the first transistor Q1, and the collector of the first transistor Q1 leads out a Vout signal; the Input constant current source excitation circuit provides a current for the to-be-tested IRM product.
[0013] The utility model discloses a preferable embodiment of one, and Output constant voltage source includes output constant voltage source excitation circuit, output constant voltage source excitation circuit, include: third triode Q3, and the first capacitor C1 and the eleventh resistance R11 that are provided in parallel are connected between the collector and the base of third triode Q3, and the collector of third triode Q3 is connected with power VCC, and the base of third triode Q3 is still connected with ground through the first diode D1 and the second diode D2 in series, and the emitter of third triode Q3 is connected with ground through the twelfth resistance R12, and the emitter of third triode Q3 leads out Vout signal.
[0014] The utility model discloses a preferable embodiment of one, and control signal drive circuit 14 and instruction analysis module 13 are including the DUT signal generation circuit and output channel selection circuit of electric connection respectively, and the DUT signal generation circuit includes: field programmable logic gate chip, and the output signal pin of field programmable logic gate chip is connected with output channel selection circuit respectively, and output channel selection circuit includes first digital chip U1, and first digital chip U1 is connected with field programmable logic gate chip, and first digital chip U1 output signal, and first chip U1 is 1: 8 single channel general FET bus switch digital chip, and first chip U1 is connected with DUT_OE signal pin, DUT_S0 signal pin, DUT_S1 signal pin, DUT_S2 signal pin in the FPGA output signal of control signal drive circuit 14, and the DUT_OE signal pin in the FPGA output signal of control signal drive circuit 14 is pulled up through thirteenth resistance R13, and the control end of first digital chip U1 is connected with second chip U2, and second chip U2 is direction control type voltage conversion chip, and the input power supply of second chip U2 is connected with VDD power supply, and the output power supply of second chip U2 is connected with VCC power supply.
[0015] The utility model discloses a preferable embodiment of one, and attenuation circuit includes second operational amplifier X2, and the negative input end of second operational amplifier X2 is connected with ground through third resistance R3, and the positive input end of second operational amplifier X2 is connected with IRM digital chip through fifth resistance R5, and the chip response signal of introduction, and the positive input end of second operational amplifier X2 is connected with ground through sixth resistance R6, and the output of second operational amplifier X2 is fed back to the negative input end of second operational amplifier X2 through fourth resistance R4, and the output of second operational amplifier X2 is also connected with ADC module.
[0016] In a preferred embodiment of the utility model, the power supply system comprises a voltage stabilizing circuit, and the voltage stabilizing circuit comprises: a third operational amplifier X3, a positive input end of the third operational amplifier X3 is connected with an adjusting end of an eleventh resistor VR1, two ends of the eleventh resistor VR1 are connected with a voltage reference in parallel, and one end of the eleventh resistor VR1 is grounded; a negative input end of the third operational amplifier X3 is connected with a series connection node of a seventh resistor R7 and an eighth resistor R8, another end of the eighth resistor R8 is grounded, another end of the seventh resistor R7 is connected with an emitter of a second transistor Q2, a collector of the second transistor Q2 is connected with an output end of the third operational amplifier X3, the emitter of the second transistor Q2 is further connected with a series connection of a ninth resistor R9 and a tenth resistor R10, a connection node of the ninth resistor R9 and the tenth resistor R10 is connected with a negative input end of a fourth operational amplifier X4, a positive input end of the fourth operational amplifier X4 is grounded, an output end of the fourth operational amplifier X4 is connected with a base of a third transistor Q3, an emitter of the third transistor Q3 is connected with the tenth resistor R10, a collector of the third transistor Q3 and a collector of the second transistor Q2 serve as an input end, and an emitter of the second transistor Q2 and an emitter of the third transistor Q3 serve as an output end.
[0017] Compared with the prior art, the utility model has the beneficial effects that:
[0018] The utility model discloses a kind of IRM digital chip high-speed test system with better stability, high flexibility, fast test speed.
[0019] 1, IRM communication protocol program editing module can be generated with waveform output format configuration module and cooperate multiple IRM protocol digital waveforms, and flexibility is better.
[0020] 2, bus is as the data channel of driving part and hardware part, to realize the high-speed upload and issue of test data, realizes the high-speed test of IRM digital chip.
[0021] 3, attenuation circuit is used to attenuate the digital signal voltage returned by IRM product under test to the voltage range suitable for ADC collection, improves the stability of test.
[0022] 4, power supply system uses voltage stabilizing circuit to improve the stability of power supply, further improve the detection stability and power supply stability of entire test system. DETAILED DESCRIPTION
[0023] The utility model is further described below in connection with the drawings and examples.
[0024] Figure 1 It is the system framework diagram of a kind of IRM digital chip high-speed test system of the utility model;
[0025] Figure 2 is the Input constant current source excitation circuit diagram of the IRM digital chip high-speed test system of the utility model,
[0026] Figure 3 is the attenuation circuit diagram of the IRM digital chip high-speed test system of the utility model,
[0027] Figure 4 is the voltage stabilizing circuit principle diagram of the IRM digital chip high-speed test system of the utility model,
[0028] Figure 5 is the Output constant voltage source excitation circuit principle diagram of the IRM digital chip high-speed test system of the utility model,
[0029] Figure 6 is the stable DUT signal generation circuit and output channel selection circuit principle diagram of the IRM digital chip high-speed test system of the utility model,
[0030] Wherein, 1-drive part, 10-digital circuit, 11-analog circuit, 12-FX3 module, 13-instruction analysis module, 14-control signal drive circuit, 15-PWM module, 16-DAC module one, 17-DAC module two, 18-DAC module three, 19-Input constant voltage source, 2-hardware part, 20-Input constant current source, 21-Output constant voltage source, 22-ADC module, 23-attenuation circuit, 24-IRM digital chip;
[0031] 3-IRM communication protocol programming module, 4-waveform output format configuration module, 5-data packaging module, 6-data transceiver module, 7-IRM test result feedback module, 8-bus, 9-power supply system. DETAILED DESCRIPTION
[0032] The utility model technical scheme will be explained in detail below by the drawings and specific embodiments, should understand the embodiment of the utility model and the specific features in the embodiment are the detailed explanation of the utility model technical scheme, and not the limitation of the utility model technical scheme, in the case of no conflict, the technical features in the embodiment of the utility model and the embodiment can be combined.
[0033] The term "and / or", just is the association relation of the association object, indicates that there can be three kinds of relations, for example, A and / or B, can indicate: exist A alone, exist A and B simultaneously, exist B alone these three cases.In addition, the character " / ", generally indicates that the front and rear association object is a kind of "or" relation. Embodiment one
[0034] As Figures 1-6As shown, the IRM digital chip high-speed test system comprises a driving part 1 connected with a hardware part 2 through a bus 8, and the hardware part 2 is in contact or interconnection with an IRM digital chip of an IRM product to be tested.
[0035] Specifically, the driving part 1 comprises a data transceiver module 6 connected with the hardware part 2 through the bus 8, an IRM communication protocol program editing module 3 and a waveform output format configuration module 4 connected with the data transceiver module 6 through a data packaging module 5, and the data transceiver module 6 is further connected with an IRM test result feedback module 7.
[0036] The IRM communication protocol program editing module 3 is used for editing a communication protocol program of the IRM product to be tested, and is connected with the data packaging module 5, and the data packaging module 5 is connected with the data transceiver module 6. Specifically, different IRM products have different communication protocol controls, such as NEC protocol and RC-6 protocol. The data transceiver module 6 is realized based on a CyUSB.dll dynamic link library file matched with CYUSB3014, and the data transceiver module 6 transmits data to an FX3 module 12 of a digital circuit 10 in the hardware part 2 through the USB3.0 bus 8.
[0037] The waveform output format configuration module 4 is used for configuring program data programmed by the IRM communication protocol program editing module 3. Specifically, the waveform output format configuration module 4 is used for controlling an output channel of the program data programmed by the IRM communication protocol program editing module 3, secondarily selecting output data from the program data, determining an output frequency of the program data, and determining a cycle of output of the program data. The IRM communication protocol program editing module 3 can generate digital waveforms of multiple IRM protocols in cooperation with the waveform output format configuration module 4, and has good flexibility.
[0038] The data packaging module 5 is used for receiving information of the IRM communication protocol program editing module 3 and the waveform output format configuration module 4 and packaging FX3 data format, and outputs data to the data transceiver module 6.
[0039] The data transceiver module 6 transmits data to the hardware part 2 in cooperation with the bus 8, the hardware part 2 performs a test operation of the IRM product to be tested, and outputs corresponding IRM test results.
[0040] The IRM test result feedback module 7 is used for receiving IRM test results fed back by the hardware part 2, and displays the IRM test results to a user for test result analysis.
[0041] The bus 8 is a USB3.0 bus, and the transmission speed of the bus 8 is greater than or equal to 120 MB / s. Specifically, in order to realize high-speed testing of the IRM digital chip, the bus 8 in the utility model selects USB3.0 as the data channel of the driving part 1 and the hardware part 2, so as to realize high-speed uploading and issuing of test data.
[0042] Specifically, the hardware part 2 comprises: an IRM digital chip 24, the IRM digital chip 24 is connected with the bus 8 through a digital circuit 10 and an analog circuit 11, and a power supply system 9 supplies power to the digital circuit 10 and the analog circuit 11.
[0043] The digital circuit 10 comprises an instruction analysis module 13, the instruction analysis module 13 is connected with the bus 8 through an FX3 module 12, the instruction analysis module 13 is connected with a control signal driving circuit 14, the control signal driving circuit 14 is connected with the analog circuit 11, and the instruction analysis module 13 is also connected with the analog circuit 11 through a DAC module one 16, a DAC module two 17, a DAC module three 18 and an ADC module 22 respectively.
[0044] The analog circuit 11 comprises a PWM module 15 connected with the control signal driving circuit 14, an Input constant voltage source 19, an Input constant current source 20 and an Output constant voltage source 21 connected with the DAC module one 16, the DAC module two 17 and the DAC module three 18 respectively, and an attenuation circuit 23 connected with the ADC module 22. Embodiment two
[0045] As shown in Figures 1-6 An IRM digital chip high-speed testing system, comprising: a driving part 1, the driving part 1 is connected with a hardware part 2 through a bus 8, and the hardware part 2 is in contact or interconnection with an IRM digital chip of a to-be-tested IRM product.
[0046] Specifically, the driving part 1 comprises: a data transceiver module 6, the data transceiver module 6 is connected with the hardware part 2 through the bus 8, an IRM communication protocol program editing module 3 and a waveform output format configuration module 4 are connected with the data transceiver module 6 through a data packing module 5, and the data transceiver module 6 is also connected with an IRM test result feedback module 7.
[0047] The IRM communication protocol programming module 3 is used for programming the communication protocol of the IRM product to be tested, and is connected with the data packaging module 5, and the data packaging module 5 is connected with the data transceiver module 6. Specifically, different IRM products have different communication protocol controls, such as NEC protocol and RC-6 protocol. The data transceiver module 6 is realized based on the CyUSB.dll dynamic link library file matched with the CYUSB3014, and the data transceiver module 6 and the bus 8 of the USB3.0 transmit data to the FX3 module 12 of the digital circuit 10 in the hardware part 2.
[0048] The waveform output format configuration module 4 is used for configuring the program data programmed by the IRM communication protocol programming module 3. Specifically, the waveform output format configuration module 4 is used for controlling the output channel of the program data programmed by the IRM communication protocol programming module 3, secondarily selecting the output data from the program data, determining the output frequency of the program data and the cycle of the output of the program data. The IRM communication protocol programming module 3 can generate multiple groups of digital waveforms of the IRM protocol in cooperation with the waveform output format configuration module 4, and has good flexibility.
[0049] The data packaging module 5 is used for receiving the information of the IRM communication protocol programming module 3 and the waveform output format configuration module 4 and packaging the FX3 data format, and outputs data to the data transceiver module 6.
[0050] The data transceiver module 6 cooperates with the bus 8 to transmit data to the hardware part 2, and the hardware part 2 executes the test operation of the IRM product to be tested and outputs the corresponding IRM test result.
[0051] The IRM test result feedback module 7 is used for receiving the IRM test result fed back by the hardware part 2 and showing the IRM test result to the user for test result analysis.
[0052] The bus 8 adopts the USB3.0 bus, and the transmission speed of the bus 8 is greater than or equal to 120MB / s. Specifically, in order to realize the high-speed test of the IRM digital chip, the bus 8 in the utility model selects the USB3.0 as the data channel of the driving part 1 and the hardware part 2, so as to realize the high-speed uploading and issuing of the test data.
[0053] Specifically, the hardware part 2 comprises: an IRM digital chip 24 connected with the bus 8 through the digital circuit 10 and the analog circuit 11, and the power supply system 9 supplies power to the digital circuit 10 and the analog circuit 11. The digital circuit 10 comprises an instruction analysis module 13 connected with the bus 8 through an FX3 module 12, the instruction analysis module 13 is connected with a control signal driving circuit 14, the control signal driving circuit 14 is connected with the analog circuit 11, and the instruction analysis module 13 is further connected with the analog circuit 11 through a DAC module one 16, a DAC module two 17, a DAC module three 18 and an ADC module 22 respectively. The analog circuit 11 comprises a PWM module 15 connected with the control signal driving circuit 14, an Input constant voltage source 19, an Input constant current source 20 and an Output constant voltage source 21 connected with the DAC module one 16, the DAC module two 17 and the DAC module three 18 respectively, and an attenuation circuit 23 connected with the ADC module 22.
[0054] The Input constant current source 20 comprises an Input constant current source excitation circuit, which comprises: a first operational amplifier X1, a positive input end of the first operational amplifier X1 is connected with the DAC module one 16, an output end of the first operational amplifier X1 is connected with a base of a first transistor Q1 through a first resistor R1, a collector of the first transistor Q1 is connected with a power supply VCC through a third resistor RL, an emitter of the first transistor Q1 is connected with the ground through a second resistor R2, a negative input end of the first operational amplifier X1 is connected with the emitter of the first transistor Q1, and the collector of the first transistor Q1 outputs a Vout signal; the Input constant current source excitation circuit provides current for an IRM product to be tested;
[0055] The Output constant voltage source 21 comprises an Output constant voltage source excitation circuit, which comprises a third triode Q3, a first capacitor C1 and an eleventh resistor R11 connected in parallel between the collector and the base of the third triode Q3, the collector of the third triode Q3 is connected to the power supply VCC, the base of the third triode Q3 is connected to the ground through the first diode D1 and the second diode D2 in series, the emitter of the third triode Q3 is connected to the ground through the twelfth resistor R12, and the emitter of the third triode Q3 outputs the Vout signal. More specifically, one end of the eleventh resistor R11 is connected to the VCC, the other end is connected to the first capacitor C1 and the forward end of the first diode D1, and the base of the third triode Q3 is connected to the other end of the eleventh resistor R11 and the forward end of the first diode D1; one end of the first capacitor C1 is connected to the VCC, and the other end is connected to the collector of the third triode Q3. The collector of the third triode Q3 is connected to the VCC and one end of the first capacitor C1, the emitter is connected to the twelfth resistor R12, and the base is connected to the first capacitor C1, the eleventh resistor R11 and the forward end of the first diode D1. The forward end of the first diode D1 is connected to the base of the third triode Q3 and the first capacitor C1, and the other end is connected to the forward end of the second diode D2. The forward end of the second diode D2 is connected to the negative end of the first diode D1, and the negative end is connected to the GND. One end of the twelfth resistor R12 is connected to the emitter of the third triode Q3, and the other end is connected to the GND.
[0056] The control signal driving circuit 14 and the instruction analysis module 13 respectively comprise a DUT signal generating circuit and an output channel selection circuit connected electrically; the DUT signal generating circuit comprises a field programmable logic gate chip, the output signal pins of the field programmable logic gate chip are connected with the output channel selection circuit, the output channel selection circuit comprises a first digital chip U1, the first digital chip U1 is connected with the field programmable logic gate chip, the first digital chip U1 outputs a signal, the first chip U1 is a 1:8 single-channel general FET bus switch digital chip, the first chip U1 is connected with the DUT_OE signal pin, the DUT_S0 signal pin, the DUT_S1 signal pin and the DUT_S2 signal pin in the FPGA output signal of the control signal driving circuit 14, the DUT_OE signal pin in the FPGA output signal of the control signal driving circuit 14 is pulled up through the thirteenth resistor R13; and the control end of the first digital chip U1 is connected with a second chip U2, and the second chip U2 is a direction control type voltage conversion chip, the input power supply of the second chip U2 is connected with the VDD power supply, and the output power supply of the second chip U2 is connected with the VCC power supply. Specifically, the field programmable logic gate chip XC7A35T-2FGG484C outputs signal pins DUT_OE, DUT_S0, DUT_S1, DUT_S2, DUT_S3, DUT_DATA and the output signal pins DUT_PIN1, DUT_PIN2, DUT_PIN3, DUT_PIN4, DUT_PIN5, DUT_PIN6, DUT_PIN7, DUT_PIN8 of the first digital chip U1, and the thirteenth resistor R13, the first chip U1 and the second chip U2. Further, one end of the thirteenth resistor R13 is connected with the VCC, and the other end is connected with the field programmable logic gate chip XC7A35T-2FGG484C output signal pin DUT_OE signal, for pulling up the DUT_OE signal. The first chip U1 is a 1:8 single-channel general FET bus switch digital chip, which is controlled by the FPGA output signals DUT_OE, DUT_S0, DUT_S1, DUT_S2. The DUT_OE is pulled up through the thirteenth resistor R13. The second chip U2 is a direction control type voltage conversion chip, the input power supply of the second chip U2 is connected with the VDD, the output power supply of the second chip U2 is connected with the VCC, and the output signal of the second chip U2 is connected with the signal input end of the first chip U1.
[0057] The attenuation circuit 23 comprises a second operational amplifier X2; the negative input end of the second operational amplifier X2 is connected to the ground through a third resistor R3; the positive input end of the second operational amplifier X2 is connected to the IRM digital chip 24 through a fifth resistor R5, and the introduced chip response signal is connected; the positive input end of the second operational amplifier X2 is connected to the ground through a sixth resistor R6, and the output end of the second operational amplifier X2 is fed back to the negative input end of the second operational amplifier X2 through a fourth resistor R4, and the output end of the second operational amplifier X2 is also connected to the ADC module 22. Specifically, one end of the third resistor R3 is connected to the negative input end of the second operational amplifier X2, and the other end is connected to one end of the fourth resistor R4, and the other end is grounded; one end of the fourth resistor R4 is connected to one end of the third resistor R3, and the other end is connected to the output end of the second operational amplifier X2; one end of the fifth resistor R5 is connected to the chip response signal, and the other end is connected to one end of the sixth resistor R6; one end of the sixth resistor R6 is connected to one end of the fifth resistor R5, and the other end is connected to the positive input end of the second operational amplifier X2; the negative input end of the second operational amplifier X2 is connected to one end of the third resistor R3 and one end of the fourth resistor R4, the positive input end is connected to one end of the fifth resistor R5 and one end of the sixth resistor R6, and the output end is connected to the ADC input, and the signal is transmitted into the ADC detection module; the attenuation circuit 23 is used for attenuating the digital signal voltage returned by the IRM product to be tested to a voltage range suitable for ADC collection.
[0058] The power supply system 9 comprises a voltage stabilizing circuit, which comprises a third operational amplifier X3, a positive input end of the third operational amplifier X3 being connected with an adjusting end of an eleventh resistor VR1, two ends of the eleventh resistor VR1 being connected with a voltage reference in parallel, and one end of the eleventh resistor VR1 being grounded; a negative input end of the third operational amplifier X3 being connected with a joint of a seventh resistor R7 and an eighth resistor R8, and the other end of the eighth resistor R8 being grounded, the other end of the seventh resistor R7 being connected with an emitter of a second transistor Q2, and a collector of the second transistor Q2 being connected with an output end of the third operational amplifier X3, the emitter of the second transistor Q2 further being connected with a ninth resistor R9 and a tenth resistor R10 connected in series, and a joint of the ninth resistor R9 and the tenth resistor R10 being connected with a negative input end of a fourth operational amplifier X4, a positive input end of the fourth operational amplifier X4 being grounded, an output end of the fourth operational amplifier X4 being connected with a base of a third transistor Q3, an emitter of the third transistor Q3 being connected with the tenth resistor R10, and the collector of the second transistor Q2 and the collector of the third transistor Q3 being input ends, and the emitter of the second transistor Q2 and the emitter of the third transistor Q3 being output ends. Specifically, one end of the seventh resistor R7 is connected with one end of the emitter of the second transistor Q2, and simultaneously connected with one end of the ninth resistor R9 and leads out a positive output voltage +Vo signal, and the other end is simultaneously connected with the negative input end of the third operational amplifier X3 and the eighth resistor R8; one end of the eighth resistor R8 is connected with one end of the seventh resistor R7, and simultaneously connected with the negative input end of the third operational amplifier X3, and the other end is grounded; one end of the ninth resistor R9 is connected with one end of the emitter of the second transistor Q2 and one end of the seventh resistor R7, and the other end is connected with one end of the tenth resistor R10 and the negative input end of the fourth operational amplifier X4; the tenth resistor R10 is connected with one end of the ninth resistor R9 and the negative input end of the fourth operational amplifier X4, and the other end is connected with one end of the emitter of the third transistor Q3 and leads out a negative output voltage -Vo signal; the eleventh resistor VR1 is an adjustable resistor, one end of which is connected with one end of the voltage reference, the other end of which is connected with the other end of the voltage reference and grounded, and an adjusting end of the resistance value is connected with the positive input end of the fourth operational amplifier X4; the base of the second transistor Q2 is connected with the output end of the fourth operational amplifier X4, one end of the collector of the second transistor Q2 is connected with a positive input voltage +Vi, and one end of the emitter of the second transistor Q2 is connected with one end of the seventh resistor R7 and one end of the ninth resistor R9 and leads out the positive output voltage +Vo signal. The base of the third transistor Q3 is connected with the output end of the fourth operational amplifier X4, one end of the emitter of the third transistor Q3 is connected with the tenth resistor R10 and leads out the negative output voltage -Vo signal, and the collector of the second transistor Q3 is connected with a negative input voltage -Vi.The negative input terminal of the third operational amplifier X3 is connected to one end of the seventh resistor R7 and one end of the eighth resistor R8, and the positive input terminal of the third operational amplifier X3 is connected to the resistance adjustment terminal of the eleventh resistor VR1. The output terminal of the third operational amplifier X3 is connected to the base of the second transistor Q2. The negative input terminal of the fourth operational amplifier X4 is connected to one end of the ninth resistor R9 and one end of the tenth resistor R10, the positive input terminal of the fourth operational amplifier X4 is grounded, and the output terminal of the fourth operational amplifier X4 is connected to the base of the third transistor Q3. The voltage regulator circuit provides power to the various components of the hardware section, including: the seventh resistor R7, the eighth resistor R8, the ninth resistor R9, the tenth resistor R10, the eleventh resistor VR1, the second transistor Q2, the third transistor Q3, the third operational amplifier X3, and the fourth operational amplifier X4.
[0059] Working principle:
[0060] like Figures 1-6 As shown, in actual operation, the IRM communication protocol program editing module 3 and the waveform output format configuration module 4 work together to generate digital waveform data that conforms to the IRM communication protocol. This data includes digital waveform data of protocols such as NEC type, RC-5 type, RC-6 type, RCMM type, and JVC type. After being processed by the data packaging module 5 and the FX3 data transceiver module 6, the data generated by the driver part is sent to the digital circuit 10 through the USB 3.0 bus 8.
[0061] The instruction parsing module 13 receives the data received by the FX3 module 12 and controls the PWM module 15 to generate the digital waveform required for IRM testing; the PWM module 15 sends the generated digital waveform to the digital input pin of the IRM under test; the attenuation circuit 23 and the ADC detection circuit are connected to the digital output pin of the digital chip 24 of the IRM under test, first attenuating the voltage waveform returned by the IRM digital chip 24, and then performing digital-to-analog conversion by the ADC detection circuit.
[0062] Based on the preferred embodiments of this utility model, and through the above description, those skilled in the art can make various changes and modifications without departing from the inventive concept. The technical scope of this invention is not limited to the contents of the specification, but must be determined according to the claims.
Claims
1. An IRM digital chip high speed test system, comprising: The drive part (1) is connected with the hardware part (2) through a bus (8); characterized in that, The drive part (1) comprises a data transceiver module (6) connected with the hardware part (2) through the bus (8), an IRM communication protocol programming module (3) and a waveform output format configuration module (4) connected with the data transceiver module (6) through a data packing module (5), and the data transceiver module (6) is further connected with an IRM test result feedback module (7); The hardware part (2) comprises an IRM digital chip (24) connected with the bus (8) through a digital circuit (10) and an analog circuit (11), and a power supply system (9) supplies power to the digital circuit (10) and the analog circuit (11).
2. The IRM digital chip high-speed test system of claim 1, wherein: The digital circuit (10) comprises an instruction analysis module (13) connected with the bus (8) through an FX3 module (12), the instruction analysis module (13) is connected with a control signal driving circuit (14), the control signal driving circuit (14) is connected with the analog circuit (11), and the instruction analysis module (13) is further connected with the analog circuit (11) through a DAC module one (16), a DAC module two (17), a DAC module three (18) and an ADC module (22) respectively.
3. The IRM digital chip high speed test system of claim 2, wherein: The analog circuit (11) comprises a PWM module (15) connected with the control signal driving circuit (14), an Input constant voltage source (19), an Input constant current source (20) and an Output constant voltage source (21) connected with the DAC module one (16), the DAC module two (17) and the DAC module three (18) respectively, and an attenuation circuit (23) connected with the ADC module (22).
4. The IRM digital chip high speed test system of claim 3, wherein: The IRM communication protocol programming module (3) is used for editing a communication protocol program of an IRM product to be tested, the IRM communication protocol programming module (3) is connected with the data packing module (5), and the data packing module (5) is connected with the data transceiver module (6).
5. The IRM digital chip high speed test system of claim 4, wherein: The waveform output format configuration module (4) is used for configuring program data programmed by the IRM communication protocol programming module (3).
6. The IRM digital chip high speed test system of claim 5, wherein: The Input constant current source (20) comprises an Input constant current source excitation circuit, the Input constant current source excitation circuit comprises a first operational amplifier X1, a positive input end of the first operational amplifier X1 is connected with the DAC module one (16), an output end of the first operational amplifier X1 is connected with a base of a first transistor Q1 through a first resistor R1, a collector of the first transistor Q1 is connected with a power supply VCC through a third resistor RL, an emitter of the first transistor Q1 is connected with the ground through a second resistor R2, a negative input end of the first operational amplifier X1 is connected with the emitter of the first transistor Q1, and the collector of the first transistor Q1 outputs a Vout signal; and the Input constant current source excitation circuit provides a current for an IRM product to be tested.
7. The IRM digital chip high speed test system of claim 6, wherein: The Output constant voltage source (21) includes an Output constant voltage source excitation circuit, the Output constant voltage source excitation circuit includes: a third transistor Q3, a first capacitor C1 and an eleventh resistor R11 are connected in parallel between the collector and the base of the third transistor Q3, the collector of the third transistor Q3 is connected to a power supply VCC, the base of the third transistor Q3 is also connected to ground through a first diode D1 and a second diode D2 in series, the emitter of the third transistor Q3 is connected to ground through a twelfth resistor R12, and the emitter of the third transistor Q3 outputs a Vout signal.
8. The IRM digital chip high speed test system of claim 7, wherein: The control signal driving circuit (14) and the instruction analysis module (13) respectively include a DUT signal generation circuit and an output channel selection circuit electrically connected; the DUT signal generation circuit includes a field programmable logic gate chip, output signal pins of the field programmable logic gate chip are connected with the output channel selection circuit, the output channel selection circuit includes a first digital chip U1, the first digital chip U1 is connected with the field programmable logic gate chip, the first digital chip U1 outputs a signal, the first digital chip U1 is a 1:8 single-channel general FET bus switch digital chip, the first digital chip U1 is connected with a DUT_OE signal pin, a DUT_S0 signal pin, a DUT_S1 signal pin and a DUT_S2 signal pin in the FPGA output signal of the control signal driving circuit (14), the DUT_OE signal pin in the FPGA output signal of the control signal driving circuit (14) is pulled up through a thirteenth resistor R13; and a control end of the first digital chip U1 is connected with a second chip U2, and the second chip U2 is a direction control type voltage conversion chip, an input power supply of the second chip U2 is connected with a VDD power supply, and an output power supply of the second chip U2 is connected with a VCC power supply.
9. The IRM digital chip high speed test system of claim 8, wherein: The attenuation circuit (23) includes a second operational amplifier X2; a negative input end of the second operational amplifier X2 is connected to ground through a third resistor R3; a positive input end of the second operational amplifier X2 is connected with an IRM digital chip (24) through a fifth resistor R5, and a chip response signal is introduced; the positive input end of the second operational amplifier X2 is connected to ground through a sixth resistor R6, an output end of the second operational amplifier X2 is fed back to the negative input end of the second operational amplifier X2 through a fourth resistor R4, and the output end of the second operational amplifier X2 is also connected with an ADC module (22).
10. The IRM digital chip high speed test system of claim 9, wherein: The power supply system (9) comprises a voltage stabilizing circuit, which comprises a third operational amplifier X3, a positive input end of the third operational amplifier X3 is connected with an adjusting end of an eleventh resistor VR1, two ends of the eleventh resistor VR1 are connected with a voltage reference in parallel, and one end of the eleventh resistor VR1 is grounded; a negative input end of the third operational amplifier X3 is connected with a series joint of a seventh resistor R7 and an eighth resistor R8, the other end of the eighth resistor R8 is grounded, the other end of the seventh resistor R7 is connected with an emitter of a second transistor Q2, a collector of the second transistor Q2 is connected with an output end of the third operational amplifier X3, the emitter of the second transistor Q2 is further connected with a ninth resistor R9 and a tenth resistor R10 in series, a series joint of the ninth resistor R9 and the tenth resistor R10 is connected with a negative input end of a fourth operational amplifier X4, a positive input end of the fourth operational amplifier X4 is grounded, an output end of the fourth operational amplifier X4 is connected with a base of a third transistor Q3, an emitter of the third transistor Q3 is connected with the tenth resistor R10, a collector of the third transistor Q3 and the collector of the second transistor Q2 are used as input ends, and the emitter of the second transistor Q2 and the emitter of the third transistor Q3 are used as output ends.