Joined assembly

Abstract

The embodiment of the utility model provides a jointed assembly. The jointed assembly comprises a first packaging structure and a second packaging structure, wherein the first packaging structure comprises a first metal bump structure and a first polymer joint layer laterally surrounding the first metal bump structure; a second package structure including a second metal bump structure and a second polymer bonding layer laterally surrounding the second metal bump structure; and a solder portion between the first metal bump structure and the second metal bump structure. Each solder portion is bonded to a respective one of the first metal bump structures and a respective one of the second metal bump structures, and the second polymer bonding layer is bonded to the first polymer bonding layer by polymer-to-polymer bonding, high density bump structures that provide strong and rigid bonding provide cost-effective and efficient bonding between package structures.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a bonded assembly, and more particularly, to a polymer hybrid bonded assembly. BACKGROUND

[0002] Advanced semiconductor packages require cost-effective and efficient high-density metal bonding structures to provide high mechanical strength and reliability. SUMMARY

[0003] Embodiments of the present application provide a bonded assembly including a first package structure, a second package structure, and a plurality of solder portions. The first package structure includes a plurality of first metal interconnect structures, a plurality of first metal bump structures electrically connected to the first metal interconnect structures, and a first polymer bonding layer laterally surrounding the first metal bump structures. The second package structure includes a plurality of second metal interconnect structures, a plurality of second metal bump structures electrically connected to the second metal interconnect structures, and a second polymer bonding layer laterally surrounding the second metal bump structures. Each of the solder portions is between the first metal bump structures and the second metal bump structures, each of the solder portions is bonded to a respective one of the first metal bump structures and a respective one of the second metal bump structures, each of the solder portions is laterally surrounded by the first polymer bonding layer and not in direct contact with the second polymer bonding layer, and the first polymer bonding layer is spaced apart from the second package structure by the second polymer bonding layer.

[0004] Embodiments of the present application provide a bonded assembly including a first package structure, a second package structure, and a plurality of solder portions. The first package structure includes a plurality of first metal interconnect structures, a plurality of first metal bump structures electrically connected to the first metal interconnect structures, and a first polymer bonding layer laterally surrounding the first metal bump structures. The second package structure includes a plurality of second metal interconnect structures, a plurality of second metal bump structures electrically connected to the second metal interconnect structures, and a second polymer bonding layer laterally surrounding the second metal bump structures. Each of the solder portions is between the first metal bump structures and the second metal bump structures, each of the solder portions is bonded to a respective one of the first metal bump structures and a respective one of the second metal bump structures, each of the solder portions is laterally surrounded by the first polymer bonding layer and not in direct contact with the second polymer bonding layer, and the first polymer bonding layer is spaced apart from the second package structure by the second polymer bonding layer.

[0005] Based on the above, the hybrid bonding method of embodiments of the present application can be used to provide cost-effective and efficient bonding between package structures using high-density bump structures that provide strong and rigid bonding.

[0006] In order to make the above features and advantages of embodiments of the present application more apparent, specific embodiments are described below in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a vertical cross-sectional view of an exemplary structure after attaching semiconductor dies and dummy dies to a first carrier wafer according to embodiments of the present disclosure.

[0008] Figure 2 is a vertical cross-sectional view of an exemplary structure after forming a first mold compound frame according to embodiments of the present disclosure.

[0009] Figure 3 is a vertical cross-sectional view of an exemplary structure after forming a first stage hybrid semiconductor package and attaching an interposer via structure according to embodiments of the present disclosure.

[0010] Figure 4 is a vertical cross-sectional view of an exemplary structure after attaching a first semiconductor substrate including proximal metal bump structures and proximal polymer bonding layers to a first stage hybrid semiconductor package according to embodiments of the present disclosure.

[0011] Figures 5A-5I shows sequential vertical cross-sectional views of an exemplary package structure that can be bonded using the hybrid bonding process of the present disclosure.

[0012] Figure 6 is a vertical cross-sectional view of an exemplary structure after forming a mold compound interposer matrix according to embodiments of the present disclosure.

[0013] Figure 7 is a vertical cross-sectional view of an exemplary structure after forming second redistribution intraconnects, second redistribution dielectric layers, distal metal bump structures, and distal polymer bonding layers according to embodiments of the present disclosure.

[0014] Figure 8 is a vertical cross-sectional view of an exemplary structure after attaching a second carrier wafer and separating the first carrier wafer according to embodiments of the present disclosure.

[0015] Figure 9 is a vertical cross-sectional view of an exemplary structure after separating the second carrier wafer and singulating a reconstituted wafer including a second stage hybrid package array into discrete hybrid packages according to embodiments of the present disclosure.

[0016] Figure 10 is a vertical cross-sectional view of a semiconductor interposer work-in-process that is within a wafer and that includes an array of semiconductor interposer work-in-process according to embodiments of the present disclosure.

[0017] Figure 11 is a vertical cross-sectional view of an assembly according to embodiments of the present disclosure, including a semiconductor interposer, a composite package, and two high bandwidth memory dies within a unit area of a wafer.

[0018] Figure 12 is a vertical cross-sectional view of an assembly according to embodiments of the present disclosure after forming a mold compound multi-die frame.

[0019] Figure 13 is a vertical cross-sectional view of an assembly according to embodiments of the present disclosure after thinning a backside of a wafer and singulating a reconstituted wafer into third stage composite packages.

[0020] Figure 14 is a vertical cross-sectional view of a first assembly of a third stage composite package and a package substrate according to embodiments of the present disclosure.

[0021] Figure 15 is a vertical cross-sectional view of a second assembly of a third stage composite package and a package substrate according to embodiments of the present disclosure.

[0022] Figure 16 is a vertical cross-sectional view of a third assembly of a third stage composite package and a package substrate according to embodiments of the present disclosure.

[0023] Figure 17 is a flowchart showing steps for forming a bonded assembly according to embodiments of the present disclosure.

[0024] BRIEF DESCRIPTION OF DRAWINGS

[0025] 44: first metal bump structure; 48, 698, 790: solder portion; 49: first polymer bonding layer; 49': first polymer material layer; 54: second metal bump structure; 59: second polymer bonding layer; 59': second polymer material layer; 100: first semiconductor interposer; 110: first semiconductor substrate; 111, 611: planar insulating layer; 120: first substrate through via (TSV) structure; 122: proximal redistribution line interconnect; 144: proximal metal bump structure; 148: first solder portion; 149: proximal polymer bonding layer; 150: first distal redistribution dielectric layer; 160: first distal redistribution line interconnect; 200: semiconductor die; 201: dummy die; 210: die semiconductor substrate; 220: semiconductor assembly; 222: metal interconnect structure; 224: die side bonding pad; 230: dielectric material layer; 290: semiconductor package; 300: die interposer assembly; 305: molded compound (MC) die frame / MC matrix; 330: fan-out redistribution dielectric layer; 335: molded compound interposer frame; 340: fan-out redistribution line interconnect; 344: distal metal bump structure; 348: second solder portion; 349: distal polymer bonding layer; 352: TSV structure; 354: metal bump structure; 359: polymer bonding layer; 370: second distal redistribution dielectric layer; 380: second distal redistribution line interconnect; 400: memory die; 410: memory layer; 420: substrate layer; 430: molded compound frame; 444: memory die metal bump structure; 448: third solder portion; 449: memory die polymer bonding layer; 500: combination; 505: molded compound multi-die frame; 510: interposer semiconductor substrate; 600: second semiconductor interposer; 600': semiconductor interposer semi-finished product; 620: second TSV structure; 654: silicon interposer metal bump structure; 659: silicon interposer polymer bonding layer; 670: backside redistribution dielectric layer; 680: backside redistribution line interconnect; 694: backside bump structure; 710: first carrier wafer; 711: first die attach film (DAF); 720: second carrier wafer; 721: second DAF; 792: die side underfill material portion; 800: package substrate; 801: carrier substrate / carrier wafer; 810: core substrate; 811, 861: adhesive layer; 820: core through via structure; 830: chip side surface level circuitry (SLC); 832: chip side insulating layer; 836: chip side wiring interconnect; 838: substrate bonding pad; 840: board side surface level circuitry (SLC); 842: board side insulating layer; 846: board side wiring interconnect; 848: board side bonding pad; 860: stabilization structure; 871: chip side integrated passive component; 872: board side integrated passive component; 890: underfill material portion; 898: solder ball;910: first encapsulation structure; 918: first metal interconnect structure; 920: second encapsulation structure; 928: second metal interconnect structure; 1710, 1720, 1730: steps; UA1, UA2: unit area. DETAILED DESCRIPTION

[0026] The following disclosure provides different embodiments or examples for implementing various features of the present disclosure. Specific examples of structures and arrangements are presented in order to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the scope of the present disclosure. For example, in the following description, a first feature formed "on" a second feature or formed "over" a second feature can include embodiments where the first feature is formed directly on the second feature, and embodiments where the first feature is formed indirectly on the second feature with additional features intervening between the first feature and the second feature. Additionally, the present disclosure can repeat component / stage numbering and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not serve as a limitation of the various embodiments and / or configurations.

[0027] Numerical ordinals such as "first," "second," "third," etc. are generally not intended to refer to a part of a noun to which the ordinal refers, but rather to the noun itself. Thus, in the present document, the same component can be referred to with different ordinals. Also, whenever a plurality of components or elements is presented in a figure, it is understood that the various figures can be numbered in any order. Thus, for each instance in which a plurality of components is present, the possibility of numbering the components in a different order is explicitly considered. Also, spatially relative terms such as "beneath", "below", "lower", "above", "upper" and the like can be used herein for ease of describing one component or feature to another component or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0028] Various embodiments disclosed herein are directed to a semiconductor component, and in particular to a chip-on-wafer-on-board (CoWoB) structure using spacer dies and a method of forming the same. A chip-on-wafer-on-substrate (CoWoS) structure using spacer dies and a method of forming the same, ) structures use fan-out packages that include a chip-on-wafer structure bonded to a package substrate. Thus, the package substrate serves as an intermediary structure between the fan-out package (i.e., the chip-on-wafer structure) and a printed circuit board. However, the manufacturing cost of the package substrate can be high, and die warpage during attachment to the package substrate can reduce yield.

[0029] According to one aspect of the present disclosure, a metal bump structure compatible with a polymer bonding layer is used to provide bonding between stacked package structures. An intermediate solder portion is used to bond the mating metal bump structures. A pair of polymer bonding layers are adhered to each other around an array of solder portions, providing polymer-to-polymer bonding in addition to solder-mediated bonding. The hybrid bonding approach of the present disclosure can be used to provide cost-effective and efficient bonding between package structures using high-density bump structures that provide strong and rigid bonding. Moreover, the polymer-to-polymer bonding provides additional bonding strength. Various embodiments of the present disclosure can be used to provide highly reliable bonding in package structures for high-performance mobile devices that can include various types of processors, such as accelerated processing units, central processing units, graphics processing units, and field programmable gate arrays, and / or can include various memory dies. Various aspects of embodiments of the present disclosure are now described with reference to the accompanying drawings.

[0030] Reference is made to Figure 1 FIG. 1 shows an exemplary structure according to embodiments of the present disclosure. The exemplary structure includes semiconductor dies 200 and optional dummy dies 201 that are attached to a top side of a first carrier wafer 710. The first carrier wafer 710 can include a transparent wafer, such as a glass wafer. The first carrier wafer 710 can include a two-dimensional array of unit areas UA1, such as a rectangular array of unit areas UA1. In this embodiment, multiple instances of the unit areas UA1 can repeat at a first pitch along a first horizontal direction and at a second pitch along a second horizontal direction. The shown portion of the exemplary structure corresponds to one area of a single unit area UA1. In general, a set of at least one semiconductor die 200 and optional at least one dummy die 201 can be attached to the first carrier wafer 710 within each unit area UA1. In one embodiment, a first die attachment film (DAF) 711 can be applied to a top surface of the first carrier wafer 710, and each set of at least one semiconductor die 200 and optional at least one dummy die 201 can be attached to the first DAF 711 by performing pick-and-place operations.

[0031] In general, each semiconductor die 200 can be any type of semiconductor die known in the art. For example, each of the at least one semiconductor die 200 in the unit area UA1 can include a system-on-chip (SoC) die, a logic die, a memory die, or any other type of semiconductor die. In an embodiment, the semiconductor die 200 can include a die semiconductor substrate 210, which can include a single crystalline semiconductor substrate, such as a single crystalline semiconductor substrate. A semiconductor component 220 can be formed on a top surface of the die semiconductor substrate 210. The semiconductor component 220 can include a field effect transistor, a resistor, a diode, a capacitor, an inductor, or any other type of semiconductor component known in the art.

[0032] A metal interconnect structure 222 can be formed within the dielectric material layer 230 and also above the semiconductor component 220. The metal interconnect structure 222 can be electrically connected to the semiconductor component 220 and can provide electrical interconnection for the semiconductor component 220. A die-side bond pad 224 (i.e., a bond pad formed on the semiconductor die 200) can be formed at the topmost layer of the dielectric material layer 230. In an embodiment, the semiconductor die 200 can be attached to the first carrier wafer 710 such that the die semiconductor substrate 210 is closer to the first carrier wafer 710 than the die-side bond pad 224. After each semiconductor die 200 is attached to the first carrier wafer 710, a planar horizontal surface of the die-side bond pad 224 can be physically exposed.

[0033] Although the present disclosure is described using an embodiment in which a single semiconductor die 200 and dummy die 201 are attached to the first carrier wafer 710 within each unit area UA1, embodiments in which two or more semiconductor dies 200 are attached to the first carrier wafer 710 are expressly contemplated herein. Additional embodiments in which no dummy die 201 is used or in which multiple dummy dies 201 are attached to the first carrier wafer 710 in each unit area UA1 are expressly contemplated herein.

[0034] Reference Figure 2An encapsulant such as a molding compound (MC) material can be applied to the gaps between adjacent pairs of dies (200, 201) that are bonded to the first carrier wafer 710. The MC material can include an epoxy-based compound that can be hardened (i.e., cured) to provide a dielectric material portion having sufficient rigidity and mechanical strength. The MC material can include an epoxy resin, a hardener, silica (as a filler material), and other additives. The MC material can be provided in a liquid form or a solid form depending on the viscosity and flowability. Liquid MC material generally provides better handleability, good flowability, fewer voids, better filling, and fewer flow marks. Solid MC material generally can provide less curing shrinkage, better isolation, and less die displacement. Higher filler content (e.g., 85% by weight) in the MC material can shorten the time in a mold, reduce mold shrinkage, and reduce mold warping. Uniform filler size distribution in the MC material can reduce flow marks and can enhance flowability.

[0035] The MC material can be cured at a curing temperature to form an MC matrix, which is referred to herein as a first MC matrix or a die-level MC matrix. The die-level MC matrix can be a continuous layer of material that extends across the entire first carrier wafer 710. Each portion of the die-level MC matrix within a cell region UA1 constitutes a first molding compound frame, which is referred to herein as a molding compound die frame 305 or MC die frame 305. Each MC die frame 305 laterally surrounds a group of at least one semiconductor die 200 and optionally at least one dummy die 201. A planarization process can be performed to remove portions of the MC material that overlie a horizontal plane including the topmost faces of the semiconductor dies 200. The top faces of the semiconductor dies 200 and the dummy dies 201 can be coplanar with the top face of the die-level MC matrix. The combination of the semiconductor dies 200, the optional dummy dies 201, and the die-level MC matrix 305 constitutes a reconstituted wafer. The reconstituted wafer can include a two-dimensional array of a plurality of reconstituted dies. Each reconstituted die can be located within a respective cell region UA1 and can include at least one semiconductor die 200, optionally at least one dummy die 201, and a molding compound die frame 305. The illustrated portion of the example structure corresponds to a cell region UA1, i.e., a region within the reconstituted wafer that includes a single repeating unit.

[0036] Reference is made to Figure 3Fan-out redistribution interconnects 340 formed within fan-out redistribution dielectric layers 330 can be formed over a reconstituted wafer comprising a two-dimensional array of reconstituted dies (e.g., 200, 201, 305). Fan-out redistribution dielectric layers 330 comprise a respective dielectric polymer material, such as polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (PBO). Other suitable dielectric polymer materials can also be used. Each fan-out redistribution dielectric layer 330 can be formed by spin-coating and drying of the respective dielectric polymer material. The thickness of each fan-out redistribution dielectric layer 330 can be in a range from 2 microns to 40 microns, such as from 4 microns to 20 microns. Each fan-out redistribution dielectric layer 330 can be patterned, such as by applying and patterning a respective photoresist layer thereover and by transferring the pattern of the photoresist layer to the fan-out redistribution dielectric layer 330 using an etching process, such as an anisotropic etching process. Subsequently, the photoresist layer can be removed, such as with ashing.

[0037] Each fan-out redistribution interconnect 340 can be formed by depositing a metal seed layer by sputtering, by applying a photoresist layer over the metal seed layer and patterning the photoresist layer to form an open pattern through the photoresist layer, by electroplating a metal fill material (e.g., copper, nickel, or a stack of copper and nickel), by removing the photoresist layer (e.g., by ashing), and by etching portions of the metal seed layer that are between portions of the electroplated metal fill material. The metal seed layer can comprise a stack of a titanium barrier layer and a copper seed layer. The titanium barrier layer can have a thickness in a range from 50 nm to 300 nm, and the copper seed layer can have a thickness in a range from 100 nm to 500 nm. The metal fill material for the fan-out redistribution interconnects 340 can comprise copper, nickel, or copper and nickel. The thickness of the metal fill material deposited for each fan-out redistribution interconnect 340 can be in a range from 2 microns to 40 microns, such as from 4 microns to 10 microns, although lesser or greater thicknesses can also be used.

[0038] The fan-out re-routes interconnects 340 at the topmost level can have a general shape of a metal pad with a maximum lateral size in a range of 5 microns to 50 microns, such as from 10 microns to 40 microns and / or from 15 microns to 30 microns, although smaller and larger maximum lateral sizes can also be used. The lateral size of the bottom end of the via portion of the fan-out re-routes interconnects 340 can be in a range of 2 microns to 10 microns, such as from 3 microns to 8 microns, although smaller and larger lateral sizes can also be used. The total number of levels of the fan-out re-routes interconnects 340 can be in a range of 1 to 20. The combination of the fan-out re-routes interconnects 340 and the fan-out re-routes dielectric layers 330 within each unit area UA1 forms a re-routes structure, which is referred to herein as a fan-out re-routes structure (e.g., 330, 340), which is used to provide for the formation of a fan-out bonding structure.

[0039] An array of metal bump structures can be formed at the topmost level of the fan-out re-routes structure (e.g., 330, 340) within each unit area UA1. The metal bump structures are referred to herein as fan-out metal bump structures 354 (i.e., metal bump structures that provide a fan-out configuration) or die-side metal bump structures 354 (i.e., metal bump structures that are provided on a side of a die structure). The combination of the reconstituted dies (e.g., 200, 201, 305), the fan-out re-routes structure (e.g., 330, 340), and the array of fan-out metal bump structures 354 forms a composite semiconductor package, which can be referred to as a fan-out semiconductor package 290. The fan-out semiconductor package 290 is also referred to as a first-stage composite semiconductor package. Thus, upon formation of the fan-out re-routes structure (e.g., 330, 340) and the fan-out metal bump structures 354, the reconstituted dies (e.g., 200, 201, 305) comprise a two-dimensional array of fan-out semiconductor packages 290. Each fan-out semiconductor package 290 is a package structure, i.e., a structure that includes at least one semiconductor die or interposer, which is assembled or can be subsequently assembled to form a composite structure that includes at least a semiconductor die. The illustrated portion of the example structure corresponds to a unit area UA1, i.e., an area within a reconstituted wafer that includes a single repeating unit.

[0040] The fan-out metal bump structures 354 are bump structures that can be subsequently used to electrically connect the fan-out semiconductor package 290 to another package structure. The metal fill material used for the fan-out metal bump structures 354 can include copper. Other suitable metal fill materials are within the intended scope of the present disclosure. The fan-out metal bump structures 354 can have a horizontal cross-sectional shape that is rectangular, rounded rectangular, or circular. Other horizontal cross-sectional shapes can be within the intended scope of the present disclosure.

[0041] According to one aspect of the present disclosure, fan-out metal bump structures 354 can be formed as second metal bump structures 54 that can later be joined with first metal bump structures to be provided in another package structure. In general, like the second metal bump structures 54, the fan-out metal bump structures 354 can be configured for micro-bump joining (i.e., C2 joining) and can have an upper post portion and a lower via portion. Each post portion of the second metal bump structures 54 can have a height in a range of 5 microns to 30 microns (e.g., 10 microns to 18 microns), although smaller or larger heights can also be used. Each post portion of the second metal bump structures 54 can have a diameter in a range of 2 microns to 10 microns (e.g., 3 microns to 8 microns), although smaller and larger diameters can also be used.

[0042] According to one aspect of the present disclosure, a layer of polymer material that can be joined to another layer of polymer material through polymer-to-polymer joining can be applied around the fan-out metal bump structures 354, which are second metal bump structures 54. The layer of polymer material is referred to herein as a fan-out polymer joining layer 359 that serves as a second polymer joining layer 59 to be used later in a joining process. In general, the second polymer joining layer 59 includes a polymer material that can be joined to another polymer material after a thermal annealing process. In one embodiment, the second polymer joining layer 59 can include any of polyimide (PI), benzocyclobutene (BCB), and polybenzobisoxazole (PBO). Other suitable polymer materials that provide polymer-to-polymer joining can also be used. As used herein, polymer-to-polymer joining is a joining between two polymer materials through polymer adhesion that is formed through the formation of atomic bonds between the polymer materials.

[0043] According to one aspect of the present disclosure, the second polymer joining layer 59 can be formed over the second metal bump structures 54 by spin coating to cover all surfaces of the second metal bump structures 54. The second metal bump structures 54 and the second polymer joining layer 59 can then be planarized, for example, by lapping and / or by chemical mechanical polishing. The height of the post portion of each second metal bump structure 54 can be in a range of 2 microns to 10 microns, for example, 3 microns to 8 microns, although smaller and larger heights can also be used. The second polymer joining layer 59 can then be vertically recessed to physically expose the top surface of the second metal bump structures 54 and the topmost surface segments of the sidewalls. The vertical recess distance of the top surface of the second polymer joining layer 59 below the level that includes the planar top surface of the second metal bump structures 54 can be in a range of 0.2 microns to 1.0 micron, although smaller and larger vertical recess distances can also be used.

[0044] Through-interposer via (TIV) structures 352 can be selectively formed on a subset of fan-out metal bump structures 354, which are second metal bump structures 54. In this embodiment, the subset of fan-out metal bump structures 354 can have a suitable lateral size (e.g., a size in the range of 15 microns to 60 microns) to accommodate the fan-out metal bump structures 354. The fan-out metal bump structures 354 can be formed, for example, by using a sacrificial deposition mask layer and at least a metal deposition process (e.g., an electroplating process, a physical vapor deposition process, etc.) or by attaching pre-fabricated TIV structures 352. The height of the TIV structures 352 can be in the range of 30 microns to 300 microns, although smaller and larger heights can also be used.

[0045] With reference to Figure 4 An array of first semiconductor interposers 100 can be provided on a carrier wafer, and the array of first semiconductor interposers 100 can be subsequently diced to provide stacks of first semiconductor interposers 100 and carrier substrates 801. The first semiconductor interposer 100 is one of the array of first semiconductor interposers 100. The carrier substrate 801 is a diced portion of the carrier wafer.

[0046] The first semiconductor interposer 100 can include a first semiconductor substrate 110 and a first substrate through via (TSV) structure 120 extending vertically through the first semiconductor substrate 110. Redistributed wiring interconnects formed within a redistribution dielectric layer can be formed on a first side of the first semiconductor substrate 110. The redistribution wiring interconnects are referred to herein as first distal redistribution wiring interconnects 160, and the redistribution dielectric layer is referred to herein as a first distal redistribution dielectric layer 150.

[0047] In an example embodiment, the first semiconductor substrate 110 can be provided as part of a semiconductor wafer including a two-dimensional array of first semiconductor substrates 110, and the first TSV structure 120 can be formed in an upper portion of the semiconductor wafer. In an embodiment, a commercially available single crystalline silicon wafer can be used as the semiconductor wafer. The first distal redistribution wiring interconnects 160 and the first distal redistribution dielectric layer 150 can be formed on a first side of the semiconductor wafer. The set of processing steps used to form the first distal redistribution wiring interconnects 160 and the first distal redistribution dielectric layer 150 can be similar to the set of processing steps used to form the fan-out redistribution wiring interconnects 340 and the fan-out redistribution dielectric layer 330.

[0048] The carrier wafer 801 can be attached to the first distal redistribution dielectric layer 150 with an adhesive layer 811. In one embodiment, the carrier wafer 801 can comprise an additional semiconductor wafer, which can be a polysilicon wafer or a single crystalline silicon wafer. The backside of the semiconductor wafer comprising the array of first semiconductor substrates 110 can be removed, for example, by a grinding, polishing, anisotropic etching process, and / or an isotropic etching process. Upon thinning of the semiconductor wafer, the end surface of the first TSV structures 120 can be exposed. The backside surface of the semiconductor wafer can be recessed with respect to the physically exposed surface of the first TSV structures 120. A planar insulating layer 111 can be formed on the physically exposed backside surface of the thinned semiconductor wafer. The proximal redistribution intraconnects 122 and optional proximal redistribution layers (not explicitly shown) can be formed on the physically exposed surface of the first TSV structures 120.

[0049] The proximal metal bump structures 144 and the first solder portions 148 can be formed on the proximal redistribution intraconnects 122. The proximal metal bump structures 144 serve as the first metal bump structures 44, and the first solder portions 148 serve as the solder portions 48. In general, like the first metal bump structures 44, the proximal metal bump structures 144 can be configured for micro bump bonding (i.e., C2 bonding) and can have an upper post portion and a lower via portion. Each post portion of the first metal bump structures 44 can have a height in the range of 2 microns to 10 microns (e.g., 3 microns to 8 microns), although smaller or larger heights can also be used. Each post portion of the first metal bump structures 44 can have a diameter in the range of 2 microns to 10 microns (e.g., 3 microns to 8 microns), although smaller and larger diameters can also be used.

[0050] According to one aspect of the disclosure, a layer of polymer material that is bondable to another layer of polymer material through polymer-to-polymer bonding can be applied around the proximal metal bump structures 144, which are the first metal bump structures 44. The layer of polymer material is referred to herein as a proximal polymer bonding layer 149, which serves as the first polymer bonding layer 49 that will be used in a subsequent bonding process. In general, the first polymer bonding layer 49 comprises a polymer material that is bondable to another polymer material after a thermal annealing process. In one embodiment, the first polymer bonding layer 49 can comprise any of polyimide (PI), benzocyclobutene (BCB), and polybenzobisoxazole (PBO). Other suitable polymer materials that provide polymer-to-polymer bonding can also be used.

[0051] According to one aspect of the disclosure, the first polymer bonding layer 49 can be formed over the solder portions 48 (which can include first solder portions 148) by spin coating to cover all surfaces of the solder portions 48. The solder portions 48 and the first polymer bonding layer 49 can then be planarized by grinding and / or by chemical mechanical grinding. The height of each remaining solder portion 48 can be in a range from 2 microns to 6 microns, such as from 2.5 microns to 5 microns, although smaller and larger heights can also be used. The solder portions 48 can then be vertically recessed by a vertical recess distance in a range from 0.2 microns to 1 micron. After the recessing process, the height of each remaining solder portion 48 can be in a range from 1.8 microns to 5 microns, such as from 2 microns to 4 microns, although smaller and larger heights can also be used.

[0052] The combination of the semiconductor wafer on which the first TSV structures 120 are formed, the combination of the first remote redistribution intraconnects 160 and the first remote redistribution dielectric layer 150, the near redistribution intraconnects 122 and the near redistribution layer (if any), the carrier wafer, and the adhesive layer 811 between the carrier wafer and the first remote redistribution dielectric layer 150 can be diced along a dicing street. Each diced portion of the combination of the semiconductor wafer with the first TSV structures 120, the combination of the first remote redistribution intraconnects 160 and the first remote redistribution dielectric layer 150, the near redistribution intraconnects 122 and the near redistribution layer (if any) forms a first semiconductor interposer 100, which functions as a first package structure. Each diced portion of the carrier wafer forms a carrier substrate 801, which can include a silicon substrate having a thickness in a range from 200 microns to 1 millimeter, and provides structural support for the first semiconductor interposer 100. In this embodiment, the carrier substrate 801 can be used to handle the first semiconductor interposer 100 when the first semiconductor interposer 100 is attached to the fan-out semiconductor package 290.

[0053] Figures 5A-5I Sequential vertical cross-sectional views of exemplary package structures that can be bonded using the hybrid bonding process of the disclosure are shown. In Figures 5A-5I The first semiconductor interposer 100 shown or any other package structure can be provided. The second package structure 920 can include the fan-out semiconductor package 290 shown or any other package structure. The processing steps described can be used to provide bonding between the first semiconductor interposer 100 and the fan-out semiconductor package 290 and accompanying polymer-to-polymer bonding between the near polymer bonding layer 149 (as the first polymer bonding layer 49) and the fan-out polymer bonding layer 359 (as the second polymer bonding layer 59). Figure 4 The first semiconductor interposer 100 shown or any other package structure can be provided. The second package structure 920 can include the fan-out semiconductor package 290 shown or any other package structure. The processing steps described can be used to provide bonding between the first semiconductor interposer 100 and the fan-out semiconductor package 290 and accompanying polymer-to-polymer bonding between the near polymer bonding layer 149 (as the first polymer bonding layer 49) and the fan-out polymer bonding layer 359 (as the second polymer bonding layer 59). Figure 4 The first semiconductor interposer 100 shown or any other package structure can be provided. The second package structure 920 can include the fan-out semiconductor package 290 shown or any other package structure. The processing steps described can be used to provide bonding between the first semiconductor interposer 100 and the fan-out semiconductor package 290 and accompanying polymer-to-polymer bonding between the near polymer bonding layer 149 (as the first polymer bonding layer 49) and the fan-out polymer bonding layer 359 (as the second polymer bonding layer 59). Figures 5A-5I The first semiconductor interposer 100 shown or any other package structure can be provided. The second package structure 920 can include the fan-out semiconductor package 290 shown or any other package structure. The processing steps described can be used to provide bonding between the first semiconductor interposer 100 and the fan-out semiconductor package 290 and accompanying polymer-to-polymer bonding between the near polymer bonding layer 149 (as the first polymer bonding layer 49) and the fan-out polymer bonding layer 359 (as the second polymer bonding layer 59).

[0054] Referring to Figure 5A A portion of a first package structure 910, which can include the first semiconductor interposer 100 or any other package structure, is shown. The first package structure 910 can include first metal interconnect structures 918 therein, as with embodiments of the first semiconductor interposer 100, the first package structure 910 can include, for example, first TSV structures 120, proximal re-routed interconnects 122, first distal re-routed interconnects 160, etc. First metal bump structures 44 can be formed on the first package structure 910. For example, the first metal bump structures 44 can include proximal metal bump structures 144. In general, the first metal bump structures 44 can be electrically connected to the first metal interconnect structures 918.

[0055] Solder portions 48, which can include first solder portions 148, are bonded to the first metal bump structures 44. The first metal bump structures 44 can be configured as micro-bump bonds (i.e., C2 bonds). In an embodiment, each of the first metal bump structures 44 can have an upper pillar portion and a lower via portion. The first metal bump structures 44 and the solder portions 48 can be formed by deposition and patterning of metal bump material and solder, and each stack of the upper pillar portion of the first metal bump structures 44 and the solder portions 48 can have the same horizontal cross-sectional shape.

[0056] Each pillar portion in the first metal bump structures 44 and each solder portion 48 can have a diameter in a range of 2 microns to 10 microns (e.g., 3 microns to 8 microns), although smaller and larger diameters can also be used. Each pillar portion of the first metal bump structures 44 can have a height in a range of 2 microns to 10 microns (e.g., 3 microns to 8 microns), although smaller or larger heights can also be used. Each solder portion 48 formed on the first metal bump structures 44 can have a height in a range of 3 microns to 15 microns (e.g., 5 microns to 10 microns), although smaller and larger heights can also be used. In an embodiment, the pitch of the upper pillar portion of the first metal bump structures 44 and the solder portions 48 can be in a range of 4 microns to 20 microns, although smaller and larger pitches can also be used.

[0057] Referring to Figure 5BA first polymer material layer 49' can be formed over the first metal bump structures 44. The first polymer material layer 49' is a polymer bonding layer that is subsequently modified. The first polymer material layer 49' can include any of polyimide (PI), benzocyclobutene (BCB), and polybenzoxazole (PBO). Other suitable polymer materials that provide polymer-to-polymer bonding can also be used. In an embodiment, the first polymer material layer 49' can be formed by spin coating. The thickness of the first polymer material layer 49' can be selected such that the solder portions 48 are covered by the first polymer material layer 49'. The first polymer material layer 49' can be cured by performing a first annealing process at a first high temperature, which can be in a range from 150 degrees Celsius to 200 degrees Celsius. The duration of the first annealing process can be in a range from 10 minutes to 200 minutes, although shorter and longer durations can also be used.

[0058] Referring to Figure 5C A planarization process can be performed to remove an upper portion of the first polymer material layer 49' and the solder portions 48. The planarization process can include a grinding process and / or a chemical mechanical grinding process. The remaining portion of the first polymer material layer 49' constitutes the first polymer bonding layer 49. After the planarization process, the height of the solder portions 48 can be in a range from 2 microns to 6 microns, such as from 2.5 microns to 5 microns, although smaller and larger heights can also be used. The top surface of the first polymer bonding layer 49 can be coplanar with the top surface of the remaining portions of the solder portions 48.

[0059] Referring to Figure 5D Subsequently, the solder portions 48 can be vertically recessed, such as by performing a plasma dry etching process selective to the first polymer bonding layer 49. The vertically recessed distance can be in a range from 0.2 microns to 1 micron. After the recessing process, the height of each remaining solder portion 48 can be in a range from 1.8 microns to 5 microns, such as from 2 microns to 4 microns, although smaller and larger heights can also be used.

[0060] Referring to Figures 5B-5DA first polymer material layer 49' having a planar top surface can be formed over the first metal bump structure 44, which can include a proximal metal bump structure 144. The first polymer material layer 49' can be vertically recessed until a top surface of the solder portion 48, which can include a first solder portion 148, is exposed. A first polymer bond layer 49, which can include a proximal polymer bond layer 149, is formed. The solder portion 48, which can include a first solder portion 148, can be selectively vertically recessed relative to the first polymer bond layer 49, which can include a proximal polymer bond layer 149. In particular, a physically exposed surface of the solder portion 48, which can include a first solder portion 148, can be vertically recessed relative to a physically exposed surface of the first polymer bond layer 49, which can include a proximal polymer bond layer 149.

[0061] Referring to Figure 5E A portion of a second package structure 920, which can include a fan-out semiconductor package 290 or any other package structure, is shown. The second package structure 920 can include a second metal interconnect structure 928 therein, as in embodiments of the fan-out semiconductor package 290. The second package structure 920 may, for example, include the metal interconnect structure 222, the die-side bond pads 224, the fan-out rewiring interconnect 340, etc. A second metal bump structure 54 can be formed on the second package structure 920. By way of example, the second metal bump structure 54 can include a fan-out metal bump structure 354. In general, the second metal bump structure 54 can be electrically connected to the second metal interconnect structure 928.

[0062] In an embodiment, each second metal bump structure 54 can have an upper pillar portion and a lower via portion. The second metal bump structure 54 can be formed by deposition and patterning of a metal bump material. The pillar portion of the second metal bump structure 54 can have the same diameter as the pillar portion of the first metal bump structure 44 and the solder portion 48. Each pillar portion of the second metal bump structure 54 can have a height in a range of 5 microns to 30 microns, such as 10 microns to 18 microns, although smaller or larger heights can also be used. The pattern of the second metal bump structure 54 can be a mirror image of the pattern of the first metal bump structure 44.

[0063] Referring to Figure 5FA second polymer material layer 59' can be formed over the second metal bump structures 54. The second polymer material layer 59' is a polymer bonding layer that is subsequently modified. The second polymer material layer 59' can include any of polyimide (PI), benzocyclobutene (BCB), and polybenzoxazole (PBO). Other suitable polymer materials that provide polymer-to-polymer bonding can also be used. The material of the second polymer material layer 59' can be the same as or can be different from the material of the first polymer material layer 49'. In an embodiment, the second polymer material layer 59' can be formed by spin coating. The thickness of the second polymer material layer 59' can be selected so that the second metal bump structures 54 are covered by the second polymer material layer 59'. The second polymer material layer 59' can be cured by performing a second annealing process at a second high temperature, which can be in a range from 150 degrees Celsius to 200 degrees Celsius. The duration of the second annealing process can be in a range from 10 minutes to 200 minutes, although shorter and longer durations can also be used.

[0064] Referring to Figure 5G A planarization process can be performed to remove an upper portion of the second polymer material layer 59'. The planarization process can include a grinding process and / or a chemical mechanical grinding process. Subsequently, the second metal bump structures 54 and the second polymer material layer 59' can be planarized, for example, by grinding and / or by chemical mechanical grinding. After the planarization process, the height of the column portion of each second metal bump structure 54 can be in a range from 2 microns to 10 microns, for example, 3 microns to 8 microns, although smaller and larger heights can also be used.

[0065] Subsequently, the second polymer material layer 59' can be vertically recessed to physically expose the top surfaces of the second metal bump structures 54 and the topmost sections of the sidewalls. After the recessing process, the remaining portion of the second polymer material layer 59' constitutes a second polymer bonding layer 59. The vertical recessed distance of the top surface of the second polymer bonding layer 59 below the horizontal plane that includes the planar top surfaces of the second metal bump structures 54 can be in a range from 0.2 microns to 1.0 microns, although smaller and larger vertical recessed distances can also be used.

[0066] The material of the second polymer bonding layer 59 can be the same as or can be different from the material of the first polymer bonding layer 49. In an embodiment, the material of the second polymer bonding layer 59 can be different from the material of the first polymer bonding layer 49. In an embodiment, the material of the second polymer bonding layer 59 and the first polymer bonding layer 49 is such that the second polymer bonding layer 59 and the first polymer bonding layer 49 provide strong polymer-to-polymer bonding upon contact and subsequent annealing process. In an embodiment, the first polymer bonding layer 49 can comprise a first component of a two-component adhesive material (e.g., epoxy), and the second polymer bonding layer 59 can comprise a second component of the two-component adhesive material. In a non-limiting illustrative example, the first polymer bonding layer 49 can comprise a first component polymer material (e.g., epoxy) used to form an epoxy, and the second polymer bonding layer 59 can comprise a second component polymer material (e.g., hardener) used to form the epoxy.

[0067] With reference to Figures 5E-5G , a second package structure 920 (e.g., a fan-out semiconductor package 290) is provided, the second package structure 920 comprising a second metal interconnect structure 928 (which can comprise the metal interconnect structure 222, the die-side bonding pads 224, the fan-out rewiring interconnects 340), a second metal bump structure 54 (which can comprise the fan-out metal bump structure 354) electrically connected to the second metal interconnect structure 928, and a second polymer bonding layer 59 (which can comprise the fan-out polymer bonding layer 359) laterally surrounding the second metal bump structure 54 (which can comprise the fan-out metal bump structure 354). In an embodiment, the second package structure 920 can be formed by forming a second polymer material layer 59' having a planar top surface over the second metal bump structure 54, and by vertically recessing the top surface of the second polymer material layer 59' to below a level comprising the top surface of the second metal bump structure 54. The remaining portion of the second polymer material layer 59' constitutes the second polymer bonding layer 59.

[0068] With reference to Figure 5H , the second package structure 920 can be positioned to face the first package structure 910, and the second metal bump structure 54 of the second package structure 920 can be aligned with the solder portion 48 on the first package structure 910. The first polymer bonding layer 49 and the second polymer bonding layer 59 can be pre-heated to a temperature in the range of 150 degrees Celsius to 200 degrees Celsius for a duration of time, which can be in the range of 1 second to 20 seconds.

[0069] With reference to Figure 5IA hybrid bonding process including a combination of solder bonding and polymer-to-polymer bonding can be performed. In particular, the second metal bump structure 54 is in contact with the solder portion 48. The assembly of the first package structure 910 and the second package structure 920 can be heated to a reflow temperature or higher to cause the solder portion 48 to reflow and bond between the solder portion 48 and the second metal bump structure 54. The high temperature of the reflow process can be in a range of 250 degrees Celsius to 300 degrees Celsius, and the duration of the reflow process can be in a range of 10 seconds to 60 seconds. Subsequently, when the solder portion 48 is at or below the reflow temperature, the assembly of the first package structure 910 and the second package structure 920 can be annealed at a high temperature to cause polymer-to-polymer bonding between the first polymer bonding layer 49 and the second polymer bonding layer 59. The high temperature can be in a range of 200 degrees Celsius to 300 degrees Celsius. The duration of the annealing process can be in a range of 30 minutes to 3 hours, although shorter and longer durations can also be used.

[0070] In general, the second metal bump structure 54 (which can include a fan-out metal bump structure 354) can be bonded to the first metal bump structure 44 (which can include a proximal metal bump structure 144) by performing a bonding process in which the solder portion 48 (which can include a first solder portion 148) is reflowed while the second metal bump structure 54 (which can include a fan-out metal bump structure 354) contacts the solder portion 48 and while the second polymer bonding layer 59 (which can include a fan-out polymer bonding layer 359) contacts the first polymer bonding layer 49 (which can include a proximal polymer bonding layer 149). In an embodiment, the second polymer bonding layer 59 (which can include a fan-out polymer bonding layer 359) is bonded to the first polymer bonding layer 49 (which can include a proximal polymer bonding layer 149) while the solder portion 48 is reflowed.

[0071] Referring to Figure 6 Each carrier substrate 801 can be separated from the respective first semiconductor interposers 100. An appropriate cleaning process can be performed to remove the adhesive layer 811. An encapsulant (e.g., a molding compound (MC) material) can be applied around the array of first semiconductor interposers 100 and TIV structures 352. The MC material can include any material that can be used for a molding compound die matrix, which is described in more detail with reference to Figure 2 The molding compound interposer matrix can be formed around the array of first semiconductor interposers 100 and TIV structures 352. Each portion of the molding compound interposer matrix that is located within a cell region UA1 is referred to herein as a molding compound interposer frame 335 or MC interposer frame 335. Each MC interposer frame 335 laterally surrounds a first semiconductor interposer 100 and a selective set of TIV structures 352.

[0072] A planarization process can be performed to remove portions of the MC material covering the topmost horizontal surface of the first semiconductor interposer 100. The top surface of the MC material can be coplanar, including the top surface of the first semiconductor interposer 100 and the remaining portion of the TIV structure 352. The reconstructed wafer now comprises a two-dimensional array of a combination of a fan-out semiconductor package 290, the first semiconductor interposer 100, a selective TIV structure 352, and a molded compound framework (which is a molded compound interposer framework 335). As described above, the illustrated portion of the exemplary structure corresponds to cell region UA1, i.e., the region within the reconstructed wafer that includes a single repeating cell.

[0073] refer to Figure 7 The redistribution interconnects formed within the redistribution dielectric layer can be formed above the first far-end redistribution interconnect 160 and the first far-end redistribution dielectric layer 150. The redistribution interconnect formed at this processing step is referred to herein as the second far-end redistribution interconnect 380. The redistribution dielectric layer formed at this processing step is referred to herein as the second far-end redistribution dielectric layer 370. This set of processing steps for forming the second far-end redistribution interconnect 380 and the second far-end redistribution dielectric layer 370 can be similar to the set of processing steps for forming the fan-out redistribution interconnect 340 and the fan-out redistribution dielectric layer 330.

[0074] Subsequently, it can be implemented in accordance with the above. Figures 5A-5D The described processing steps form a distal metal bump structure 344, a second solder portion 348, and a distal polymer bonding layer 349. In this embodiment, the second distal redistribution interconnect 380 constitutes... Figures 5A-5D The first metal interconnect structure 918 is a component of the first metal interconnect structure 918, and the first metal bump structure 44 is formed on the first metal interconnect structure 918. The distal metal bump structure 344 corresponds to Figures 5A-5D The first metal bump structure 44. The second solder portion 348 corresponds to Figures 5A-5D The solder portion 48 in the middle. The distal polymer bonding layer 349 corresponds to Figure 5C and 5D The first polymer bonding layer 49 in the middle.

[0075] The combination of all material portions within each unit area UA1 except for the second solder portion 348, the first carrier wafer 710, and the first DAF 711 constitutes a die interposers assembly 300, which is an assembly comprising at least one semiconductor die 200 and a first semiconductor interposer 100. Each die interposers assembly 300 is a second stage compound package incorporated into a first stage compound package. The reconstituted wafer now comprises a two-dimensional array of die interposers assemblies 300. As noted above, the illustrated portion of the example structure corresponds to a unit area UA1, i.e., an area within the reconstituted wafer comprising a single repeating unit.

[0076] Referring to Figure 8 The second carrier wafer 720 can be adhered to the reconstituted wafer using a second DAF 721. The second carrier wafer 720 can comprise an optically transparent material, such as glass. If the first carrier wafer 710 comprises an optically transparent material (e.g., glass), the first DAF 711 can be irradiated with high energy photons (e.g., ultraviolet photons) to cause chemical bond breakage therein. The first carrier wafer 710 can be separated from the assembly of the reconstituted wafer and the second carrier wafer 720.

[0077] A grinding process can be performed to thin the backside of the semiconductor dies 200 and dummy dies 201. The thickness of the die semiconductor substrate 210 of each semiconductor die 200 can be in the range of 30 microns to 300 microns, although smaller and larger thicknesses can also be used. As noted above, the illustrated portion of the example structure corresponds to a unit area UA1, i.e., an area within the reconstituted wafer comprising a single repeating unit.

[0078] Referring to Figure 9 The second DAF 721 can be irradiated by high energy photons (e.g., ultraviolet photons) through the second carrier wafer 720 to cause chemical bond breakage therein. The second carrier wafer 720 can be separated from the reconstituted wafer. The reconstituted wafer can be mounted on a dicing frame, and can subsequently be diced along dicing channels, which are the boundaries between adjacent pairs of unit areas UA1. The reconstituted wafer is diced into separate die interposers assemblies 300. Each die interposers assembly 300 is a second stage compound package. Thus, an array of second stage compound packages can be singulated into separate second stage compound packages (i.e., separate die interposers assemblies 300). A single one of the die interposers assemblies 300 is illustrated in Figure 9

[0079] Referring to Figure 5I and Figure 9 ​, a bonded assembly is provided that includes: a first package structure 910 (which can include a first semiconductor interposer 100) that includes first metal interconnect structures 918 (e.g., first TSV structures 120, proximal re-routed interconnects 122, and first distal re-routed interconnects 160), first metal bump structures 44 (which can include proximal metal bump structures 144) electrically connected to the first metal interconnect structures 918, and a first polymer bonding layer 49 (which can include proximal polymer bonding layer 149) laterally surrounding the first metal bump structures 44 (which can include proximal metal bump structures 144); a second package structure 920 (e.g., a fan-out semiconductor package 290) that includes second metal interconnect structures 928 (which can include metal interconnect structures 222, die-side bonding pads 224, fan-out re-routed interconnects 340, etc.), second metal bump structures 54 (which can include fan-out metal bump structures 354) electrically connected to the second metal interconnect structures 928, and a second polymer bonding layer 59 (which can include fan-out polymer bonding layer 359) laterally surrounding the second metal bump structures 54 (which can include fan-out metal bump structures 354); and solder portions 48 (which can include first solder portions 148) between the first metal bump structures 44 and the second metal bump structures 54. Each solder portion 48 is bonded to a respective one of the first metal bump structures 44 and a respective one of the second metal bump structures 54, and the second polymer bonding layer 59 is bonded to the first polymer bonding layer 49 by polymer-to-polymer bonding.

[0080] In an embodiment, the first package structure 910 (which can include a first semiconductor interposer 100) includes a first semiconductor substrate 110 that includes first substrate via structures 120 through the first semiconductor substrate 110. The first metal interconnect structures 918 (e.g., first TSV structures 120, proximal re-routed interconnects 122, and first distal re-routed interconnects 160) include the first substrate via structures 120. In an embodiment, the first package structure 910 is laterally surrounded by a mold compound frame (e.g., a mold compound interposer frame 335) laterally surrounding the first semiconductor substrate 110.

[0081] In an embodiment, the first metal interconnect structure 918 (e.g., the first TSV structure 120, the proximal redistribution line interconnect 122, and the first distal redistribution line interconnect 160) includes: a first redistribution line interconnect (e.g., the first distal redistribution line interconnect 160) formed within a first redistribution dielectric layer (e.g., the first distal redistribution dielectric layer 150); and the first redistribution dielectric layer (e.g., the first distal redistribution dielectric layer 150) laterally surrounded by a mold compound frame (e.g., the mold compound interposer frame 335).

[0082] In an embodiment, the first metal interconnect structure 918 (e.g., the first TSV structure 120, the proximal redistribution line interconnect 122, and the first distal redistribution line interconnect 160) includes a second redistribution line interconnect (e.g., the second distal redistribution line interconnect 380) formed within a second redistribution dielectric layer (e.g., the second distal redistribution dielectric layer 370); and the second redistribution dielectric layer (e.g., the second distal redistribution dielectric layer 370) includes a horizontal surface in contact with a mold compound frame (e.g., the mold compound interposer frame 335) and includes a sidewall vertically coincident with an outer sidewall of the mold compound frame (e.g., the mold compound interposer frame 335).

[0083] In an embodiment, the second package structure 920 (e.g., the fan-out semiconductor package 290) includes: an additional semiconductor substrate (e.g., the die semiconductor substrate 210); and field effect transistors (which are a subset of the semiconductor components 220) located on the additional semiconductor substrate (e.g., the die semiconductor substrate 210). The second metal interconnect structure 928 (which can include the metal interconnect structure 222, the die side bond pad 224, the fan-out redistribution line interconnect 340, etc.) includes the metal interconnect structure 222 electrically connected to the field effect transistors.

[0084] In an embodiment, a horizontal bond interface distance between the second polymer bond layer 59 (which can include the fan-out polymer bond layer 359) and the first polymer bond layer 49 (which can include the proximal polymer bond layer 149) includes a horizontal surface of a proximal horizontal surface of the first semiconductor substrate 110 of the first package structure 910 (which can include the first semiconductor interposer 100) is farther than an interface distance between the solder portion 48 (which can include the first solder portion 148) and the second metal bump structure 54 (which can include the fan-out metal bump structure 354) from the horizontal surface of the proximal horizontal surface of the first semiconductor substrate 110 of the first package structure 910 (which can include the first semiconductor interposer 100).

[0085] In an embodiment, each of the solder portions 48 (which can include first solder portions 148) is laterally surrounded by and contacts a first polymer bonding layer 49 (which can include a proximal polymer bonding layer 149). In an embodiment, the second polymer bonding layer 59 (which can include a fan-out polymer bonding layer 359) is spaced apart from and does not contact the solder portions 48 (which can include first solder portions 148).

[0086] In an embodiment, the first polymer bonding layer 49 (which can include a proximal polymer bonding layer 149) is spaced apart from and does not contact the second package structure 920 (e.g., a fan-out semiconductor package 290), and the second polymer bonding layer 59 (which can include a fan-out polymer bonding layer 359) is spaced apart from and does not contact the first package structure 910 (which can include a first semiconductor interposer 100).

[0087] According to another aspect of the present disclosure, a bonded assembly is provided, the bonded assembly comprising: a first package structure 910 (which can include a first semiconductor interposer 100), the first package structure 910 including a first metal interconnect structure 918 (e.g., a first TSV structure 120, a proximal re-distribution line interconnect 122, and a first distal re-distribution line interconnect 160), a first metal bump structure 44 (which can include a proximal metal bump structure 144) electrically connected to the first metal interconnect structure 918 (e.g., a first TSV structure 120, a proximal re-distribution line interconnect 122, and a first distal re-distribution line interconnect 160), and a first polymer bonding layer 49 (which can include a proximal polymer bonding layer 149) laterally surrounding the first metal bump structure 44 (which can include a proximal metal bump structure 144); a second package structure 920 (e.g., a fan-out semiconductor package 290), the second package structure 920 including a second metal interconnect structure 928 (which can include a metal interconnect structure 222, a die-side bonding pad 224, and a fan-out re-distribution line interconnect 340), a second metal bump structure 54 (which can include a fan-out metal bump structure 354) electrically connected to the second metal interconnect structure 928 (which can include a metal interconnect structure 222, a die-side bonding pad 224, and a fan-out re-distribution line interconnect 340), and a second polymer bonding layer 59 (which can include a fan-out polymer bonding layer 359) laterally surrounding the second metal bump structure 54 (which can include a fan-out metal bump structure 354); and a solder portion 48 (which can include a first solder portion 148) between the first metal bump structure 44 (which can include a proximal metal bump structure 144) and the second metal bump structure 54 (which can include a fan-out metal bump structure 354). Each solder portion 48 (which can include a first solder portion 148) is bonded to a respective one of the first metal bump structure 44 (which can include a proximal metal bump structure 144) and a respective one of the second metal bump structure 54 (which can include a fan-out metal bump structure 354), each solder portion 48 (which can include a first solder portion 148) is laterally surrounded by the first polymer bonding layer 49 (which can include a proximal polymer bonding layer 149) and is not in direct contact with the second polymer bonding layer 59 (which can include a fan-out polymer bonding layer 359). The first polymer bonding layer 49 (which can include a proximal polymer bonding layer 149) is spaced apart from the second package structure 920 (e.g., a fan-out semiconductor package 290) by the second polymer bonding layer 59 (which can include a fan-out polymer bonding layer 359).

[0088] In an embodiment, the second polymer bonding layer 59 (which can include a fan-out polymer bonding layer 359) is bonded to the first polymer bonding layer 49 (which can include a proximal polymer bonding layer 149) by polymer-to-polymer bonding. In an embodiment, the first package structure 910 (which can include a first semiconductor interposer 100) includes the first semiconductor substrate 110, and a horizontal plane of an interface between the first polymer bonding layer 49 (which can include a proximal polymer bonding layer 149) and the second polymer bonding layer 59 (which can include a fan-out polymer bonding layer 359) is farther from a horizontal plane including a proximal horizontal surface of the first semiconductor substrate 110 than a distance of an interface between the solder portion 48 (which can include a first solder portion 148) and the second metal bump structure 54 (which can include a fan-out metal bump structure 354).

[0089] In an embodiment, the first semiconductor substrate 110 is embedded in the first substrate via structure 120 and is laterally surrounded by a mold compound frame (e.g., a mold compound interposer frame 335), and the second package structure 920 (e.g., a fan-out semiconductor package 290) includes a semiconductor die 200 including field effect transistors (which are a subset of semiconductor components 220) therein.

[0090] Referring to Figure 10 , a semiconductor interposer in-process semiconductor interposer 600' is shown that is within a wafer and the wafer includes an array of semiconductor interposer in-process. As used herein, an "in-process" component refers to a component whose material composition and / or shape will be changed in at least one subsequent processing step. The illustrated region of the wafer corresponds to a repeating unit area UA2 in which a single semiconductor interposer in-process 600' is provided. Each semiconductor interposer in-process 600' can be processed into a second semiconductor interposer during a subsequent processing step.

[0091] An interposer semiconductor substrate 510 is shown that is a portion of a semiconductor wafer that is within a repeating unit area UA2. The repeating unit area UA2 in the semiconductor wafer is smaller than the semiconductor interposer 500 that is formed from the semiconductor wafer. The semiconductor wafer includes a plurality of semiconductor interposer substrates 510 that are within a plurality of repeating unit areas UA2. Figures 1-4 and Figures 6-8A repeating unit area UA1 of the die interposer assembly 300 is shown. A planar insulating layer 611 can be formed on a top surface of the interposer semiconductor substrate 510. A via cavity having a depth in a range from 2 microns to 40 microns can be formed through the planar insulating layer 611 and into an upper portion of the interposer semiconductor substrate 510. A combination of an insulating spacer (not shown) and a second substrate through via (TSV) structure 620 can be formed in each via cavity by performing a material deposition process and a planarization process (e.g., a chemical mechanical polishing process).

[0092] A metal bump structure (referred to herein as a silicon interposer metal bump structure 654) can be formed in the planar insulating layer 611. According to one aspect of the present disclosure, the silicon interposer metal bump structure 654 includes a pillar portion having the same structure as the pillar portion of the second metal bump structure 54 described with reference to Figures 5E-5G FIG. 6. Thus, the silicon interposer metal bump structure 654 is formed as the second metal bump structure 54 and can have the same configuration as the second metal bump structure 54 described with reference to Figures 5E-5G FIG. 6 for the purpose of a subsequent bonding process. In this embodiment, the second TSV structure 620 functions as the second metal interconnect structure 928.

[0093] In addition, a second polymer bonding layer 59 can be formed around the second metal bump structure 54 (which can include the silicon interposer metal bump structure 654), as described with reference to Figure 5F and 5G FIG. 6. In this embodiment, the second polymer bonding layer 59 is referred to herein as a silicon interposer polymer bonding layer 659.

[0094] With reference to Figure 11 , a hybrid bonding process including a combination of solder bonding and polymer-to-polymer bonding can be performed in the same manner as described with reference to Figure 5I FIG. 6. In this embodiment, Figure 9The die interposer assembly 300 is used as the first package structure 910 and the semiconductor interposer semi-finished product 600' is used as the second package structure 920. The first TSV structure 120, the proximal re-routed intraconnect 122, the first distal re-routed intraconnect 160, and the second distal re-routed intraconnect 380 are used as the first metal intraconnect structure 918 within the first package structure 910. The second TSV structure 620 is used as the second metal intraconnect structure 928 in the second package structure 920. The distal metal bump structure 344 in the die interposer assembly 300 is used as the first metal bump structure 44. The second solder portion 348 is used as the solder portion 48. The silicon interposer metal bump structure 654 of the semiconductor interposer semi-finished product 600' is used as the second metal bump structure 54. The distal polymer bonding layer 349 is used as the first polymer bonding layer 49. The silicon interposer polymer bonding layer 659 is used as the second polymer bonding layer 59.

[0095] Referring to FIG. 1, a semiconductor die 100 is provided. The semiconductor die 100 includes a semiconductor die active surface 102, a semiconductor die back surface 104, a first TSV structure 120, a proximal re-routed intraconnect 122, a first distal re-routed intraconnect 160, and a second distal re-routed intraconnect 380. Figures 5A-5I and Figures 7-11 The described processing steps can provide a first package structure 910 (which can include a die interposer assembly 300). The first package structure 910 includes: a first metal intraconnect structure 918 (e.g., the first TSV structure 120, the proximal re-routed intraconnect 122, the first distal re-routed intraconnect 160, and optionally the second distal re-routed intraconnect 380), a first metal bump structure 44 (which can include a distal metal bump structure 344) electrically connected to the first metal intraconnect structure 918 (e.g., the first TSV structure 120, the proximal re-routed intraconnect 122, the first distal re-routed intraconnect 160, and optionally the second distal re-routed intraconnect 380), and a first polymer bonding layer 49 (which can include a distal polymer bonding layer 349) laterally surrounding the first metal bump structure 44 (which can include a distal metal bump structure 344). A solder portion 48 (e.g., a second solder portion 348) can be formed on the first metal bump structure 44.

[0096] In an embodiment, the first polymer bonding layer 49 (which can include the distal polymer bonding layer 349) can be provided by forming the solder portion 48 over the first metal bump structure 44, by forming a first polymer material layer 49' having a planar top surface over the first metal bump structure 44 (which can include the distal metal bump structure 344) and the solder portion 48 (which can include the second solder portion 348), and by vertically recessing the first polymer material layer 49' until the top surface of the solder portion 48 is exposed. The first polymer bonding layer 49 includes the remaining portion of the first polymer material layer 49'. The solder portion 48 (which can include the second solder portion 348) can be selectively vertically recessed relative to the first polymer bonding layer 49 (which can include the distal polymer bonding layer 349). In an embodiment, the physically exposed surface of the solder portion 48 (which can include the second solder portion 348) is vertically recessed relative to the physically exposed surface of the first polymer bonding layer 49 (which can include the distal polymer bonding layer 349) prior to performing the bonding process.

[0097] A second package structure 920 (which can include the semiconductor interposer semi-finished product 600') can be provided. The second package structure 920 includes a second metal interconnect structure 928 (which can include the second TSV structure 620), a second metal bump structure 54 (which can include the silicon interposer metal bump structure 654) electrically connected to the second metal interconnect structure 928 (which can include the second TSV structure 620), and a second polymer bonding layer 59 (which can include the silicon interposer polymer bonding layer 659) laterally surrounding the second metal bump structure 54 (which can include the silicon interposer metal bump structure 654). In an embodiment, a second polymer material layer 59' having a planar top surface can be formed over the second metal bump structure 54 (which can include the silicon interposer metal bump structure 654). The top surface of the second polymer material layer 59' can be vertically recessed below the level of the top surface of the second metal bump structure 54 (which can include the silicon interposer metal bump structure 654). The second polymer bonding layer 59 (which can include the silicon interposer polymer bonding layer 659) is formed.

[0098] During the hybrid bonding process, the second metal bump structure 54 is in contact with the solder portion 48. The assembly of the first package structure 910 and the second package structure 920 can be heated to a reflow temperature or higher to cause the solder portion 48 to reflow and make a bond between the solder portion 48 and the second metal bump structure 54. The high temperature of the reflow process can be in the range of 250 degrees Celsius to 300 degrees Celsius, and the duration of the reflow process can be in the range of 10 seconds to 60 seconds. Subsequently, when the solder portion 48 is at or below the reflow temperature, the assembly of the first package structure 910 and the second package structure 920 can be annealed at a high temperature to make a polymer-to-polymer bond between the first polymer bonding layer 49 and the second polymer bonding layer 59. The high temperature can be in the range of 200 degrees Celsius to 300 degrees Celsius. The duration of the annealing process can be in the range of 30 minutes to 3 hours, although shorter and longer durations can also be used.

[0099] Additionally, while, before, or after the die interposer assembly 300 is bonded to the semiconductor interposer semi-finish 600’, additional semiconductor dies or additional semiconductor packages can be bonded to the semiconductor interposer semi-finish 600’. For example, at least one memory die 400, such as at least one high bandwidth memory (HBM) memory die, can be provided. Each HBM memory die can include a vertical stack of a memory layer 410 and a substrate layer 420 that includes logic circuitry for controlling operation of a memory array in the memory layer 410. A mold compound frame 430 can laterally surround the vertical stack of the memory layer 410 and the substrate layer 420. In general, the first metal bump structure 44, the solder portion 48, and the first polymer bonding layer 49 can be provided on each memory die 400. The first metal bump structure 44 formed on the at least one memory die 400 is referred to herein as a memory die metal bump structure 444. The solder portion 48 provided on the memory die metal bump structure 444 is referred to herein as a third solder portion 448. The first polymer bonding layer 49 formed on the at least one memory die 400 is referred to herein as a memory die polymer bonding layer 449. The processing steps described below can be used to bond each memory die 400 to the semiconductor interposer semi-finish 600’. Figures 5A-5I The processing steps described below can be used to bond each memory die 400 to the semiconductor interposer semi-finish 600’.

[0100] Reference is made to Figure 12An encapsulant, such as a mold compound (MC) material, can be applied to the gap between the die interposer assembly 300 and the memory die 400 that are joined to the array of semiconductor interposer semi-finished products 600'. The encapsulant can include any material that can be used for the mold compound die frame 305 or the mold compound interposer frame 335 as described above. A planarization process can be performed to remove a portion of the MC material that overlies a horizontal plane that includes the topmost faces of the semiconductor dies 200 and the memory die 400. The top faces of the semiconductor dies 200 and the dummy die 201 can be coplanar with the top faces of the remaining portions of the MC material. The remaining portions of the MC material include a mold compound matrix. Each portion of the mold compound matrix that is located within a unit area UA2 constitutes a mold compound die frame that laterally surrounds a plurality of semiconductor dies, and is referred to herein as a mold compound multi-die frame 505. The combination 500 of the array of semiconductor interposer semi-finished products 600', the die interposer assembly 300, the memory die 400, and the mold compound matrix constitutes a reconstituted wafer. The reconstituted wafer can include a two-dimensional array of reconstituted dies. Each reconstituted die can be located within a respective unit area UA2, and can include a semiconductor interposer semi-finished product 600', a die interposer assembly 300, at least one memory die 400, and a mold compound multi-die frame 505. The illustrated portion of the example structure corresponds to a unit area UA2, i.e., an area that includes a single repeating unit within the reconstituted wafer.

[0101] Referring to Figure 13 The reconstituted wafer can be thinned from the backside. In particular, a backside portion of the semiconductor wafer that includes the array of interposer semiconductor substrates 510 can be removed by performing a thinning process. The thinning process can use a grinding process, a polishing process, an anisotropic etching process, and / or an isotropic etching process. The thinning process can be continued until the backside surfaces of the second TSV structures 620 are physically exposed. Subsequently, a backside redistribution structure can be formed on the semiconductor wafer and the physically exposed backside surfaces of the second TSV structures 620. The backside redistribution structure can include a backside redistribution dielectric layer 670 and backside redistribution lines 680.

[0102] A backside bump structure 694 can be formed on the last layer of the backside redistribution lines 680. The backside bump structure 694 can include a micro bump structure or a C4 bond pad. A solder portion 698 can be formed on the backside bump structure 694. Upon thinning the semiconductor wafer and upon forming the backside redistribution structure, the backside bump structure 694, and the solder portion 698, the semiconductor interposer semi-finished product 600' is converted into a semiconductor interposer, which is referred to herein as a second semiconductor interposer 600.

[0103] A reconstituted wafer can be cut along the cut channel. Each cut portion of the reconstituted wafer includes a third stage compound package that includes an assembly of a second semiconductor interposer 600, a die interposer assembly 300, at least one memory die 400, and a molded compound multi-die frame 505.

[0104] Referring to Figure 14 , a first assembly of a third stage compound package and a package substrate 800 is shown. The package substrate 800 can be a core package substrate that includes a core substrate 810 or a coreless package substrate that does not include a package core. Alternatively, the package substrate 800 can include a system-on-integrated packaging substrate (SoIS) that includes a redistribution layer, a dielectric interposer, and / or at least one embedded interposer (e.g., a silicon interposer). Such a system-on-integrated packaging substrate can include layer-to-layer interconnections using solder portions, micro-bumps, underfill material portions (e.g., molded underfill material portions), and / or adhesive films. While the present disclosure is described using a core package substrate, it should be understood that the scope of the present disclosure is not limited to any particular type of substrate package. For example, a SoIS can be used in place of a core package substrate. In embodiments using a SoIS, the core substrate 810 can include a glass epoxy board that includes an array of board vias. An array of core via structures 820 including a metallic material can be provided in the board vias. Each core via structure 820 can or can not include a cylindrical hollow portion therein. A dielectric spacer (not shown) can optionally be used to electrically isolate the core via structures 820 from the core substrate 810.

[0105] The package substrate 800 can include a board-side surface laminar circuit (SLC) 840 and a chip-side surface laminar circuit (SLC) 830. The board-side SLC 840 can include a board-side insulating layer 842 that has board-side wiring interconnects 846 embedded therein. The chip-side SLC 830 can include a chip-side insulating layer 832 that has chip-side wiring interconnects 836 embedded therein. The board-side insulating layer 842 and the chip-side insulating layer 832 can include a photo- patternable and then cured photoactive epoxy material. The board-side wiring interconnects 846 and the chip-side wiring interconnects 836 can include copper that can be deposited by electroplating within a pattern in the board-side insulating layer 842 or the chip-side insulating layer 832.

[0106] In an embodiment, the chip-side surface build-up circuitry 830 includes chip-side wire interconnects 836 connected to an array of substrate bond pads 838. The array of substrate bond pads 838 can be configured to allow for bonding by C4 solder balls. The board-side surface build-up circuitry 840 includes board-side wire interconnects 846 connected to an array of board-side bond pads 848. The array of board-side bond pads 848 is configured to allow for bonding by solder joints having a size larger than C4 solder balls. While the present disclosure is described using an embodiment of the package substrate 800 including both the chip-side surface build-up circuitry 830 and the board-side surface build-up circuitry 840, embodiments are expressly contemplated herein in which one of the chip-side surface build-up circuitry 830 and the board-side surface build-up circuitry 840 is omitted or replaced by an array of bonding structures, such as micro-bumps. In illustrative examples, the chip-side surface build-up circuitry 830 can be replaced by an array of micro-bumps or any other array of bonding structures.

[0107] The third-stage composite package, which includes the second semiconductor interposer 600, the die interposer assembly 300, the at least one memory die 400, and the assembly of the mold compound multi-die frame 505, can be bonded to the package substrate 800 by the solder portions 698. In this embodiment, each solder portion 698 can be bonded to a respective pair of backside bump structures 694 and substrate bond pads 838. Integrated passive components, such as 871, 872, can be selectively bonded to the chip-side surface build-up circuitry 830 and / or the board-side surface build-up circuitry 840. For example, a chip-side integrated passive component 871 can be bonded to the chip-side surface build-up circuitry 830, and a board-side integrated passive component 872 can be bonded to the board-side surface build-up circuitry 840. A stabilization structure 860, such as a stabilization ring or stabilization lid structure, can be selectively attached to the package substrate 800 using an adhesive layer 861.

[0108] A underfill material portion 890 can be formed within each cell region between the second semiconductor interposer 600 and the package substrate 800. The underfill material portion 890 can be formed by injecting a die-side underfill material around the respective arrays of backside bump structures 694 and solder portions 698 in the respective cell regions. Any known method of application of underfill material can be used, which can be, for example, a capillary underfill method, a molded underfill method, or a printed underfill method.

[0109] Within each cell region, the underfill material portion 890 can laterally surround and contact a respective set of solder portions 790 within the cell region. A die-side underfill material portion 792 can be formed around and contact the backside bump structures 694 and the solder portions 698 in the cell region.

[0110] The solder balls 898 can be attached to the bottom side of the package substrate 800 for coupling to a printed circuit board (not shown).

[0111] Referring to Figure 15 , a third-stage composite package and a second assembly of the package substrate 800 is shown. The second assembly can be derived from the first assembly shown in Figure 15 by modifying the die interposer assembly 300. In this embodiment, the fan-out semiconductor package 290 can be formed without a dummy die 201 therein. Alternatively or additionally, the TIV structure 352 can not be used during formation of the die interposer assembly 300. Alternatively or additionally, the second far-end redistribution wiring interconnects 380 and the second far-end redistribution dielectric layer 370 can be omitted.

[0112] Referring to Figure 16 , a third-stage composite package and a third assembly of the package substrate 800 is shown. The third assembly can be derived from the first assembly shown in Figure 15 by modifying the die interposer assembly 300. In this embodiment, the fan-out semiconductor package 290 can be formed without a dummy die 201 therein. Alternatively or additionally, the TIV structure 352 can not be used during formation of the die interposer assembly 300.

[0113] Referring to Figures 13-16According to various embodiments of the present disclosure, a bonded assembly is provided, the bonded assembly including: a first package structure 910 (which can include a die interposer assembly 300) including a first metal interconnect structure 918 (e.g., a first TSV structure 120, a proximal re-routed interconnect 122, a first distal re-routed interconnect 160, and optionally a second distal re-routed interconnect 380), a first metal bump structure 44 (which can include a distal metal bump structure 344) electrically connected to the first metal interconnect structure 918 (e.g., a first TSV structure 120, a proximal re-routed interconnect 122, a first distal re-routed interconnect 160, and optionally a second distal re-routed interconnect 380), and a first polymer bonding layer 49 (which can include a distal polymer bonding layer 349) laterally surrounding the first metal bump structure 44 (which can include a distal metal bump structure 344); a second package structure 920 (which can include a second semiconductor interposer 600) including a second metal interconnect structure 928 (which can include a second TSV structure 620), a second metal bump structure 54 (which can include a silicon interposer metal bump structure 654) electrically connected to the second metal interconnect structure 928 (which can include a second TSV structure 620), and a second polymer bonding layer 59 (which can include a silicon interposer polymer bonding layer 659) laterally surrounding the second metal bump structure 54 (which can include a silicon interposer metal bump structure 654); and a solder portion 48 (which can include a second solder portion 348) between the first metal bump structure 44 (which can include a distal metal bump structure 344) and the second metal bump structure 54 (which can include a silicon interposer metal bump structure 654). Each solder portion 48 (which can include a second solder portion 348) is bonded to a respective one of the first metal bump structure 44 (which can include a distal metal bump structure 344) and the second metal bump structure 54 (which can include a silicon interposer metal bump structure 654), and the second polymer bonding layer 59 (which can include a silicon interposer polymer bonding layer 659) is bonded to the first polymer bonding layer 49 (which can include a distal polymer bonding layer 349) by polymer-to-polymer bonding.

[0114] In an embodiment, the first package structure 910 (which can include the die interposer assembly 300) includes a first semiconductor substrate 110 including a substrate via structure 120 through the first semiconductor substrate 110, where the first metal interconnect structure 918 (e.g., the first TSV structure 120, the proximal re-routed interconnect 122, the first distal re-routed interconnect 160, and optionally the second distal re-routed interconnect 380) includes the substrate via structure 120. In an embodiment, the first package structure 910 (which can include the die interposer assembly 300) is laterally surrounded by a mold compound frame (e.g., the mold compound interposer frame 335) that laterally surrounds the first semiconductor substrate 110.

[0115] In an embodiment, the first metal interconnect structure 918 (e.g., the first TSV structure 120, the proximal re-routed interconnect 122, the first distal re-routed interconnect 160, and optionally the second distal re-routed interconnect 380) includes a first re-routed interconnect (e.g., the first distal re-routed interconnect 160) embedded in a first re-routed dielectric layer (e.g., the first distal re-routed dielectric layer 150), and the first re-routed dielectric layer (e.g., the first distal re-routed dielectric layer 150) is laterally surrounded by a mold compound frame (e.g., the mold compound interposer frame 335).

[0116] In an embodiment, the first metal interconnect structure 918 (e.g., the first TSV structure 120, the proximal re-routed interconnect 122, the first distal re-routed interconnect 160, and optionally the second distal re-routed interconnect 380) includes a second re-routed interconnect (e.g., the second distal re-routed interconnect 380) formed within a second re-routed dielectric layer (e.g., the second distal re-routed dielectric layer 370), and the second re-routed dielectric layer (e.g., the second distal re-routed dielectric layer 370) includes a horizontal surface that contacts the mold compound frame (e.g., the mold compound interposer frame 335) and includes a sidewall that is vertically coincident with an outer sidewall of the mold compound frame (e.g., the mold compound interposer frame 335).

[0117] In an embodiment, the second package structure 920 includes a second semiconductor interposer 600 that includes an additional semiconductor substrate (e.g., the interposer semiconductor substrate 510) and an additional substrate via structure (e.g., the second TSV structure 620) and has a greater lateral extent than the first semiconductor substrate 110 of the first package structure 910 (which can include the die interposer assembly 300).

[0118] In an embodiment, the horizontal interface distance between the second polymer bonding layer 59 (which can include a silicon interposer polymer bonding layer 659) and the first polymer bonding layer 49 (which can include a distal polymer bonding layer 349) includes a horizontal plane that includes a proximal horizontal surface of the first semiconductor substrate 110 of the first package structure 910 (which can include a die interposer assembly 300) is farther than the interface distance between the solder portion 48 (which can include a second solder portion 348) and the second metal bump structure 54 (which can include a silicon interposer metal bump structure 654) from the proximal horizontal surface of the first semiconductor substrate 110 of the first package structure 910 (which can include a die interposer assembly 300).

[0119] In an embodiment, each solder portion 48 (which can include a second solder portion 348) is laterally surrounded by and in contact with the first polymer bonding layer 49 (which can include a distal polymer bonding layer 349). In an embodiment, the second polymer bonding layer 59 (which can include a silicon interposer polymer bonding layer 659) is spaced apart from and not in contact with the solder portion 48 (which can include a second solder portion 348). In an embodiment, the first polymer bonding layer 49 (which can include a distal polymer bonding layer 349) is spaced apart from and not in contact with the second package structure 920 (which can include a second semiconductor interposer 600), and the second polymer bonding layer 59 (which can include a silicon interposer polymer bonding layer 659) is spaced apart from and not in contact with the first package structure 910 (which can include a die interposer assembly 300).

[0120] According to another aspect of the present disclosure, there is provided a bonded assembly, comprising: a first package structure 910 (which can comprise a die interposer assembly 300) including a first metal interconnect structure 918 (e.g., a first TSV structure 120, a proximal re-routed interconnect 122, a first distal re-routed interconnect 160, and optionally a second distal re-routed interconnect 380), a first metal bump structure 44 (which can comprise a distal metal bump structure 344) electrically connected to the first metal interconnect structure 918 (e.g., a first TSV structure 120, a proximal re-routed interconnect 122, a first distal re-routed interconnect 160, and optionally a second distal re-routed interconnect 380), and a first polymer bonding layer 49 (which can comprise a distal polymer bonding layer 349) laterally surrounding the first metal bump structure 44 (which can comprise a distal metal bump structure 344); a second package structure 920 (which can comprise a second semiconductor interposer 600) including a second metal interconnect structure 928 (which can comprise a second TSV structure 620), a second metal bump structure 54 (which can comprise a silicon interposer metal bump structure 654) electrically connected to the second metal interconnect structure 928 (which can comprise a second TSV structure 620), and a second polymer bonding layer 59 (which can comprise a silicon interposer polymer bonding layer 659) laterally surrounding the second metal bump structure 54 (which can comprise a silicon interposer metal bump structure 654); and a solder portion 48 (which can comprise a second solder portion 348) between the first metal bump structure 44 (which can comprise a distal metal bump structure 344) and the second metal bump structure 54 (which can comprise a silicon interposer metal bump structure 654). Each solder portion 48 (which can comprise a second solder portion 348) is bonded to a respective one of the first metal bump structure 44 (which can comprise a distal metal bump structure 344) and the second metal bump structure 54 (which can comprise a silicon interposer metal bump structure 654), each solder portion 48 (which can comprise a second solder portion 348) is laterally surrounded by the first polymer bonding layer 49 (which can comprise a distal polymer bonding layer 349) and is not in direct contact with the second polymer bonding layer 59 (which can comprise a silicon interposer polymer bonding layer 659); and the first polymer bonding layer 49 (which can comprise a distal polymer bonding layer 349) is spaced apart from the second package structure 920 (which can comprise a second semiconductor interposer 600) by the second polymer bonding layer 59 (which can comprise a silicon interposer polymer bonding layer 659).

[0121] In an embodiment, the second polymer bonding layer 59 (which can include a silicon interposer polymer bonding layer 659) can be bonded to the first polymer bonding layer 49 (which can include a distal polymer bonding layer 349) by polymer-to-polymer bonding. In an embodiment, the first package structure 910 (which can include a die interposer assembly 300) includes the first semiconductor substrate 110, and a horizontal distance of an interface of bonding between the first polymer bonding layer 49 (which can include a distal polymer bonding layer 349) and the second polymer bonding layer 59 (which can include a silicon interposer polymer bonding layer 659) includes a horizontal surface of a proximal horizontal surface of the first semiconductor substrate 110 is further than a horizontal distance of an interface between the solder portion 48 (which can include a second solder portion 348) and the second metal bump structure 54 (which can include a silicon interposer metal bump structure 654) includes a horizontal surface of a proximal horizontal surface of the first semiconductor substrate 110.

[0122] Figure 17 is a flowchart showing steps for forming a bonded assembly according to embodiments of the present disclosure.

[0123] Referring to steps 1710 and Figure 4 , Figures 5A-5D and Figures 6-9 , a first package structure 910 (which can include a first semiconductor interposer 100 or as a die interposer assembly 300) is provided, the first package structure 910 including a first metal interconnect structure 918 (such as a first TSV structure 120, a proximal rewiring interconnect 122, a first distal rewiring interconnect 160, and optionally a second distal rewiring interconnect 380), a first metal bump structure 44 (which can include a proximal metal bump structure 144 or a distal metal bump structure 344) electrically connected to the first metal interconnect structure 918 (such as a first TSV structure 120, a proximal rewiring interconnect 122, a first distal rewiring interconnect 160, and optionally a second distal rewiring interconnect 380), a solder portion 48 (which can include a first solder portion 148 or a second solder portion 348) bonded to the first metal bump structure 44 (which can include a proximal metal bump structure 144 or a distal metal bump structure 344), and a first polymer bonding layer 49 (which can include a proximal polymer bonding layer 149 or a distal polymer bonding layer 349) laterally surrounding the first metal bump structure 44 (which can include a proximal metal bump structure 144 or a distal metal bump structure 344) and the solder portion 48 (which can include a first solder portion 148 or a second solder portion 348).

[0124] Referring to steps 1720 and Figures 1-3 , Figures 5E-5G and Figure 10, a second package structure 920 (e.g., a fan-out semiconductor package 290 or a semiconductor interposer semi-finished product 600') is provided, the second package structure 920 including a second metal interconnect structure 928 (which can include the metal interconnect structure 222, the die-side bond pad 224, the fan-out rewiring interconnect 340, or the second TSV structure 620), a second metal bump structure 54 (which can include the fan-out metal bump structure 354 or the silicon interposer metal bump structure 654) electrically connected to the second metal interconnect structure 928 (which can include the metal interconnect structure 222, the die-side bond pad 224, the fan-out rewiring interconnect 340, or the second TSV structure 620), and a second polymer bonding layer 59 (which can include the fan-out polymer bonding layer 359 or the silicon interposer polymer bonding layer 659) laterally surrounding the second metal bump structure 54 (which can include the fan-out metal bump structure 354 or the silicon interposer metal bump structure 654).

[0125] Referring to step 1730 and Figure 4 、 Figure 5H 、 Figure 5I and Figures 11-16 The second metal bump structure 54 (which can include the fan-out metal bump structure 354 or the silicon interposer metal bump structure 654) can be bonded to the first metal bump structure 44 (which can include the proximal metal bump structure 144 or the distal metal bump structure 344) by performing a bonding process in which the solder portion 48 (which can include the first solder portion 148 or the second solder portion 348) is reflowed while the second polymer bonding layer 59 (which can include the fan-out polymer bonding layer 359 or the silicon interposer polymer bonding layer 659) contacts the first polymer bonding layer 49 (which can include the proximal polymer bonding layer 149 or the distal polymer bonding layer 349).

[0126] Various embodiments of the present disclosure can be used to provide hybrid bonded structures in which the first package structure 910 and the second package structure 920 are bonded to one another using both solder bonding and polymer-to-polymer bonding. The hybrid bonding of the present disclosure provides enhanced bonding strength between the first package structure 910 and the second package structure 920 as compared to bonded assemblies that use only solder bonding. The strength of the polymer-to-polymer bonding can be enhanced by selecting a pair of polymer materials that can provide enhanced adhesion strength, such as by forming a dual-constituent adhesive material (e.g., an epoxy resin).

[0127] The features of several embodiments were summarized above to enable a person of ordinary skill in the art to better understand the various aspects of the present disclosure. Unless explicitly disclosed otherwise herein, each embodiment described using the term "comprising" is inherently disclosed with the term "consisting essentially of" or the term "consisting of" in some embodiments. Whenever two or more components are listed in the same paragraph or different paragraphs as alternatives, Markush groups consisting of the listed two or more components in some embodiments are also implicitly disclosed. Whenever a helping verb "can" is used in the present disclosure to describe the formation of a component or the performance of a processing step, embodiments in which the component is not formed or the processing step is not performed are also explicitly contemplated, as long as the resulting device or apparatus can provide equivalent results. Therefore, whenever the helping verb "can" is applied to the formation of a component or the performance of a processing step, it should also be interpreted as "may or can not" as long as equivalent results can be provided, including slightly better results and slightly worse results. The above embodiments are merely used to illustrate the technical solutions of the embodiments of the present application, and are not intended to limit the present application; although the embodiments of the present application have been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements for some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A bonded assembly, comprising: Comprising: a first package structure comprising: a plurality of first metal interconnect structures; a plurality of first metal bump structures electrically connected to the first metal interconnect structures; and a first polymer bonding layer laterally surrounding the first metal bump structures; a second package structure comprising: a plurality of second metal interconnect structures; a plurality of second metal bump structures electrically connected to the second metal interconnect structures; and a second polymer bonding layer laterally surrounding the second metal bump structures; and a plurality of solder portions between the first metal bump structures and the second metal bump structures, wherein: each of the solder portions is bonded to a respective one of the first metal bump structures and a respective one of the second metal bump structures; and the second polymer bonding layer is bonded to the first polymer bonding layer by polymer-to-polymer bonding.

2. The engaged assembly of claim 1, wherein, wherein the first package structure comprises a semiconductor substrate comprising a plurality of substrate via structures through the semiconductor substrate, wherein the first metal interconnect structures comprise the substrate via structures.

3. The engaged assembly of claim 2, wherein, wherein the first package structure is laterally surrounded by a mold compound frame laterally surrounding the semiconductor substrate.

4. The engaged assembly of claim 2, wherein, wherein a horizontal bonding interface between the second polymer bonding layer and the first polymer bonding layer is further from a proximal horizontal surface of the semiconductor substrate comprising the first package structure than a plurality of interfaces between the solder portions and the second metal bump structures.

5. The engaged assembly of claim 1, wherein, wherein each of the solder portions is laterally surrounded by and contacted by the first polymer bonding layer.

6. The engaged assembly of claim 1, wherein, wherein the second polymer bonding layer is spaced apart from and not in contact with the solder portions.

7. The engaged assembly of claim 1, wherein, wherein: the first polymer bonding layer is spaced apart from and not in contact with the second package structure; and the second polymer bonding layer is spaced apart from and not in contact with the first package structure.

8. A bonded assembly, comprising: Comprising: a first package structure comprising: a plurality of first metal interconnect structures; a plurality of first metal bump structures electrically connected to the first metal interconnect structures; and a first polymer bonding layer laterally surrounding the first metal bump structures; a second package structure comprising: a plurality of second metal interconnect structures; a plurality of second metal bump structures electrically connected to the second metal interconnect structures; and a second polymer bonding layer laterally surrounding the second metal bump structures; and a plurality of solder portions between the first metal bump structures and the second metal bump structures, wherein: each of the solder portions is bonded to a respective one of the first metal bump structures and a respective one of the second metal bump structures, each of the solder portions is laterally surrounded by the first polymer bonding layer and not in direct contact with the second polymer bonding layer; and the first polymer bonding layer is spaced apart from the second package structure by the second polymer bonding layer.

9. The engaged assembly of claim 8, wherein, wherein the second polymer bonding layer is bonded to the first polymer bonding layer by polymer-to-polymer bonding.

10. The engaged assembly of claim 8, wherein, wherein: the first package structure includes a semiconductor substrate; and a horizontal plane of a bonding interface included between the first polymer bonding layer and the second polymer bonding layer is farther from a horizontal plane of a proximal horizontal surface of the semiconductor substrate than a horizontal plane of a plurality of interfaces included between the solder portion and the second metal bump structure.

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