Gate driver and display device including the same

Abstract

The utility model relates to a gate driver and a display device including the same. The gate driver includes at least one stage including: a first transistor including a control electrode receiving a first clock signal, a first electrode receiving a gate signal of a previous stage, and a second electrode connected to a first node; a third transistor including a control electrode directly receiving the first clock signal, a first electrode receiving the first power voltage, and a second electrode connected to a third node; a fourth transistor including a control electrode connected to the second node, a first electrode receiving a second clock signal different from the first clock signal, and a second electrode connected to the third node; and a first capacitor including a first electrode connected to the second node and a second electrode connected to the third node, in which the at least one stage outputs a voltage of the third node as a gate signal.

Description

TECHNICAL FIELD

[0001] Aspects of some embodiments of the present disclosure relate to display apparatuses. BACKGROUND

[0002] Generally, a display apparatus includes a display panel and a display panel driver for driving the display panel. The display panel includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels. The display panel driver can include a gate driver that provides a gate signal to the gate lines and a data driver that provides a data voltage to the data lines.

[0003] Generally, the gate driver can include a plurality of transistors and a plurality of capacitors, such that it is possible to relatively increase a bezel size of the display apparatus.

[0004] The above information disclosed in this Background section is only for enhancing the understanding of the background of the disclosure, and therefore it can not necessarily be construed as known art known to those skilled in the art. SUMMARY

[0005] Aspects of some embodiments of the present disclosure relate to display apparatuses. For example, aspects of some embodiments of the present disclosure relate to a gate driver and a display apparatus including the gate driver.

[0006] Aspects of some embodiments include a gate driver having a relatively improved integration.

[0007] Aspects of some embodiments can further include a display apparatus including the gate driver.

[0008] According to some embodiments, the gate driver includes a plurality of stages. At least one stage of the plurality of stages includes: a first transistor including a control electrode configured to directly receive a first clock signal, a first electrode configured to receive a previous stage gate signal, and a second electrode connected to a first node; a third transistor including a control electrode configured to directly receive the first clock signal, a first electrode configured to receive a first power voltage, and a second electrode connected to a third node; a fourth transistor including a control electrode connected to a second node, a first electrode configured to receive a second clock signal different from the first clock signal, and a second electrode connected to the third node; and a first capacitor including a first electrode connected to the second node and a second electrode connected to the third node. According to some embodiments, the at least one stage outputs a voltage of the third node as a gate signal.

[0009] According to some embodiments, the at least one stage can further include: a second transistor including a control electrode configured to receive a second power voltage different from the first power voltage, a first electrode connected to the first node, and a second electrode connected to the second node.

[0010] According to some embodiments, a ratio of a channel width to a channel length of the third transistor is different from a ratio of a channel width to a channel length of the fourth transistor.

[0011] According to some embodiments, a channel width of the third transistor can be narrower than a channel width of the fourth transistor.

[0012] According to some embodiments, the fourth transistor can be turned on based on the previous stage gate signal having an activation level in a first time period.

[0013] According to some embodiments, in a second time period after the first time period, the first clock signal can have a deactivation level, the second clock signal can have an activation level, and a voltage of the second node can be lower than a low voltage of the second clock signal.

[0014] According to some embodiments, in a third time period after the second time period, the first clock signal can have an activation level, the second clock signal can have a deactivation level, and the gate signal has a deactivation level.

[0015] According to some embodiments, the at least one stage can further include a second transistor including a control electrode configured to receive a second power voltage different from the first power voltage, a first electrode connected to the first node, and a second electrode connected to the second node. According to some embodiments, a channel length of the first transistor can be longer than a channel length of the second transistor.

[0016] According to some embodiments, the gate driver includes a plurality of stages. At least one stage of the stages includes a first transistor configured to apply a previous stage gate signal to a first node in response to a first clock signal, a second transistor connected between the first node and a second node, a third transistor configured to directly receive the first clock signal and configured to apply a first power voltage to a third node, a fourth transistor configured to apply a second clock signal different from the first clock signal to the third node in response to a voltage of the second node, and a first capacitor connected between the second node and the third node. According to some embodiments, the at least one stage outputs a voltage of the third node as a gate signal.

[0017] According to some embodiments, a display device includes a display panel, a gate driver, and a data driver. According to some embodiments, the gate driver outputs a gate signal to a gate line of the display panel. According to some embodiments, the data driver outputs a data voltage to a data line of the display panel. According to some embodiments, the gate driver includes a plurality of stages. According to some embodiments, at least one stage of the plurality of stages includes: a first transistor including a control electrode configured to receive a first clock signal, a first electrode configured to receive a start signal, and a second electrode connected to a first node; a second transistor including a control electrode configured to receive a second power voltage, a first electrode connected to the first node, and a second electrode connected to a second node; a third transistor including a control electrode configured to directly receive the first clock signal, a first electrode configured to receive a first power voltage different from the second power voltage, and a second electrode connected to a third node; a fourth transistor including a control electrode connected to the second node, a first electrode configured to receive a second clock signal different from the first clock signal, and a second electrode connected to the third node; and a first capacitor including a first electrode connected to the second node and a second electrode connected to the third node. According to some embodiments, the at least one stage outputs a voltage of the third node as the gate signal.

[0018] In the gate driver and the display device according to some embodiments, compared to an alternative gate driver, by including a smaller number of transistors and a smaller number of capacitors, the integration of the display device can be relatively improved, and the bezel size of the display device becomes relatively smaller.

[0019] In addition, the ratio of the channel width (W) to the channel length (L) of any one of the transistors included in the gate driver can be variable, so that the bezel size of the display device can become smaller. BRIEF DESCRIPTION OF DRAWINGS

[0020] Aspects of some embodiments of the present disclosure will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, by the way of which:

[0021] Figure 1 is a block diagram illustrating a display device according to some embodiments.

[0022] Figure 2 is a block diagram illustrating a gate driver included in the display device of Figure 1 according to some embodiments.

[0023] Figure 3 is a circuit diagram illustrating the gate driver of Figure 2 according to some embodiments.

[0024] Figure 4 is a block diagram illustrating a gate driver included in the display device ofFigure 1 a circuit diagram of a pixel circuit in the display apparatus of FIG. 1.

[0025] Figure 5 is a timing diagram illustrating operation of the gate driver of FIG. 1 in a first time period, according to some embodiments. Figure 2

[0026] Figure 6 is a circuit diagram of the gate driver of FIG. 1, according to some embodiments. Figure 2 is a circuit diagram of the gate driver of FIG. 1 in a first time period, according to some embodiments.

[0027] Figure 7 is a circuit diagram of the gate driver of FIG. 1 in a second time period, according to some embodiments. Figure 2

[0028] Figure 8 is a circuit diagram of the gate driver of FIG. 1 in a third time period, according to some embodiments. Figure 2

[0029] Figure 9 is a circuit diagram of the gate driver of FIG. 1, according to some embodiments. Figure 2

[0030] Figure 10 is a circuit diagram of the gate driver of FIG. 1, according to some embodiments. Figure 2

[0031] Figure 11 is a circuit diagram of the gate driver of FIG. 1, according to some embodiments. Figure 2

[0032] Figure 12 is a block diagram illustrating an electronic device, according to some embodiments; and

[0033] Figure 13 is a diagram illustrating an example in which the electronic device of FIG. 1 is implemented as a smart phone, according to some embodiments. Figure 12 DETAILED DESCRIPTION

[0034] Hereinafter, aspects of some embodiments of the present disclosure will be described in greater detail with reference to the accompanying drawings.

[0035] Figure 1 is a block diagram illustrating a display apparatus, according to some embodiments.

[0036] Referring to FIG. 1, Figure 1 the display apparatus includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500.

[0037] ​​​​​​​For example, the driving controller 200 and the data driver 500 can be integrally formed (e.g., integrally formed as a single component). For example, the driving controller 200, the gamma reference voltage generator 400, and the data driver 500 can be integrally formed (e.g., integrally formed as a single component). A driving module including at least the integrally formed driving controller 200 and the data driver 500 can be referred to as a timing controller-embedded data driver (TED).

[0038] The display panel 100 includes a display area configured to display an image and a peripheral area adjacent to the display area (e.g., at a periphery of the display area). For example, the peripheral area can be referred to as a bezel.

[0039] The display panel 100 includes a plurality of gate lines GL, a plurality of data lines DL, and a plurality of pixels electrically connected to the gate lines GL and the data lines DL, respectively. The gate lines GL can extend in a first direction D1, and the data lines DL can extend in a second direction D2 crossing the first direction D1.

[0040] The driving controller 200 receives input image data IMG and input control signals CONT from an external device. For example, the input image data IMG can include red image data, green image data, and blue image data. The input image data IMG can include white image data. The input image data IMG can include magenta image data, yellow image data, and cyan image data. The input control signals CONT can include a main clock signal and a data enable signal. The input control signals CONT can further include a vertical synchronization signal and a horizontal synchronization signal.

[0041] The driving controller 200 generates first control signals CONT1, second control signals CONT2, third control signals CONT3, and data signals DATA based on the input image data IMG and the input control signals CONT.

[0042] The driving controller 200 generates the first control signals CONT1 for controlling operations of the gate driver 300 based on the input control signals CONT, and outputs the generated first control signals CONT1 to the gate driver 300. The first control signals CONT1 can include a start signal and a gate clock signal.

[0043] The driving controller 200 generates the second control signals CONT2 for controlling operations of the data driver 500 based on the input control signals CONT, and outputs the generated second control signals CONT2 to the data driver 500.

[0044] The second control signals CONT2 can include a horizontal start signal and a load signal.

[0045] The drive controller 200 generates a data signal DATA based on the input image data IMG, and outputs the generated data signal DATA to the data driver 500.

[0046] The drive controller 200 generates a third control signal CONT3 for controlling the operation of the gamma reference voltage generator 400 based on the input control signal CONT, and outputs the generated third control signal CONT3 to the gamma reference voltage generator 400.

[0047] The gate driver 300 generates a gate signal GW[n] for driving the gate line GL in response to the first control signal CONT1 received from the drive controller 200. The gate driver 300 can output the gate signal GW[n] to the gate line GL. For example, the gate driver 300 can sequentially output the gate signal GW[n] to the gate line GL. For example, the gate driver 300 can be mounted on a peripheral area of the display panel 100. For example, the gate driver 300 can be integrated on a peripheral area of the display panel 100.

[0048] The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to the third control signal CONT3 received from the drive controller 200. The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500.

[0049] For example, the gamma reference voltage generator 400 can be located in the drive controller 200 or the data driver 500.

[0050] The data driver 500 receives the second control signal CONT2 and the data signal DATA from the drive controller 200, and receives the gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 can convert the data signal DATA into a data voltage VDATA in an analog form by using the gamma reference voltage VGREF. The data driver 500 outputs the data voltage VDATA to the data line DL.

[0051] Figure 2 is a block diagram illustrating the gate driver 300 included in a display apparatus of Figure 1 .

[0052] Referring to Figure 1 and Figure 2 , the gate driver 300 can include a plurality of stages STAGE 1, STAGE 2, STAGE 3, STAGE 4,... in which a start signal FLM, a first clock signal CLK1, and a second clock signal CLK2 are received and sequentially output gate signals GW[1], GW[2], GW[3], GW[4],... to a plurality of pixels row by row.

[0053] The first clock signal CLK1 and the second clock signal CLK2 can be applied to the first clock terminal CLK1T and the second clock terminal CLK2T of the first stage STAGE 1, respectively. The first clock signal CLK1 and the second clock signal CLK2 can be applied to the second clock terminal CLK2T and the first clock terminal CLK1T of the second stage STAGE 2, respectively. Likewise, the first clock signal CLK1 and the second clock signal CLK2 can be applied to the first clock terminal CLK1T and the second clock terminal CLK2T of the third stage STAGE 3, respectively. The first clock signal CLK1 and the second clock signal CLK2 can be applied to the second clock terminal CLK2T and the first clock terminal CLK1T of the fourth stage STAGE 4, respectively.

[0054] Figure 3 is a circuit diagram of a gate driver 300 according to some embodiments. Figure 2 Although Figure 3 various components of the gate driver 300 according to some embodiments are illustrated, embodiments according to the present disclosure are not limited thereto, and the gate driver 300 can include additional components or fewer components according to some embodiments without departing from the spirit and scope of embodiments according to the present disclosure.

[0055] Referring to Figure 3 , the gate driver 300 can include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a first capacitor C1. The gate driver 300 can be a 4T1C structure including four transistors and one capacitor. For example, the transistors can include a control electrode (e.g., a gate electrode), a first electrode (e.g., one of a source electrode and a drain electrode), and a second electrode (e.g., one of a source electrode and a drain electrode).

[0056] According to some embodiments, the first transistor can include a control electrode configured to receive a first clock signal CLK1, a first electrode configured to receive a previous stage gate signal GW[n-1], and a second electrode connected to the first node Q1. The first transistor T1 can apply the previous stage gate signal GW[n-1] to the first node Q1 in response to the first clock signal CLK1. For example, the first clock signal CLK1 and the second clock signal CLK2 can be switched between a high voltage and a low voltage. For example, the first clock signal CLK1 and the second clock signal CLK2 can be switched between a first power voltage VGH and a second power voltage VGL. For example, the first power voltage VGH can be a high voltage. For example, the second power voltage VGL can be a low voltage. For example, the high voltage can be about 6 V. However, embodiments according to the present disclosure are not limited to the value of the high voltage. The second power voltage VGL can be a low voltage. The second power voltage VGL can be lower than the first power voltage VGH. For example, the low voltage can be about -6 V. However, embodiments according to the present disclosure are not limited to the value of the low voltage.

[0057] According to some embodiments, a channel length (L) of the first transistor T1 can be longer than a channel length of the second transistor T2. Accordingly, stability and reliability of the gate driver 300 can be relatively more improved.

[0058] According to some embodiments, the second transistor T2 can include a control electrode configured to receive the second power voltage VGL, a first electrode connected to the first node Q1, and a second electrode connected to the second node Q2. The second transistor T2 can apply a voltage of the first node Q1 to the second node Q2 in response to the second power voltage VGL.

[0059] According to some embodiments, the third transistor T3 can include a control electrode configured to receive the first clock signal CLK1, a first electrode configured to receive the first power voltage VGH, and a second electrode connected to the third node Q3. The third transistor T3 can apply the first power voltage VGH to the third node Q3 in response to the first clock signal CLK1.

[0060] According to some embodiments, the first clock signal CLK1 can be directly applied to the control electrode of the third transistor T3. Accordingly, integration of the gate driver 300 can be relatively improved compared to a gate driver of a conventional display apparatus. In addition, a bezel size of a display apparatus according to the present disclosure can become relatively small.

[0061] According to some embodiments, a ratio (W / L) between a channel width (W) and a channel length of the third transistor T3 can be different from a ratio between a channel width and a channel length of the fourth transistor T4. For example, the channel width of the third transistor T3 can be shorter than the channel width of the fourth transistor T4. Accordingly, the size of the third transistor T3 can be reduced. The size of the third transistor T3 can be reduced so that the integration of the gate driver 300 can be relatively increased. Accordingly, the bezel size of the display apparatus according to the disclosure can become even smaller.

[0062] According to some embodiments, the fourth transistor T4 can include a control electrode connected to the second node Q2, a first electrode configured to receive the second clock signal CLK2, and a second electrode connected to the third node Q3. The fourth transistor T4 can apply the second clock signal CLK2 to the third node Q3 in response to the voltage of the second node Q2. For example, the phase of the second clock signal CLK2 can be opposite to the phase of the first clock signal CLK1.

[0063] According to some embodiments, the first capacitor C1 can include a first electrode connected to the second node Q2 and a second electrode connected to the third node Q3. The first capacitor C1 can couple a change in the voltage of the third node Q3 and can apply the change in the voltage of the third node Q3 to the second node Q2. For example, the coupling operation of the first capacitor C1 can be referred to as a bootstrap operation. Through the coupling operation of the first capacitor C1, the stability and reliability of the gate driver 300 can be relatively increased.

[0064] According to some embodiments, the gate driver 300 can output the voltage of the third node Q3 as a gate signal GW[n]. For example, the gate signal GW[n] can have an activation level or a deactivation level.

[0065] Figure 4 is a circuit diagram illustrating a pixel circuit PX included in a display apparatus according to the disclosure. Figure 1 Although the pixel circuit PX according to the disclosure is not limited thereto, the pixel circuit PX according to some embodiments can include additional components or fewer components without departing from the spirit and scope of the embodiments according to the disclosure. Figure 4 FIG. 1 illustrates various components of a pixel circuit PX according to some embodiments, but embodiments according to the disclosure are not limited thereto, and the pixel circuit PX can include additional components or fewer components without departing from the spirit and scope of the embodiments according to the disclosure.

[0066] Referring to Figure 4 , the pixel circuit PX can include a first pixel transistor PT1, a second pixel transistor PT2, a storage capacitor CST, and a light emitting element EE. For example, the pixel circuit PX can have a 2T1C structure. However, embodiments according to the disclosure are not limited to the structure of the pixel circuit PX.

[0067] The first pixel transistor PT1 can include a control electrode configured to receive a gate signal GW[n], a first electrode configured to receive a data voltage VDATA, and a second electrode connected to the first pixel node P1. The first pixel transistor PT1 can apply the data voltage VDATA to a control electrode of the second pixel transistor PT2 in response to the gate signal GW[n].

[0068] The second pixel transistor PT2 can include a control electrode connected to the first pixel node P1, a first electrode configured to receive a high power voltage VDD, and a second electrode connected to the second pixel node P2. The second pixel transistor PT2 can output a driving current in response to a voltage of the first pixel node P1.

[0069] The storage capacitor CST can include a first electrode configured to receive the high power voltage VDD and a second electrode connected to the first pixel node P1. The storage capacitor CST can store the voltage of the first pixel node P1.

[0070] The light emitting element EE can include an anode connected to the second pixel node P2 and a cathode configured to receive a low power voltage VSS. The light emitting element EE can emit light based on the driving current.

[0071] Figure 5 is a timing diagram of the gate driver 300. Figure 2

[0072] Referring to Figure 5 , according to some embodiments, a signal period applied to the gate driver 300 can include a first period TP1, a second period TP2, and a third period TP3.

[0073] According to some embodiments, in the first period TP1, the first clock signal CLK1 can have an activation level, the second clock signal CLK2 can have a deactivation level, and the previous stage gate signal GW[n-1] can have an activation level. For example, the activation level can be a low voltage, and the deactivation level can be a high voltage. For example, the voltage of the activation level can be about -6V, and the voltage of the deactivation level can be about 6V. However, embodiments according to the present disclosure are not limited to the voltage of the activation level and the voltage of the deactivation level. For example, the activation level of an N-type transistor can be a high level, and the deactivation level of the N-type transistor can be a low level.

[0074] According to some embodiments, in the second period TP2, the first clock signal CLK1 can have an activation level, the second clock signal CLK2 can have a deactivation level, and the previous stage gate signal GW[n-1] can have a deactivation level.

[0075] ​According to some embodiments, in the third time period TP3, the first clock signal CLK1 can have an active level, the second clock signal CLK2 can have a deactive level, and the previous stage gate signal GW[n-1] can have a deactive level.

[0076] Figure 6 is a circuit diagram illustrating an operation of the gate driver 300 in the first time period TP1. Figure 2

[0077] Referring to Figure 5 and Figure 6 , the first transistor T1 can be turned on in response to the first clock signal CLK1 having an active level. Accordingly, the previous stage gate signal GW[n-1] having an active level can be applied to the first node Q1 and the second node Q2. For example, the voltage of the first node Q1 can be changed to about -4V. In the first time period TP1, the voltage of the first node Q1 can be changed from a deactive level to an active level. The second transistor T2 can be turned on in response to the second power voltage VGL. The fourth transistor T4 can be turned on in response to the voltage of the second node Q2. Accordingly, the second clock signal CLK2 can be applied to the third node Q3. The third transistor T3 can apply the first power voltage VGH to the third node Q3 in response to the first clock signal CLK1 having an active level. For example, the first power voltage VGH can be about 6V, and the voltage of the third node Q3 can be about 6V.

[0078] According to some embodiments, the gate driver 300 can output the gate signal GW[n] having a deactive level in the first time period TP1.

[0079] Figure 7 is a circuit diagram illustrating an operation of the gate driver 300 in the second time period TP2. Figure 2

[0080] Referring to Figure 5 and Figure 7 ​​In the second period TP2, the first transistor T1 can be turned off in response to the first clock signal CLK1 having the deactivation level. In the second period TP2, the first transistor T1 can be turned off so that the second node Q2 can be in a floating state. The third transistor T3 can be turned off in response to the first clock signal CLK1 having the deactivation level. The fourth transistor T4 can remain in the on state, and the second clock signal CLK2 having the activation level can be applied to the third node Q3. In the second period TP2, the voltage of the third node Q3 can be changed from the deactivation level (i.e., the high voltage) to the activation level (i.e., the low voltage). The first capacitor C1 can couple the change in the voltage of the third node Q3 and can apply the change in the voltage of the third node Q3 to the second node Q2. For example, the voltage applied to the second node Q2 by coupling the change in the voltage of the third node Q3 can be referred to as a bootstrap voltage VGL-ΔV. For example, in the second period TP2, the voltage of the third node Q3 can be changed from about 6V to about -6V, and the voltage of the second node Q2 can be changed from about -4V to about -16V. Accordingly, the fourth transistor T4 can stably apply the second clock signal CLK2 to the third node Q3. Accordingly, the reliability and stability of the gate driver 300 can be relatively improved. According to some embodiments, the gate driver 300 can output the gate signal GW[n] having the activation level.

[0081] According to some embodiments, the activation level period of the first clock signal CLK1 and the second clock signal CLK2 can be longer than the deactivation period of the first clock signal CLK1 and the second clock signal CLK2. Accordingly, the time for performing the coupling operation of the first capacitor C1 in the second period TP2 can be further ensured.

[0082] Figure 8 is a circuit diagram illustrating Figure 2 operation of the gate driver 300 in a third period TP3.

[0083] Referring to Figure 5 and Figure 8 In the third period TP3, the first transistor T1 can be turned on in response to the first clock signal CLK1 having the activation level. The first transistor T1 can apply the previous stage gate signal GW[n-1] having the deactivation level to the first node Q1. Accordingly, the previous stage gate signal GW[n-1] having the deactivation level can be applied to the second node Q2. Accordingly, the fourth transistor T4 can be turned off. In the third period TP3, the third transistor T3 can be turned on in response to the first clock signal CLK1 having the activation level. Accordingly, the third transistor T3 can apply the first power voltage VGH to the third node Q3.

[0084] According to some embodiments, the gate driver 300 can output the gate signal GW[n] having the deactivation level in the third period TP3.

[0085] A conventional gate driver of a display apparatus can include eight transistors and two capacitors. In contrast, the gate driver 300 of the display apparatus according to some embodiments of the disclosure can include four transistors and one capacitor. Accordingly, the integration of the gate driver 300 can be relatively improved, the bezel size of the display apparatus can be reduced, and power consumption can be reduced. In addition, although having fewer transistors and fewer capacitors than an alternative gate driver of a display apparatus, the gate driver 300 according to some embodiments of the disclosure can have similar performance to the alternative gate driver of the display apparatus. Accordingly, the gate driver 300 according to some embodiments of the disclosure can reduce the bezel size without degrading performance.

[0086] Figure 9 is a circuit diagram illustrating the gate driver 300 of Figure 2 according to some embodiments.

[0087] Because the previous stage gate signal GW[n-1] of the gate driver 300A according to Figure 9 is the start signal FLM except that, the same reference numerals will be used to refer to the same elements and any repetitive explanation about the above elements will be omitted. Figure 3

[0088] Referring to Figure 2 and Figure 9 , according to some embodiments, the previous stage gate signal GW[n-1] of the gate driver 300A can be the start signal FLM. For example, the first stage STAGE 1 of the gate driver 300A can output the gate signal GW[n] in response to the start signal FLM. For example, the gate signal GW[n] of the first stage STAGE 1 can be the first gate signal GW[1].

[0089] Figure 10 is a circuit diagram illustrating the gate driver 300 of Figure 2 according to some embodiments.

[0090] Because the gate driver 300B according to Figure 10 is substantially the same as the gate driver 300 of Figure 3 ​The gate driver 300 of FIG. 1A can have a 3T1C structure. The gate driver 300 of FIG. 1A can include the first transistor T1, the second transistor T2, and the first capacitor C1. The gate driver 300 of FIG. 1A can have fewer transistors and fewer capacitors than the gate driver of the conventional display device. Accordingly, the gate driver 300 of FIG. 1A can reduce the bezel size of the display device and can reduce power consumption.

[0091] According to some embodiments, the gate driver 300B can include the first transistor T1, the first-second transistor T1-2, the second transistor T2, the third transistor T3, the fourth transistor T4, and the first capacitor C1. The gate driver 300B can have a 5T1C structure including five transistors and one capacitor. Accordingly, the integration of the gate driver 300B can be relatively improved, the bezel size of the display device can be reduced, and power consumption can be reduced. In addition, the first transistor T1 and the first-second transistor T1-2 are connected in series, so that the voltage of the first node Q1 and the voltage of the second node Q2 can be stably maintained. Accordingly, the reliability and stability of the gate driver 300B can be relatively improved.

[0092] In addition, although having fewer transistors and fewer capacitors than the gate driver of the conventional display device, the gate driver 300B can have similar performance to the gate driver of the conventional display device. Accordingly, the gate driver 300B can reduce the bezel size without degrading performance.

[0093] Figure 11 is a circuit diagram illustrating a gate driver 300 according to some embodiments. Figure 2 is a circuit diagram illustrating a gate driver 300 according to some embodiments.

[0094] Because the second electrode of the first transistor T1 is connected to the second node Q2, according to some embodiments, the gate driver 300B can have a similar structure to the gate driver 300A of FIG. 1A. Accordingly, the same reference numerals will be used to refer to the same elements and any repetitive explanation about the above elements will be omitted. Figure 11 is a circuit diagram illustrating a gate driver 300 according to some embodiments. Figure 3 The gate driver 300 of FIG. 1A can have a 3T1C structure. The gate driver 300 of FIG. 1A can include the first transistor T1, the second transistor T2, and the first capacitor C1. The gate driver 300 of FIG. 1A can have fewer transistors and fewer capacitors than the gate driver of the conventional display device. Accordingly, the gate driver 300 of FIG. 1A can reduce the bezel size of the display device and can reduce power consumption.

[0095] The gate driver 300C can include the first transistor T1, the third transistor T3, the fourth transistor T4, and the first capacitor C1. For example, the gate driver 300C can have a 3T1C structure.

[0096] Although having fewer transistors and fewer capacitors than the gate driver of the conventional display device, the gate driver 300C can still have similar performance to the gate driver of the conventional display device. Accordingly, the gate driver 300C can reduce the bezel size without degrading performance.

[0097] Figure 12 is a block diagram illustrating an electronic device according to some embodiments of the disclosure. Figure 13 is a diagram illustrating an example in which the electronic device of Figure 12 is implemented as a smart phone. is a diagram illustrating an example in which the electronic device of

[0098] Referring to Figure 12 and Figure 13 , the electronic device 1000 can include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device (e.g., an OLED device) 1060. Here, the display device 1060 can be a display device of Figure 1 . In addition, the electronic device 1000 can further include a plurality of ports for communication with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, etc.

[0099] According to some embodiments, as shown in Figure 13 , the electronic device 1000 can be implemented as a smart phone. However, the electronic device 1000 is not limited thereto. For example, the electronic device 1000 can be implemented as a cellular phone, a video phone, a smart pad, a smart watch, a tablet personal computer, a car navigation system, a computer monitor, a laptop computer, and a head-mounted display (HMD) device, etc.

[0100] The processor 1010 can perform various computing functions or various tasks. The processor 1010 can be a microprocessor, a central processing unit (CPU), an application processor (AP), etc. The processor 1010 can be coupled to other components via an address bus, a control bus, a data bus, etc. In addition, the processor 1010 can be coupled to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0101] The processor 1010 can output input image data IMG and an input control signal CONT to a driving controller 200 of Figure 1 .

[0102] The memory device 1020 can store data for the operation of the electronic device 1000. For example, the memory device 1020 can include at least one non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase-change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, and a ferroelectric random access memory (FRAM) device, etc., and / or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, and a mobile DRAM device, etc.

[0103] The storage 1030 can include a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, and the like. The I / O device 1040 can include input devices such as a keyboard, a keypad, a mouse device, a touchpad, a microphone, and a touchscreen, and output devices such as a printer, a speaker, and a display device. In some embodiments, the display device 1060 can be included in the I / O device 1040. The power supply 1050 can provide power for operation of the electronic device 1000. The display device 1060 can be coupled to the other components via a bus or other communication link.

[0104] According to the above-described gate driver and display device, a display device in which the integration of the display device is relatively increased and the bezel size of the display device becomes relatively small by including a smaller number of transistors and a smaller number of capacitors can be provided.

[0105] The foregoing is a summary of aspects of some embodiments of the present disclosure and should not be interpreted as limiting thereof. Although several embodiments of the present disclosure have been described, it will be readily apparent to those skilled in the art that many modifications can be made thereto without departing from the novel teachings and features of embodiments according to the present disclosure. Accordingly, all such modifications are intended to be included within the scope of embodiments according to the present disclosure as defined in the claims and the full range of equivalents thereof. In the claims, the article "a," "an," and "the" are used to refer to one or more than one unless otherwise indicated by context. The term "another" is used to refer to at least a second or more unless otherwise indicated by context. The term "includes" and its variants are used synonymously with "comprising." The term "couple" or its variants are used to indicate an indirect or direct connection. Thus, a couple can mean a connection other than through a shared electrically conductive path. The term "or" is used in the inclusive sense (i.e., and / or) unless otherwise indicated by context. The term "associated with" is used to mean that one element is associated with another unless otherwise indicated by context. Thus, a first element associated with a second element can mean that the first element coexists with the second element, or that the first element shares at least one non-trivial property with the second element. The term "substantially" is used to describe an amount that is close to the point of absolute reference under the specific context. Accordingly, the foregoing is intended to be illustrative of aspects of some embodiments of the present disclosure, and should not be construed as limiting thereof. It is intended that the scope of the present disclosure be defined by the following claims and their equivalents.

Claims

1. A gate driver comprising a plurality of stages, at least one stage of the plurality of stages comprising: a first transistor comprising a control electrode configured to receive a first clock signal, a first electrode configured to receive a previous stage gate signal, and a second electrode connected to a first node; a third transistor comprising a control electrode configured to receive the first clock signal directly, a first electrode configured to receive a first power voltage, and a second electrode connected to a third node; a fourth transistor comprising a control electrode connected to a second node, a first electrode configured to receive a second clock signal different from the first clock signal, and a second electrode connected to the third node; and a first capacitor comprising a first electrode connected to the second node and a second electrode connected to the third node, wherein the at least one stage is configured to output a voltage of the third node as a gate signal. The at least one stage further comprises:

2. The gate driver of claim 1, wherein, a second transistor comprising a control electrode configured to receive a second power voltage different from the first power voltage, a first electrode connected to the first node, and a second electrode connected to the second node. a ratio of a channel width to a channel length of the third transistor is different from a ratio of a channel width to a channel length of the fourth transistor.

3. The gate driver according to claim 1 or 2, wherein a channel width of the third transistor is narrower than a channel width of the fourth transistor.

4. The gate driver according to claim 1 or 2, wherein the fourth transistor is configured to be turned on based on the previous stage gate signal having an activation level in a first period.

5. The gate driver of claim 1, wherein, in a second period after the first period, the first clock signal has a deactivation level, the second clock signal has an activation level, and a voltage of the second node is lower than a low voltage of the second clock signal.

6. The gate driver of claim 5, wherein, in a third period after the second period, the first clock signal has an activation level, the second clock signal has a deactivation level, and the gate signal has a deactivation level.

7. The gate driver of claim 6, wherein, The at least one stage further comprises:

8. The gate driver of claim 1, wherein, a second transistor comprising a control electrode configured to receive a second power voltage different from the first power voltage, a first electrode connected to the first node, and a second electrode connected to the second node, and wherein a channel length of the first transistor is longer than a channel length of the second transistor.

9. A gate driver comprising a plurality of stages, at least one stage of the plurality of stages comprising: a first transistor configured to apply a previous stage gate signal to a first node in response to a first clock signal; a second transistor connected between the first node and a second node; a third transistor configured to receive the first clock signal directly and configured to apply a first power voltage to a third node; a fourth transistor configured to apply a second clock signal different from the first clock signal to the third node in response to a voltage of the second node; and a first capacitor connected between the second node and the third node, wherein the at least one stage is configured to output a voltage of the third node as a gate signal.

10. A display device comprising: a display panel; ​ ​ a gate driver configured to output a gate signal to a gate line of the display panel; and a data driver configured to output a data voltage to a data line of the display panel, wherein the gate driver comprises a plurality of stages, wherein at least one stage of the plurality of stages comprises: a first transistor comprising a control electrode configured to receive a first clock signal, a first electrode configured to receive a start signal, and a second electrode connected to a first node; a second transistor comprising a control electrode configured to receive a second power voltage, a first electrode connected to the first node, and a second electrode connected to a second node; a third transistor comprising a control electrode configured to receive the first clock signal directly, a first electrode configured to receive a first power voltage different from the second power voltage, and a second electrode connected to a third node; a fourth transistor comprising a control electrode connected to the second node, a first electrode configured to receive a second clock signal different from the first clock signal, and a second electrode connected to the third node; and a first capacitor comprising a first electrode connected to the second node and a second electrode connected to the third node, and wherein the at least one stage is configured to output a voltage of the third node as the gate signal.

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