Two-dimensional addressable VCSEL array, VCSEL chip and laser radar

Abstract

The utility model relates to a two-dimensional addressable VCSEL (Vertical Cavity Surface Emitting Laser) array, a VCSEL chip and a laser radar. The two-dimensional addressable VCSEL array comprises a plurality of VCSEL luminous points, a plurality of metal interconnection layers and a plurality of electrical access parts; the metal interconnection layers comprise first metal interconnection layers and second metal interconnection layers, the first metal interconnection layers are arranged at intervals in the first direction and extend in the second direction, the second metal interconnection layers are arranged at intervals in the second direction and extend in the first direction, and the first direction is perpendicular to the second direction; the plurality of electrical access parts comprise a first electrical access part and a second electrical access part, the first electrical access part is connected with negative electrodes of a row of VCSEL light-emitting points through the first metal interconnection layer, and the second electrical access part is connected with positive electrodes of a row of VCSEL light-emitting points through the second metal interconnection layer; wherein an electrical isolation area is at least formed on the electric leakage path between the adjacent first electrical access parts.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a two-dimensional addressable VCSEL array, a VCSEL chip and a laser radar. BACKGROUND

[0002] A two-dimensional addressable VCSEL array is a laser emitting device capable of independently controlling each VCSEL light emitting point. Through an external control signal, any one or more VCSEL units in the two-dimensional addressable VCSEL array can be precisely turned on or off, thereby realizing complex beam control and pattern generation. However, the two-dimensional addressable VCSEL array in the prior art is prone to causing VCSEL light emitting points to be mistakenly turned on due to leakage, which greatly affects the light emitting reliability of the two-dimensional addressable VCSEL array. SUMMARY

[0003] Therefore, it is necessary to provide a two-dimensional addressable VCSEL array, a VCSEL chip and a laser radar to solve the problems in the prior art.

[0004] In a first aspect, the utility model provides a two-dimensional addressable VCSEL array, the two-dimensional addressable VCSEL array includes a plurality of VCSEL light emitting points, a plurality of metal interconnection layers and a plurality of electrical access parts;

[0005] The plurality of metal interconnection layers include a first metal interconnection layer and a second metal interconnection layer, the first metal interconnection layer is arranged along a first direction and extends along a second direction, the second metal interconnection layer is arranged along the second direction and extends along the first direction, and the first direction and the second direction are perpendicular;

[0006] The plurality of electrical access parts include a first electrical access part and a second electrical access part, the first electrical access part is connected to the negative electrode of a column of VCSEL light emitting points through the first metal interconnection layer, and the second electrical access part is connected to the positive electrode of a row of VCSEL light emitting points through the second metal interconnection layer.

[0007] Wherein, an electrical isolation region is formed at least on the leakage path between adjacent first electrical access parts.

[0008] In one of the embodiments, the electrical isolation region is arranged along at least part of the outer contour of the first electrical access part.

[0009] In one of the embodiments, the electrical isolation region is a strip-shaped isolation region extending along the first direction or the second direction, and one end of the strip-shaped isolation region extends in a direction away from the first electrical access part.

[0010] In one of the embodiments, the top view shape of the strip-shaped isolation region is I-shaped; or

[0011] The top view shape of the strip-shaped isolation region is Y-shaped, and the bifurcation point of the strip-shaped isolation region is at least flush with one end of the first electrical access part.

[0012] In one of the embodiments, the electrical isolation region also extends between adjacent first metal interconnection layers; and / or

[0013] The electrical isolation region is arranged around the outer contour of the first electrical access part and the first metal interconnection layer.

[0014] In one of the embodiments, there are multiple leakage paths with different lengths between adjacent first electrical access parts, the width of the electrical isolation region is not completely uniform, and the width is negatively correlated with the length of the leakage path.

[0015] In one of the embodiments, when the two-dimensional addressable VCSEL array is powered on, the current density of the first electrical access part is greater than the current density of the first metal interconnection layer.

[0016] In one of the embodiments, the VCSEL light emitting point includes a substrate and a first mirror layer, an active layer, a photoelectric confinement layer, and a second mirror layer stacked on the surface of the substrate;

[0017] The first mirror layer and the second mirror layer are used to define a resonant cavity that generates a standing wave, and the photoelectric confinement layer is used to define a light emitting area of the VCSEL light emitting point.

[0018] In one of the embodiments, the electrical isolation region includes an isolation trench and / or an implanted isolation region;

[0019] The bottom of the isolation trench exposes the surface of the first mirror layer or the substrate; the implanted isolation region is located below the isolation trench, and the isolation trench exposes the surface of the first mirror layer at this time.

[0020] In one of the embodiments, the first width of the isolation trench between adjacent first electrical access parts is greater than the second width of the isolation trench between adjacent first metal interconnection layers; and / or

[0021] The first depth of the isolation trench between adjacent first electrical access parts is greater than the second depth of the isolation trench between adjacent first metal interconnection layers.

[0022] In one of the embodiments, a first implant depth of the implant isolation region between adjacent first electrical access portions is greater than a second implant depth of the implant isolation region between adjacent first metal interconnection layers; and / or

[0023] A first implant dose of the implant isolation region between adjacent first electrical access portions is greater than a second implant dose of the implant isolation region between adjacent first metal interconnection layers.

[0024] In one of the embodiments, adjacent VCSEL light emitting points are separated by mesa trenches, the first metal interconnection layer is located on a part of the surface exposed by the first mirror layer, a part of the sidewall of the mesa trench and a part of the surface of the second mirror layer, the first electrical access portion is located on a part of the surface of the first metal interconnection layer, and the first metal interconnection layer is electrically connected with the first mirror layer and the first electrical access portion respectively.

[0025] In a second aspect, the utility model provides a VCSEL chip, including two-dimensional addressable VCSEL array as above.

[0026] In a third aspect, the utility model provides a laser radar, including VCSEL chip as above and drive circuit for driving the VCSEL chip work.

[0027] The two-dimensional addressable VCSEL array, the VCSEL chip and the laser radar, by setting the electrical isolation region, can effectively improve the isolation effect between adjacent first electrical access portions, thereby reducing the leakage path between adjacent first electrical access portions, reducing the risk of leakage between adjacent first electrical access portions, and further reducing the case that the VCSEL light emitting point connected by the first metal interconnection layer of adjacent first electrical access portions is mislit when providing a control signal to one first electrical access portion, and improving the light emitting reliability of the VCSEL array. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0029] Figure 1 It is a top view global schematic diagram of one of the embodiments of the two-dimensional addressable VCSEL array;

[0030] Figure 2 It is a top view global schematic diagram of one of the embodiments of the two-dimensional addressable VCSEL array;

[0031] Figure 3 Figure 1 is a schematic diagram of a top view of a two-dimensional addressable VCSEL array according to an embodiment; Figure 2 Figure 2 is a schematic diagram of a top view of a two-dimensional addressable VCSEL array according to an embodiment;

[0032] Figure 4 Figure 3 is a schematic diagram of a top view of a two-dimensional addressable VCSEL array according to an embodiment;

[0033] Figure 5 Figure 4 is a schematic diagram of a leakage path according to an embodiment;

[0034] Figure 6 Figure 5 is a cross-sectional view of a two-dimensional addressable VCSEL array according to an embodiment along AA direction; Figure 3

[0035] Figure 7 Figure 6 is a cross-sectional view of a two-dimensional addressable VCSEL array according to an embodiment along BB direction; Figure 3

[0036] Figure 7 is a flow chart of a method for fabricating a two-dimensional addressable VCSEL array according to an embodiment; Figure 8

[0037] Figure 8 is a flow chart of a method for fabricating a two-dimensional addressable VCSEL array according to an embodiment. Figure 9 Element Number Explanation:

[0038] VCSEL light emitting point: 100; metal interconnection layer: 200; first metal interconnection layer: 210; second metal interconnection layer: 220; electrical access part: 300; first electrical access part: 310; second electrical access part: 320; electrical isolation region: 400; isolation groove: 410; injection isolation region: 420; substrate: 10; first mirror layer: 20; active layer: 30; photoelectric confinement layer: 40; second mirror layer: 50; first passivation layer: 61; second passivation layer: 62; mesa groove: 70.

[0039] DETAILED DESCRIPTION In order to facilitate the understanding of the present application, a more complete description of the present application will be provided below with reference to the relevant drawings. The drawings show embodiments of the present application. However, the present application can be implemented in many different forms, and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0040]

[0041] ​​Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application.

[0042] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section; for example, a first doped type could be termed a second doped type; and, similarly, a second doped type could be termed a first doped type; a first doped type and a second doped type are different doped types, e.g., a first doped type can be P-type and a second doped type can be N-type, or a first doped type can be N-type and a second doped type can be P-type.

[0043] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other direction, and the spatially relative terms used herein are intended to encompass such additional orientations. It is to be understood that the spatially relative terms used herein, including up, down, top, bottom, front, back, leading, trailing, left, right, over, under, above, below, under, lower, upper, and the like, are intended for the device's use in the particular orientation as shown in the figures. It will be appreciated that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Therefore, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other direction, and the spatially relative terms used herein are intended to encompass such additional orientations.

[0044] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It should also be understood that the term "comprising" or "having" etc. specifies the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but does not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in the present specification, the term "and / or" includes any and all combinations of the associated listed items.

[0045] Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic unless otherwise specified. Consequently, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change between implanted and non-implanted regions. Similarly, a buried region formed by implantation can result in some implantation in a region between the buried region and a surface through which the implantation occurs. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the application.

[0046] The embodiments of the present application provide a two-dimensional addressable VCSEL array, Figure 1 is a top view schematic diagram of a two-dimensional addressable VCSEL array according to an embodiment, and Figure 1 The two-dimensional addressable VCSEL array includes a plurality of VCSEL light emitting points 100, a plurality of metal interconnection layers 200, and a plurality of electrical access portions 300. The plurality of metal interconnection layers 200 includes a first metal interconnection layer 210 and a second metal interconnection layer 220, and the plurality of electrical access portions 300 includes a first electrical access portion 310 and a second electrical access portion 320.

[0047] The first metal interconnection layer 210 is arranged along a first direction and extends along a second direction, and the second metal interconnection layer 220 is arranged along the second direction and extends along the first direction. The first direction and the second direction can be arranged crosswise, for example, perpendicular to each other. Figure 1For example, the first direction can be the X direction, and the second direction can be the Y direction. For ease of illustration, in each embodiment of the present application, the metal interconnection layer 200 arranged along the X direction at intervals and extending along the Y direction is referred to as the first metal interconnection layer 210, and the metal interconnection layer 200 arranged along the Y direction at intervals and extending along the X direction is referred to as the second metal interconnection layer 220. Further, the plurality of first metal interconnection layers 210 can be arranged at equal or unequal intervals along the X direction, and the plurality of second metal interconnection layers 220 can be arranged at equal or unequal intervals along the Y direction, which can be specifically set according to the application scenario of the two-dimensional addressable VCSEL array, and is not limited herein.

[0048] The first electrical access part 310 is connected to the negative electrode of a column of VCSEL light emitting points through the first metal interconnection layer 210, and the second electrical access part 320 is connected to the positive electrode of a row of VCSEL light emitting points through the second metal interconnection layer 220. The electrical access part 300 is used to connect an external control circuit, so as to facilitate the access of a control signal of each VCSEL light emitting point 100. The metal interconnection layer 200 is used to provide the control signal accessed by the electrical access part 300 to the connected VCSEL light emitting point 100. The control signal is used to select the VCSEL light emitting point 100 to emit light and control the light emitting intensity of the VCSEL light emitting point 100 to emit light.

[0049] The VCSEL light emitting point 100 can include a plurality of optical apertures, for example Figure 1 For example, one VCSEL light emitting point 100 includes six optical apertures. The cross section of the VCSEL light emitting point 100 can be, but is not limited to, circular, elliptical, polygonal, etc. It should be noted that Figure 1 The number and arrangement of the optical apertures in the illustrated VCSEL light emitting point 100 are only used for illustrative purposes, and are not used to limit the protection scope of the present embodiment. Moreover, the position of the VCSEL light emitting point 100 can be correspondingly arranged according to the arrangement position of the metal interconnection layer 200 and the electrical access part 300, which is not limited in the present embodiment.

[0050] An electrical isolation region 400 is formed at least on the leakage path between adjacent first electrical access parts 310. In the related art, if the electrical isolation region 400 of the present embodiment on the leakage path between adjacent first electrical access parts 310 is not provided, it is difficult to achieve effective electrical isolation between adjacent first electrical access parts 310. In the case of insufficient isolation between adjacent first electrical access parts 310, when a control signal is provided to one first electrical access part 310, it is possible to leak to the adjacent first electrical access part 310, resulting in the case that the connected VCSEL light emitting point 100 is mistakenly lit. For example Figure 1For example, in the case of insufficient isolation between adjacent first electrical access parts 310, when a control signal is provided to the first electrical access part C2, electricity may leak to at least one of the adjacent first electrical access parts C1 and C3, thereby causing the VCSEL light emitting point 100 connected to the first electrical access parts C1 and C3 to be mistakenly lit.

[0051] In the embodiments of the application, by providing the electrical isolation region 400, the isolation effect between adjacent first electrical access parts 310 can be effectively improved, thereby reducing the electricity leakage path between adjacent first electrical access parts 310, reducing the risk of electricity leakage between adjacent first electrical access parts 310, and further reducing the case that when a control signal is provided to one first electrical access part 310, the VCSEL light emitting point 100 connected to the adjacent first electrical access part 310 through the first metal interconnection layer 210 is mistakenly lit, thereby improving the light emitting reliability of the VCSEL array.

[0052] Continuing to refer to Figure 1 In one of the embodiments, the electrical isolation region 400 is arranged along at least part of the outer contour of the first electrical access part 310. The electrical isolation region 400 can surround the outer contour of the first electrical access part 310 except for the side facing the first metal interconnection layer 210, so as to better isolate the electricity leakage path at the end of the adjacent first electrical access part 310.

[0053] Further, Figure 2 FIG. 3 is a top view of a two-dimensional addressable VCSEL array according to an embodiment of the application, which is a third view of the global schematic diagram of the two-dimensional addressable VCSEL array according to an embodiment of the application, and Figure 3 FIG. 3 is a top view of a two-dimensional addressable VCSEL array according to an embodiment of the application, which is a third view of the global schematic diagram of the two-dimensional addressable VCSEL array according to an embodiment of the application, and Figure 2 FIG. 3 is a top view of a two-dimensional addressable VCSEL array according to an embodiment of the application, which is a third view of the global schematic diagram of the two-dimensional addressable VCSEL array according to an embodiment of the application, and Figure 3 FIG. 3 is a top view of a two-dimensional addressable VCSEL array according to an embodiment of the application, which is a third view of the global schematic diagram of the two-dimensional addressable VCSEL array according to an embodiment of the application, and Figure 2 FIG. 3 is a top view of a two-dimensional addressable VCSEL array according to an embodiment of the application, which is a third view of the global schematic diagram of the two-dimensional addressable VCSEL array according to an embodiment of the application, and Figure 2 FIG. 3 is a top view of a two-dimensional addressable VCSEL array according to an embodiment of the application, which is a third view of the global schematic diagram of the two-dimensional addressable VCSEL array according to an embodiment of the application, and Figure 3 In one of the embodiments, the electrical isolation region 400 is arranged along at least part of the outer contour of the first electrical access part 310. The electrical isolation region 400 can surround the outer contour of the first electrical access part 310 except for the side facing the first metal interconnection layer 210, so as to better isolate the electricity leakage path at the end of the adjacent first electrical access part 310.

[0054] Figure 4 FIG. 3 is a top view of a two-dimensional addressable VCSEL array according to an embodiment of the application, which is a third view of the global schematic diagram of the two-dimensional addressable VCSEL array according to an embodiment of the application, and Figure 4In one embodiment, the electrical isolation region 400 is a strip-shaped isolation region extending along a first direction or a second direction, and one end of the strip-shaped isolation region extends in a direction away from the first electrical access portion 310. Figure 4 The electrical isolation area 400 shown is a strip-shaped isolation area extending along the Y direction. Specifically, the top view shape of the strip-shaped isolation area can be "I" shaped (e.g., ...). Figure 4 As shown in the figure, it can also be Y-shaped (not shown), and this application does not limit this. Furthermore, where space permits in the two-dimensional addressable VCSEL array, the end of the strip isolation region away from the first metal interconnect layer 210 can protrude beyond the end of the first electrical access portion 310 away from the first metal interconnect layer 210 to better isolate leakage paths at adjacent ends of the first electrical access portion 310. When the strip isolation region is Y-shaped, the bifurcation point of the strip isolation region is at least flush with one end of the first electrical access portion 310. In one embodiment, the end of the strip isolation region away from the first metal interconnect layer 210 can also be flush with the end of the first electrical access portion 310 away from the first metal interconnect layer 210 to save space in the two-dimensional addressable VCSEL array.

[0055] Further reference Figure 4 The electrical isolation region 400 also extends between adjacent first metal interconnect layers 210. Specifically, not only are there leakage paths between adjacent first electrical access portions 310, but there may also be leakage paths between adjacent first metal interconnect layers 210. Therefore, even if the leakage paths between adjacent first electrical access portions 310 are isolated by the electrical isolation region 400, when a control signal is transmitted on a first metal interconnect layer 210, the leakage paths between adjacent first metal interconnect layers 210 may still cause the VCSEL light-emitting points 100 connected to adjacent first metal interconnect layers 210 to be accidentally lit.

[0056] Figure 5 This is a schematic diagram of a leakage current path in one embodiment. Figure 5 Taking two adjacent first electrical connection sections C1 and C2 as examples, refer to Figure 5 In one embodiment, there are multiple leakage paths of different lengths between adjacent first electrical access portions 310. Figure 5 Two leakage paths, a and b, are shown, where path a is shorter than path b. The length of a leakage path can, to some extent, characterize the difficulty or risk of leakage. A longer leakage path generally carries a lower risk of leakage, while a shorter path carries a higher risk.

[0057] The cross-sectional dimensions of the electrical isolation zone 400 are not entirely identical at different locations, and the cross-sectional dimensions are negatively correlated with the length of the leakage path. The cross-sectional dimension refers to the size of the cross-section of the electrical isolation zone 400 along a plane perpendicular to its extension direction, including both lateral and longitudinal dimensions. Optionally, the lateral dimensions or longitudinal dimensions of the cross-section of the electrical isolation zone 400 may differ at different locations; this is not limited here. The lateral dimension can be referred to as the width of the electrical isolation zone 400, and the longitudinal dimension as its thickness or depth. A larger cross-sectional dimension of the electrical isolation zone 400 means better isolation and a greater reduction in the risk of leakage. Therefore, by setting electrical isolation zones 400 with different cross-sectional dimensions along leakage paths of different lengths, different leakage paths can be isolated more accurately.

[0058] Furthermore, simulation methods can be used to analyze a two-dimensional addressable VCSEL array without an electrical isolation region 400 to determine the leakage paths in the array and the leakage current distribution on each path. Based on this, the cross-sectional dimensions of the electrical isolation region 400 can be quantitatively set according to the leakage current values ​​of each path.

[0059] In one embodiment, the width of the electrical isolation region 400 is not uniform at different locations, and the width is negatively correlated with the length of the leakage path. For example, if leakage path a is shorter than leakage path b, the third width at the intersection of the electrical isolation region 400 and leakage path a can be set to be greater than the fourth width at the intersection of the electrical isolation region 400 and leakage path a. The boundaries between electrical isolation regions 400 with different widths can be arranged in a stepped manner, or alternatively... Figure 5 The gradient setting shown is not limited here. For leakage paths of different lengths, setting electrical isolation areas 400 of different widths on the leakage path can more accurately isolate different leakage paths, reduce the possibility of VCSEL light-emitting points 100 being accidentally lit, and reduce the space occupied by the electrical isolation area 400 in the two-dimensional addressable VCSEL array.

[0060] In one of the embodiments, the thickness of the electrical isolation region 400 is not completely uniform, and the thickness is negatively correlated with the length of the leakage path. For example, the leakage path a is shorter than the leakage path b, and the third thickness of the electrical isolation region 400 at the intersection position of the electrical isolation region 400 and the leakage path a is greater than the fourth thickness of the electrical isolation region 400 at the intersection position of the electrical isolation region 400 and the leakage path a. The junction of the electrical isolation region 400 with different thicknesses can be arranged in a stepped manner or in a gradual manner, which is not limited here. For the leakage paths with different lengths, the electrical isolation region 400 with different thicknesses is arranged on the leakage path, which can more accurately isolate different leakage paths, reduce the situation that the VCSEL light-emitting point 100 is mistakenly lit, and reduce the space occupied by the electrical isolation region 400 in the two-dimensional addressable VCSEL array.

[0061] Figure 6 For Figure 3 A cross-sectional view of the two-dimensional addressable VCSEL array of the embodiment along the AA direction, Figure 7 For Figure 3 A cross-sectional view of the two-dimensional addressable VCSEL array of the embodiment along the BB direction, in combination with reference to Figure 6 And Figure 7 In one of the embodiments, adjacent VCSEL light-emitting points 100 are separated by mesa trenches 70. The VCSEL light-emitting point 100 includes a substrate 10 and a first mirror layer 20, an active layer 30, a photoelectric confinement layer 40, and a second mirror layer 50 which are stacked on the surface of the substrate 10. The first mirror layer 20 and the second mirror layer 50 are used to define a resonant cavity that generates a standing wave, and the photoelectric confinement layer 40 is used to define the light-emitting area of the VCSEL light-emitting point 100.

[0062] The first metal interconnection layer 210 is located on the exposed part of the surface of the first mirror layer 20, part of the sidewall of the mesa trench 70, and part of the surface of the second mirror layer 50, and the first electrical access part 310 is located on part of the surface of the first metal interconnection layer 210. The first metal interconnection layer 210 is electrically connected to the first mirror layer 20 and the first electrical access part 310, respectively.

[0063] The active layer 30 includes quantum wells. The material of the active layer 30 includes one or more of AlInGaAs (e.g., AlInGaAs, GaAs, AlGaAs, and InGaAs), InGaAsP (e.g., InGaAsP, GaAs, InGaAs, GaAsP, and GaP), GaAsSb (e.g., GaAsSb, GaAs, and GaSb), InGaAsN (e.g., InGaAsN, GaAs, InGaAs, GaAsN, and GaN), or AlInGaAsP (e.g., AlInGaAsP, AlInGaAs, AlGaAs, InGaAs, InGaAsP, GaAs, InGaAs, GaAsP, and GaP).

[0064] The photoelectric confinement layer 40 can include any one of an air post type photoelectric confinement layer, an oxidation confinement type photoelectric confinement layer, an ion implantation type photoelectric confinement layer, and a tunnel junction type photoelectric confinement layer. The oxidation confinement type photoelectric confinement layer includes an unoxidized region of an AlGaAs material with a high aluminum component and an oxidized region of an aluminum oxide material, the oxidized region is located outside the unoxidized region, and the unoxidized region forms a light emitting region of effective current injection. When the current enters, the current can only flow to the active layer 30 through the opening in the photoelectric confinement layer 40, thereby realizing the confinement of the current injection path and the optical mode field. Further, the high aluminum component AlGaAs layer can be converted into aluminum oxide by a selective oxidation process to form a peripheral unoxidized region.

[0065] The first mirror layer 20 and the second mirror layer 50 have opposite conductive types, i.e., one is N-type doped and the other is P-type doped. For example, the first mirror layer 20 is an N-type layer and the second mirror layer 50 is a P-type layer.

[0066] The first mirror layer 20 includes a first Bragg mirror and a first conductive layer. The first Bragg mirror is located on the substrate 10. The first conductive layer has the same conductive type as the first Bragg mirror and is located on the top surface of the first Bragg mirror away from the substrate 10. Illustratively, the first Bragg mirror includes first AlGaAs layers and second AlGaAs layers that are alternately stacked and have the same doping type. Both the first AlGaAs layers and the second AlGaAs layers contain aluminum elements, and the content of aluminum elements in the first AlGaAs layers is greater than that in the second AlGaAs layers, so that the first AlGaAs layers and the second AlGaAs layers have different refractive indices. The mesa trench 70 exposes part of the surface of the first conductive layer, the active layer 30 is located on the first conductive layer, and the bottom surface of the first metal interconnection layer 210 is in contact with the exposed part of the surface of the first conductive layer. The material of the first conductive layer includes a doped semiconductor to realize ohmic contact between the first Bragg mirror and the first metal interconnection layer 210.

[0067] The second mirror layer 50 includes a second Bragg mirror and a second conductive layer. The second Bragg mirror is located on the top surface of the active layer 30 away from the substrate 10. The second conductive layer is of the same conductive type as the second Bragg mirror and is located on the top surface of the second Bragg mirror away from the substrate 10. Illustratively, the second Bragg mirror includes third and fourth AlGaAs layers that are alternately stacked and of the same doping type. The third and fourth AlGaAs layers both contain aluminum elements, and the content of the aluminum elements in the third AlGaAs layer is greater than that in the fourth AlGaAs layer, so that the third and fourth AlGaAs layers have different refractive indices. The bottom of the second metal interconnection layer 220 is in contact with the top surface of the second conductive layer. The material of the second conductive layer includes a doped semiconductor to realize ohmic contact between the second Bragg mirror and the second metal interconnection layer 220.

[0068] With continued reference to Figure 6 And Figure 7 In one embodiment, the electrical isolation region 400 includes an isolation trench 410. The bottom of the isolation trench 410 exposes the surface of the first mirror layer 20 or the substrate 10. Specifically, the isolation trench 410 is located below and communicates with the mesa trench 70, that is, the isolation trench 410 is located between the first mirror layers 20 of adjacent VCSEL units. The isolation trench 410 is used to achieve electrical isolation between the first mirror layers 20 of the two adjacent VCSEL units. Illustratively, the bottom of the isolation trench 410 is between the bottom of the mesa trench 70 and the top surface of the substrate 10, that is, the bottom of the isolation trench 410 is between the bottom of the mesa trench 70 and the top surface of the substrate 10 forming the first mirror layer 20. Herein, the distance between the bottom of the isolation trench 410 and the top surface of the first mirror layer 20 is greater than or equal to 2 / 3 of the thickness of the first mirror layer 20. Illustratively, the bottom of the isolation trench 410 is between the bottom of the mesa trench 70 and the bottom surface of the substrate 10, that is, the isolation trench 410 is opened into the substrate 10, and the bottom surface of the substrate 10 is arranged opposite to the top surface of the substrate 10.

[0069] In one embodiment, when the two-dimensional addressable VCSEL array is powered on, the current density of the first electrical access part 310 is greater than that of the first metal interconnection layer 210. Specifically, the electrical connection part is used as a connection structure between the two-dimensional addressable VCSEL array and an external control circuit. Therefore, improving the current carrying capacity of the first electrical access part 310 can enable it to carry a larger current density, so as to ensure that the first electrical access part 310 has good electrical connection performance, thereby improving the reliability of the two-dimensional addressable VCSEL array.

[0070] In one embodiment, asFigure 2 As shown, in the case that the electrical isolation region 400 also extends between the adjacent first metal interconnect layers 210, the first width of the isolation trench 410 between the adjacent first electrical access portions 310 is greater than the second width of the isolation trench 410 between the adjacent first metal interconnect layers 210. It can be appreciated that since the current density of the first electrical access portion 310 is greater than that of the first metal interconnect layer 210, the carrier (electron and hole) density in the film layers near the first electrical access portion 310 is also higher, which means that there are more carriers moving, and thus the carriers are more likely to generate leakage current in the process of drift and diffusion. Therefore, by providing different widths of the isolation trench 410 between different structures, the different leakage paths can be more accurately isolated, the mis-lighting of the VCSEL light emitting point 100 can be reduced, and the space occupied by the electrical isolation region 400 in the two-dimensional addressable VCSEL array can be reduced.

[0071] In one embodiment, as shown in FIG. 1A, the electrical isolation region 400 is arranged between the adjacent first metal interconnect layers 210. In this case, the first width of the isolation trench 410 between the adjacent first electrical access portions 310 is greater than the second width of the isolation trench 410 between the adjacent first metal interconnect layers 210. Figure 2 As shown, in the case that the electrical isolation region 400 also extends between the adjacent first metal interconnect layers 210, the first width of the isolation trench 410 between the adjacent first electrical access portions 310 is greater than the second width of the isolation trench 410 between the adjacent first metal interconnect layers 210. It can be appreciated that since the current density of the first electrical access portion 310 is greater than that of the first metal interconnect layer 210, the carrier (electron and hole) density in the film layers near the first electrical access portion 310 is also higher, which means that there are more carriers moving, and thus the carriers are more likely to generate leakage current in the process of drift and diffusion. Therefore, by providing different widths of the isolation trench 410 between different structures, the different leakage paths can be more accurately isolated, the mis-lighting of the VCSEL light emitting point 100 can be reduced, and the space occupied by the electrical isolation region 400 in the two-dimensional addressable VCSEL array can be reduced.

[0072] Continuing to refer to Figure 6 and Figure 7In one embodiment, the electrical isolation region 400 includes an isolation trench 410 and an implantation isolation region 420. The bottom of the isolation trench 410 exposes the surface of the first mirror layer 20 or the substrate 10. The implantation isolation region 420 is located below the isolation trench 410, where the isolation trench 410 exposes the surface of the first mirror layer 20. Specifically, both the isolation trench 410 and the implantation isolation region 420 are located between the first mirror layers 20 of adjacent VCSEL cells. The isolation trench 410 is located below and communicates with the mesa trench 70, and the implantation isolation region 420 is located below the isolation trench. The implantation isolation region 420 is formed by ion implantation of the first mirror layer 20 at the bottom of the isolation trench 410. The isolation trench 410 and the implantation isolation region 420 are used together to achieve electrical isolation between the first mirror layers 20 of two adjacent VCSEL cells.

[0073] In one embodiment, such as Figure 2 As shown, when the electrical isolation region 400 extends between adjacent first metal interconnect layers 210, the first injection depth of the injection isolation region 420 located between adjacent first electrical access portions 310 is greater than the second injection depth of the injection isolation region 420 located between adjacent first metal interconnect layers 210. It is understood that since the current density of the first electrical access portion 310 is greater than the current density of the first metal interconnect layer 210, the carrier (electron and hole) density in the film layer near the first electrical access portion 310 will also be higher, meaning that more carriers move, making it easier for these carriers to generate leakage current during drift and diffusion. Therefore, by setting injection isolation regions 420 with different injection depths for the isolation trenches 410 between different structures, different leakage paths can be isolated more accurately, reducing the possibility of the VCSEL light-emitting point 100 being accidentally lit, and reducing the space occupied by the electrical isolation region 400 in the two-dimensional addressable VCSEL array.

[0074] In one embodiment, such as Figure 2As shown, in the case that the electrical isolation region 400 also extends between the adjacent first metal interconnection layers 210, the first implant dose of the implant isolation region 420 between the adjacent first electrical access portions 310 is greater than the second implant dose of the implant isolation region 420 between the adjacent first metal interconnection layers 210. It can be understood that, since the current density of the first electrical access portion 310 is greater than the current density of the first metal interconnection layer 210, the carrier (electron and hole) density in the film layer near the first electrical access portion 310 is also higher, which means that more carriers are moved, and thus these carriers are more likely to generate leakage current in the process of drift and diffusion. Therefore, by setting different implant doses of the implant isolation region 420 for the isolation trenches 410 between different structures, different leakage paths can be more accurately isolated, the situation of the VCSEL light-emitting point 100 being mistakenly lit can be reduced, and the space occupied by the electrical isolation region 400 in the two-dimensional addressable VCSEL array can be reduced.

[0075] The embodiment of the present application also provides a preparation method of a two-dimensional addressable VCSEL array, Figure 8 For one of the flowcharts of the preparation method of the two-dimensional addressable VCSEL array of an embodiment, reference is made to Figure 8 The preparation method of the two-dimensional addressable VCSEL array includes steps 802 and 804.

[0076] Step 802, providing a substrate 10 formed with a plurality of VCSEL light-emitting points 100.

[0077] The material of the substrate 10 is a low-doped III-V compound, and the III-V compound refers to a compound including a group III element and a group V element, for example, GaAs.

[0078] Step 804, forming a plurality of metal interconnection layers 200 and a plurality of electrical access portions 300.

[0079] The plurality of metal interconnection layers 200 includes a first metal interconnection layer 210 and a second metal interconnection layer 220, and the plurality of electrical access portions 300 includes a first electrical access portion 310 and a second electrical access portion 320. The first metal interconnection layer 210 is arranged at intervals along a first direction and extends along a second direction, and the second metal interconnection layer 220 is arranged at intervals along the second direction and extends along the first direction. The first direction and the second direction are perpendicular. The first electrical access portion 310 is connected to the negative electrode of a column of VCSEL light-emitting points through the first metal interconnection layer 210, and the second electrical access portion 320 is connected to the positive electrode of a row of VCSEL light-emitting points through the second metal interconnection layer 220. An electrical isolation region 400 is formed at least on a leakage path between adjacent first electrical access portions 310. Exemplarily, the first metal interconnection layer 210 is formed by plating.

[0080] In the embodiments of the application, by arranging the electrical isolation region 400, the isolation effect between adjacent first electrical access parts 310 can be effectively improved, thereby reducing the electric leakage path between adjacent first electrical access parts 310, reducing the risk of electric leakage between adjacent first electrical access parts 310, and further reducing the case that the VCSEL light emitting point 100 connected by the first metal interconnection layer 210 of the adjacent first electrical access part 310 is mistakenly lit when providing a control signal to one first electrical access part 310, thereby improving the light emitting reliability of the prepared VCSEL array.

[0081] In one of the embodiments, the step of providing the substrate 10 formed with a plurality of VCSEL light emitting points 100 includes the following steps: providing the substrate 10, and sequentially forming the first mirror layer 20, the active layer 30, the photoelectric confinement layer 40, and the second mirror layer 50 on the surface of the substrate 10. The first mirror layer 20, the active layer 30, and the second mirror layer 50 are etched to form a mesa groove 70 exposing part of the surface of the first mirror layer 20. Among them, the first mirror layer 20, the active layer 30, the photoelectric confinement layer 40, and the second mirror layer 50 can be collectively referred to as an epitaxial layer. By photoetching and etching the front surface of the epitaxial layer, a mesa groove is formed, the mesa groove 70 exposes part of the surface of the first mirror layer 20, and separates adjacent mesas. That is, the mesa groove 70 is used to divide a plurality of VCSEL light emitting points 100.

[0082] In one of the embodiments, after forming the mesa groove 70, the first metal interconnection layer 210 can be formed on the exposed part of the surface of the first mirror layer 20, part of the sidewall of the mesa groove 70, and part of the surface of the second mirror layer 50, and the first electrical access part 310 is formed on part of the surface of the first metal interconnection layer 210. Among them, the first metal interconnection layer 210 is electrically connected with the first mirror layer 20 respectively.

[0083] In one of the embodiments, before forming the first metal interconnection layer 210, it further includes ion implantation on the first mirror layer 20 exposed by the isolation groove 410 to form an implanted isolation region 420 in the first mirror layer 20. The orthogonal projection of the implanted isolation region 420 on the substrate 10 falls in the orthogonal projection of the isolation groove 410 on the substrate 10. The implanted isolation region 420 formed by ion implantation is a high resistance / insulation region, thereby strengthening the electrical isolation between adjacent first electrical access parts 310.

[0084] Figure 9 For the second flowchart of the preparation method of the two-dimensional addressable VCSEL array of one embodiment, refer to Figure 9 In one of the embodiments, the preparation method of the two-dimensional addressable VCSEL array includes steps 902 to 922.

[0085] Step 902, providing a substrate 10.

[0086] Step 904, sequentially forming a first mirror layer 20, an active layer 30, a photoelectric confinement layer 40 and a second mirror layer 50 on the surface of the substrate 10.

[0087] Step 906, etching the first mirror layer 20, the active layer 30 and the photoelectric confinement layer 40 to form a mesa groove 70 exposing part of the surface of the first mirror layer 20.

[0088] Step 908, etching the first mirror layer 20 exposed by the mesa groove 70 to form an isolation groove 410.

[0089] Step 910, ion implantation on the first mirror layer 20 exposed by the isolation groove 410 to form an implanted isolation region 420 in the first mirror layer 20.

[0090] Step 912, forming a first passivation layer 61 on the surface of the first mirror layer 20 away from the substrate 10, the sidewall of the isolation groove 410 and the surface of the second mirror layer 50 away from the substrate 10.

[0091] Step 914, forming a first metal interconnection layer 210 on part of the surface of the first mirror layer 20 and part of the surface of the first passivation layer 61.

[0092] Step 916, forming a first electrical access part 310 on part of the surface of the first metal interconnection layer 210.

[0093] Step 918, forming a second passivation layer 62 on the surface of the first metal interconnection layer 210 exposed and the surface of the first passivation layer 61 exposed.

[0094] The second passivation layer 62 can protect the first metal interconnection layer 210 from oxidation or electrochemical effects, etc.

[0095] Step 920, forming an opening in the first passivation layer 61 and the second passivation layer 62, and forming a second metal interconnection layer 220 in the opening.

[0096] The second metal interconnection layer 220 is electrically connected with the second mirror layer 50, the opening is used to expose part of the surface of the second mirror layer 50, and the second metal interconnection layer 220 has opposite polarity to the first electrode.

[0097] Step 922, forming a second electrical access part 320 on part of the surface of the second metal interconnection layer 220.

[0098] In one of the embodiments, the method for preparing the two-dimensional addressable VCSEL array further comprises the following steps: back thinning the substrate 10, and depositing a back metal on the thinned substrate 10. The back of the substrate 10 (the back of the wafer) is the side of the substrate 10 that faces away from the first mirror layer 20.

[0099] It should be understood that, although the steps in each flowchart are shown in a sequential order following the arrows, the steps need not necessarily be performed in the order shown by the arrows. Unless otherwise explicitly stated herein, there is no strict order requirement for the performance of the steps, and the steps can be performed in other orders. Also, at least some of the steps in each flowchart can include multiple steps or stages, which need not necessarily be performed at the same time, but can be performed at different times, and the order of performance of the steps or stages need not necessarily be sequential, but can be performed in rotation or alternation with other steps or steps or stages in other steps.

[0100] The embodiments of the present application also provide a VCSEL chip, which comprises the two-dimensional addressable VCSEL array as described above. In one of the embodiments of the present application, the chip is a two-dimensional addressable vertical cavity surface emitting laser chip.

[0101] The embodiments of the present application also provide a laser radar, which comprises a transmitting end and a receiving end. The transmitting end comprises the aforementioned two-dimensional addressable vertical cavity surface emitting laser chip as a light emitting source, a driving circuit for driving the chip to work, a deflection module for adjusting the field of view (FOV) of the laser radar, and the like. The receiving end comprises a photosensitive chip and the like.

[0102] In the description of the present specification, the description of the terms "some embodiments", "other embodiments", "ideal embodiments", and the like means that the specific features, structures, materials, or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example.

[0103] The technical features of the above embodiments can be combined in any manner. To make the description concise, not all possible combinations of the technical features of the above embodiments are described, however, as long as the combinations of the technical features do not contradict each other, they should be considered as within the scope of the present application.

[0104] The above embodiments only express several implementation ways of the present application, and the description is specific and detailed, but it should not be understood as a limitation to the patent scope of the application. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, several modifications and improvements can be made, which all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A two-dimensional addressable VCSEL array, characterized in that, The two-dimensional addressable VCSEL array comprises a plurality of VCSEL light emitting points, a plurality of metal interconnection layers, and a plurality of electrical access parts; The plurality of metal interconnection layers comprises a first metal interconnection layer and a second metal interconnection layer, the first metal interconnection layer is arranged in a first direction and extends in a second direction, the second metal interconnection layer is arranged in the second direction and extends in the first direction, and the first direction and the second direction are perpendicular; The plurality of electrical access parts comprises a first electrical access part and a second electrical access part, the first electrical access part is connected to the negative electrode of a column of VCSEL light emitting points through the first metal interconnection layer, and the second electrical access part is connected to the positive electrode of a row of VCSEL light emitting points through the second metal interconnection layer; An electrical isolation region is formed at least on a leakage path between adjacent first electrical access parts.

2. The two-dimensional addressable VCSEL array of claim 1, wherein, The electrical isolation region is arranged along at least part of the outer contour of the first electrical access part.

3. The two-dimensional addressable VCSEL array of claim 1, wherein, The electrical isolation region is a strip-shaped isolation region extending in the first direction or the second direction, and one end of the strip-shaped isolation region extends in a direction away from the first electrical access part.

4. The two-dimensional addressable VCSEL array of claim 3, wherein, The top view shape of the strip-shaped isolation region is I-shaped; or The top view shape of the strip-shaped isolation region is Y-shaped, and the bifurcation point of the strip-shaped isolation region is flush with at least one end of the first electrical access part.

5. The two-dimensional addressable VCSEL array of claim 1, wherein, The electrical isolation region is also arranged between adjacent first metal interconnection layers; and / or The electrical isolation region is arranged around the outer contour of the first electrical access part and the first metal interconnection layer.

6. The two-dimensional addressable VCSEL array of claim 1, wherein, Adjacent first electrical access parts have a plurality of leakage paths with different lengths, the width of the electrical isolation region at different positions is not completely the same, and the width is negatively correlated with the length of the leakage path.

7. The two-dimensional addressable VCSEL array of claim 1, wherein, When the two-dimensional addressable VCSEL array is powered on, the current density of the first electrical access part is greater than the current density of the first metal interconnection layer.

8. The two-dimensional addressable VCSEL array according to any one of claims 1 to 7, characterized in that The VCSEL light emitting point comprises a substrate and a first mirror layer, an active layer, a photoelectric confinement layer, and a second mirror layer stacked on the surface of the substrate; The first mirror layer and the second mirror layer are used to define a resonant cavity for generating standing waves, and the photoelectric confinement layer is used to define a light emitting area of the VCSEL light emitting point.

9. The two-dimensional addressable VCSEL array according to claim 8, characterized in that, The electrical isolation region comprises an isolation trench and / or an implanted isolation region; The bottom of the isolation trench exposes the surface of the first mirror layer or the substrate; The implanted isolation region is located below the isolation trench, and the isolation trench exposes the surface of the first mirror layer at this time.

10. The two-dimensional addressable VCSEL array of claim 9, wherein, The first width of the isolation trench between adjacent first electrical access parts is greater than the second width of the isolation trench between adjacent first metal interconnection layers; and / or The first depth of the isolation trench between adjacent first electrical access parts is greater than the second depth of the isolation trench between adjacent first metal interconnection layers.

11. The two-dimensional addressable VCSEL array of claim 9, wherein, The first implantation depth of the implanted isolation region between adjacent first electrical access parts is greater than the second implantation depth of the implanted isolation region between adjacent first metal interconnection layers; and / or The first implant dose of the implant isolation region located between adjacent first electrical access portions is greater than a second implant dose of the implant isolation region located between adjacent first metal interconnect layers.

12. The two-dimensional addressable VCSEL array of claim 8, wherein, The first metal interconnect layer is located on a portion of the surface of the first mirror layer exposed, a portion of the sidewall of the mesa trench, and a portion of the surface of the second mirror layer, and the first electrical access portion is located on a portion of the surface of the first metal interconnect layer, and the first metal interconnect layer is electrically connected with the first mirror layer and the first electrical access portion respectively.

13. A VCSEL chip, characterized by A two-dimensional addressable VCSEL array comprising any one of claims 1 to 10.

14. A lidar, comprising: A VCSEL chip as claimed in claim 13 and a driving circuit for driving the VCSEL chip to work.

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