Low dropout regulator and electronic device

Abstract

The utility model provides a low dropout regulator and electronic equipment, and belongs to the technical field of electronic circuits. The low dropout linear regulator comprises an error amplifier, a partial pressure sampling circuit, a power tube and a voltage conversion module. Wherein the error amplifier comprises a first input end, a second input end and an output end, the first input end is used for accessing reference voltage, the output end is connected with a first end of the voltage conversion module, a second end of the voltage conversion module is connected with a grid electrode of the power tube, a source electrode of the power tube is connected with power supply voltage, and a drain electrode of the power tube is connected with an input end of the voltage division sampling circuit; the output end of the voltage division sampling circuit is connected with the second input end. According to the LDO, the voltage conversion module is arranged between the error amplifier and the power tube of the LDO and used for adjusting the grid voltage of the power tube, the output stage of the error amplifier can work in a saturation region, and therefore the loop gain and stability are guaranteed.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuit, and particularly relates to a low dropout linear regulator and electronic equipment. BACKGROUND

[0002] LDO (Low Dropout Regulator, low dropout linear regulator) is a widely used power management device, and its main function is to convert the input voltage into a stable output voltage. The error amplifier is the core element of the LDO, and its function is to compare the feedback voltage and the reference voltage, and adjust the output stage to ensure the stability of the output voltage. The output stage of the error amplifier usually uses a transistor, and the working state of the transistor is divided into linear region and saturation region. The error signal output by the error amplifier is sent into the control loop of the LDO for adjusting the conduction degree of the power tube. However, since the voltage at the gate of the power tube from the output of the error amplifier is not adjustable, it will cause the output stage of the error amplifier to enter the linear region in some cases, which reduces the loop gain and stability. CONTENT

[0003] The main purpose of the embodiment of the present application is to provide a low dropout linear regulator and electronic equipment. By setting a voltage conversion module between the error amplifier and the power tube of the LDO, the gate voltage of the power tube is adjusted, so that the output stage of the error amplifier works in the saturation region, thereby ensuring the loop gain and stability.

[0004] To achieve the above purpose, the first aspect of the embodiment of the present application provides a low dropout linear regulator, comprising an error amplifier, a voltage division sampling circuit, a power tube and a voltage conversion module.

[0005] The error amplifier comprises a first input end, a second input end and an output end, the first input end is used for inputting a reference voltage, the output end is connected with a first end of the voltage conversion module, a second end of the voltage conversion is connected with a gate of the power tube, a source of the power tube is connected with a power supply voltage, a drain of the power tube is connected with an input end of the voltage division sampling circuit, and an output end of the voltage division sampling circuit is connected with the second input end.

[0006] The voltage conversion module is used for converting the gate voltage of the power tube into a target voltage, so that the output stage of the error amplifier works in the saturation region.

[0007] In an embodiment of the present application, the power tube comprises an NMOS tube, and correspondingly, the first input end of the error amplifier is a positive input end, and the second input end of the error amplifier is a negative input end; the voltage conversion module is used for reducing the gate voltage of the NMOS tube to a target voltage, so that the output stage of the error amplifier works in the saturation region.

[0008] In one embodiment of the present application, the voltage conversion module comprises a first PMOS tube and a first bias unit; a gate of the first PMOS tube is connected to an output terminal of the error amplifier, a drain of the first PMOS tube is grounded, a source of the first PMOS tube is connected to a gate of the NMOS tube, and the source of the first PMOS tube is also connected to the first bias unit.

[0009] In one embodiment of the present application, the first bias unit comprises a second PMOS tube, a gate of the second PMOS tube is used to connect a bias voltage, a source of the second PMOS tube is used to connect a power supply voltage, and a drain of the second PMOS tube is connected to the source of the first PMOS tube.

[0010] In one embodiment of the present application, the power tube comprises a PMOS tube, correspondingly, a first input terminal of the error amplifier is a negative input terminal, and a second input terminal of the error amplifier is a positive input terminal; the voltage conversion module is used to increase a gate voltage of the PMOS tube to a target voltage, so that an output stage of the error amplifier works in a saturation region.

[0011] In one embodiment of the present application, the voltage conversion module comprises a first NMOS tube and a second bias unit; a gate of the first NMOS tube is connected to an output terminal of the error amplifier, a source of the first NMOS tube is used to connect a power supply voltage, a drain of the first NMOS tube is connected to a gate of the PMOS tube, and the drain of the first NMOS tube is also connected to the second bias unit.

[0012] In one embodiment of the present application, the second bias unit comprises a second NMOS tube, a gate of the second NMOS tube is used to connect a bias voltage, a drain of the second NMOS tube is grounded, and a source of the second NMOS tube is connected to the drain of the first NMOS tube.

[0013] In one embodiment of the present application, the low-dropout linear regulator further comprises a zero-point compensation module, the zero-point compensation module is connected to a gate of the power tube, or the zero-point compensation module is connected to a first terminal of the voltage conversion module.

[0014] In one embodiment of the present application, the zero-point compensation module comprises a first resistor and a first capacitor, a first terminal of the first resistor is connected to the gate of the power tube or the first terminal of the voltage conversion module, a second terminal of the first resistor is connected to a first terminal of the first capacitor, and a second terminal of the first capacitor is grounded.

[0015] A second aspect of the embodiments of the present application proposes an electronic device comprising the low-dropout linear regulator of any of the embodiments of the present application.

[0016] The application provides a low dropout linear regulator and electronic equipment, the low dropout linear regulator includes error amplifier, voltage division sampling circuit, power tube and voltage conversion module. Wherein, the error amplifier includes first input end, second input end and output end, the first input end is used for accessing reference voltage, the output end is connected with the first end of voltage conversion module, the second end of voltage conversion is connected with the gate of power tube, the source of power tube is connected with power supply voltage, the drain of power tube is connected with the input end of voltage division sampling circuit, and the output end of voltage division sampling circuit is connected with the second input end. The application sets voltage conversion module between the error amplifier and power tube of LDO, which is used for adjusting the gate voltage of power tube, so that the output stage of error amplifier can work in saturation region, thereby guaranteeing loop gain and stability

[0017] Other characteristics and advantages of the application will become apparent from the following detailed description, or will be learned by practice of the application.

[0018] It should be understood that the above general description and the following detailed description are only exemplary and cannot limit the application. BRIEF DESCRIPTION OF DRAWINGS

[0019] The above and other objects, features and advantages of the present application will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings in which:

[0020] Figure 1 is a first block diagram of the low dropout linear regulator provided by an embodiment of the application.

[0021] Figure 2 is a first circuit diagram of the low dropout linear regulator provided by an embodiment of the application.

[0022] Figure 3 is a second circuit diagram of the low dropout linear regulator provided by an embodiment of the application.

[0023] Figure 4 is a third circuit diagram of the low dropout linear regulator provided by an embodiment of the application.

[0024] Figure 5 is a fourth circuit diagram of the low dropout linear regulator provided by an embodiment of the application.

[0025] Figure 6 is a second block diagram of the low dropout linear regulator provided by an embodiment of the application.

[0026] Figure 7 is a third block diagram of the low dropout linear regulator provided by an embodiment of the application.

[0027] Figure 8Figure 5 is a fifth circuit diagram of a low dropout linear regulator according to an embodiment of the present application.

[0028] Figure 9 Figure 6 is a sixth circuit diagram of a low dropout linear regulator according to an embodiment of the present application. DETAILED DESCRIPTION

[0029] Example implementations will now be described with reference to the drawings. However, example implementations can be implemented in many different forms and should not be construed as limited to the examples set forth herein; rather, these example implementations are provided so that this disclosure will be thorough and complete, and will fully convey the inventive aspects of the example implementations to those skilled in the art. The accompanying drawings are included to provide a further understanding of the present application and are incorporated in and constitute a part of this specification. The drawings are not necessarily to scale, the same reference numerals in different drawings representing the same or similar elements so as to maintain consistency and clarity of these descriptions, and their repetitive description will be omitted.

[0030] In addition, the described features, structures, or characteristics can be combined in any suitable manner in one or more example implementations. In the following description, numerous specific details are provided to give a thorough understanding of example implementations. However, one skilled in the relevant art will recognize that the principles of the present application can be practiced without one or more of the specific details, or

[0031] Some of the block diagrams in the drawings are functional entities that do not necessarily have to correspond to physically or logically independent entities. These functional entities can be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microprocessor devices.

[0032] A LDO (Low Dropout Regulator) is an electronic component used for power management. Its main function is to stably reduce the input voltage to the required output voltage, and has the characteristics of low dropout, linear regulation and voltage stabilization. The LDO includes an error amplifier for comparing the feedback voltage and the reference voltage, and adjusting the output stage to ensure the stability of the output voltage. The output stage of the error amplifier usually uses a transistor, and the working state of the transistor is divided into linear region and saturation region. The error signal output by the error amplifier is sent to the control loop of the LDO for adjusting the conduction degree of the power tube. However, since the voltage at the gate of the power tube from the output of the error amplifier is not adjustable, it will cause the output stage of the error amplifier to enter the linear region in some cases, resulting in a decrease in loop gain and stability.

[0033] Based on this, this application proposes a low dropout linear regulator. By setting a voltage conversion module between the error amplifier and the power transistor of the LDO, the gate voltage of the power transistor can be adjusted, so that the output stage of the error amplifier can operate in the saturation region, thereby ensuring loop gain and stability.

[0034] Reference Figure 1 , Figure 1 This is a first block diagram of a low-dropout linear regulator provided in an embodiment of this application. Figure 1 As shown, the low-dropout linear regulator includes an error amplifier 10, a voltage divider sampling circuit 20, a power transistor 30, and a voltage conversion module 40. The error amplifier 10 includes a first input terminal, a second input terminal, and an output terminal. The first input terminal is connected to a reference voltage VREF. The output terminal is connected to the first terminal of the voltage conversion module 40. The second terminal of the voltage conversion module 40 is connected to the gate of the power transistor 30. The source of the power transistor 30 is connected to the power supply voltage VDD. The drain of the power transistor 30 is connected to the input terminal of the voltage divider sampling circuit 20. The output terminal of the voltage divider sampling circuit 20 is connected to the second input terminal to transmit a feedback voltage VFB to the second input terminal. The voltage conversion module 40 converts the gate voltage of the power transistor 30 into a target voltage so that the output stage of the error amplifier 10 operates in the saturation region.

[0035] In this embodiment, by setting a voltage conversion module 40 between the error amplifier 10 and the power transistor 30 of the LDO, the output stage of the error amplifier 10 can be made to operate in the saturation region to adjust the gate voltage of the power transistor 30, thereby ensuring loop gain and stability.

[0036] Reference Figure 2 , Figure 2 This is a first circuit diagram of a low-dropout linear regulator provided in an embodiment of this application. Figure 2 As shown, the low-dropout linear regulator includes an error amplifier 10, a voltage divider sampling circuit 20, an NMOS transistor 31, and a voltage conversion module 40. The error amplifier 10 includes a positive input terminal, a negative input terminal, and an output terminal. The positive input terminal is connected to a reference voltage VREF. The output terminal is connected to the first terminal of the voltage conversion module 40. The second terminal of the voltage conversion module 40 is connected to the gate G of the NMOS transistor 31. The source S of the NMOS transistor 31 is connected to the power supply voltage VDD. The drain D of the NMOS transistor 31 is connected to the input terminal of the voltage divider sampling circuit 20. The output terminal of the voltage divider sampling circuit 20 is connected to the negative input terminal to transmit a feedback voltage VFB to the negative input terminal. The voltage conversion module 40 is used to reduce the gate voltage of the NMOS transistor 31 to the target voltage so that the output stage of the error amplifier 10 operates in the saturation region.

[0037] In the embodiment of the present application, the power tube 30 can adopt the NMOS tube 31. However, when the output of the LDO is a large current, the gate voltage of the PMOS tube 32 can reach a very high value (close to VDD), which can cause the output stage of the error amplifier 10 to enter the linear region, thereby reducing the loop gain and possibly causing the output voltage to deviate, reducing the stability, and possibly causing the loop to oscillate. In this regard, the embodiment of the present application sets the voltage conversion module 40 between the output of the error amplifier 10 and the gate of the NMOS tube 31, which can reduce the gate voltage V1 of the NMOS tube 31 to the target voltage V1_pre, so that the output stage of the error amplifier 10 works in the saturation region, thereby ensuring the loop gain and stability. Specifically, by introducing the voltage conversion module 40, the gate voltage V1 of the NMOS tube 31 can be reduced by Vgs (this voltage value is generally > Vth), and the target voltage V1_pre voltage is obtained. The target voltage V1_pre voltage can be designed to make the error amplifier 10 output stage work in the saturation region, so that the loop gain is mainly provided by the error amplifier 10. Even if the gate voltage V1 of the NMOS tube 31 is very high, the output stage of the voltage conversion module 40 enters the linear region, which can be ignored in the overall loop, thereby ensuring the overall loop gain.

[0038] In the embodiment of the present application, referring to Figure 2 , the voltage conversion module 40 includes a first PMOS tube PM1 and a first bias unit 41. The gate G of the first PMOS tube PM1 is connected to the output of the error amplifier 10, the drain D of the first PMOS tube PM1 is grounded, the source S of the first PMOS tube PM1 is connected to the gate G of the NMOS tube 31, and the source S of the first PMOS tube PM1 is also connected to the first bias unit 41. The first bias unit 41 is used to provide a normal working point for the first PMOS tube PM1, and ensures that the first PMOS tube PM1 works stably in the amplification state. Specifically, the first bias unit 41 can make the gate G, the drain D and the source S of the first PMOS tube PM1 at the required potential, thereby ensuring the stable working point of the first PMOS tube PM1.

[0039] In some embodiments, referring to Figure 3 , Figure 3 is a second circuit diagram of a low dropout linear regulator provided by an embodiment of the present application. By Figure 3As shown, the first bias unit 41 includes a second PMOS PM2, a gate G of the second PMOS PM2 is used for connecting a bias voltage Vbp, a source S of the second PMOS PM2 is used for connecting a power supply voltage, and a drain D of the second PMOS PM2 is connected to a source S of the first PMOS PM1. In the embodiment of the present application, for the case that the power tube 30 adopts an NMOS, the voltage conversion module 40 is composed of the first PMOS PM1 and the second PMOS PM2. The circuit structure is simple, does not occupy much layout area, and has low power consumption, and is suitable for low-power consumption scenarios.

[0040] Referring to Figure 4 , Figure 4 is a third circuit diagram of a low-dropout linear regulator provided by an embodiment of the present application. As shown in Figure 4 , the low-dropout linear regulator includes an error amplifier 10, a voltage division sampling circuit 20, a PMOS 32, and a voltage conversion module 40. The error amplifier 10 includes a negative input end, a positive input end, and an output end, the negative input end is used for connecting a reference voltage VREF, the output end is connected to a first end of the voltage conversion module 40, a second end of the voltage conversion module 40 is connected to a gate G of the PMOS 32, a source S of the PMOS 32 is connected to a power supply voltage VDD, a drain D of the PMOS 32 is connected to an input end of the voltage division sampling circuit 20, and an output end of the voltage division sampling circuit 20 is connected to the positive input end to transmit a feedback voltage VFB to the positive input end. The voltage conversion module 40 is used for increasing a gate voltage of the PMOS 32 to a target voltage, so that an output stage of the error amplifier 10 works in a saturation region.

[0041] In the embodiment of the present application, the power tube 30 can adopt the PMOS 32, however, when the output of the LDO is a large current, the gate voltage of the PMOS 32 will be very low, which will cause the output stage of the error amplifier 10 to enter a linear region, thereby reducing the loop gain and possibly causing the output voltage to deviate and reducing the stability. For this, the embodiment of the present application sets the voltage conversion module 40 between the output end of the error amplifier 10 and the gate of the PMOS 32, which can increase the gate voltage V1 of the PMOS 32 to a target voltage V1_pre, so that the output stage of the error amplifier 10 works in the saturation region, thereby ensuring the loop gain and stability. Specifically, by introducing the voltage conversion module 40, the gate voltage V1 of the PMOS 32 can be increased by Vgs (this voltage value is generally > Vth), to obtain the target voltage V1_pre, and the target voltage V1_pre can be designed to make the output stage of the error amplifier 10 work in the saturation region, so that the loop gain is mainly provided by the error amplifier 10, even if the gate voltage V1 of the PMOS 32 is very low to cause the output stage of the voltage conversion module 40 to enter the linear region, the influence on the overall loop can be ignored, thereby ensuring the overall loop gain.

[0042] In the embodiments of the present application, referring to Figure 4 , the voltage conversion module 40 comprises a first NMOS tube NM1 and a second bias unit 42. The gate G of the first NMOS tube NM1 is connected to the output end of the error amplifier 10, the source S of the first NMOS tube NM1 is used to connect the power supply voltage VDD, the drain D of the first NMOS tube NM1 is connected to the gate G of the PMOS tube, and the drain D of the first NMOS tube NM1 is also connected to the second bias unit 42. The second bias unit 42 is used to provide a normal working point for the first NMOS tube NM1, and to ensure that the first NMOS tube NM1 works stably in the amplification state. Specifically, the second bias unit 42 can make the gate G, the drain D and the source S of the first NMOS tube NM1 at the required potential, so as to ensure that the working point of the first NMOS tube NM1 is stable.

[0043] In some embodiments, referring to Figure 5 , Figure 5 is a fourth circuit diagram of a low-dropout linear regulator provided by an embodiment of the present application. As shown in Figure 5 , the second bias unit 42 comprises a second NMOS tube NM2, the gate G of the second NMOS tube NM2 is used to connect the bias voltage Vbn, the drain D of the second NMOS tube NM2 is grounded, and the source S of the second NMOS tube NM2 is connected to the drain D of the first NMOS tube NM1. In the embodiments of the present application, for the case that the power tube 30 adopts the PMOS tube, the voltage conversion module 40 is composed of the first NMOS tube NM1 and the second NMOS tube NM2. The circuit structure is simple, and the power consumption is low, which is suitable for low-power consumption scenarios.

[0044] In some embodiments, referring to Figures 6-7 , Figure 6 is a second block diagram of a low-dropout linear regulator provided by an embodiment of the present application, Figure 7 is a third block diagram of a low-dropout linear regulator provided by an embodiment of the present application. As shown in Figure 6As shown, the low dropout linear voltage regulator comprises an error amplifier 10, a voltage division sampling circuit 20, a power transistor 30, a voltage conversion module 40 and a zero compensation module 50. The error amplifier 10 comprises a first input end, a second input end and an output end, the first input end is used to access a reference voltage VREF, the output end is connected to a first end of the voltage conversion module 40, a second end of the voltage conversion module 40 is connected to a gate of the power transistor 30, a source of the power transistor 30 is connected to a power supply voltage VDD, a drain of the power transistor 30 is connected to an input end of the voltage division sampling circuit 20, and an output end of the voltage division sampling circuit 20 is connected to the second input end to transmit a feedback voltage VFB to the second input end. The voltage conversion module 40 is used to convert the gate voltage of the power transistor 30 into a target voltage, so that the output stage of the error amplifier 10 works in the saturation region. The zero compensation module 50 is connected to the gate G of the power transistor 30. As shown Figure 7 As shown, the zero compensation module 50 is connected to the first end of the voltage conversion module 40.

[0045] In the embodiment of the present application, the voltage conversion module 40 is arranged between the error amplifier 10 and the power transistor 30 of the LDO, which is used to adjust the gate voltage of the power transistor 30, so that the output stage of the error amplifier 10 works in the saturation region, thereby ensuring the loop gain and stability. At the same time, considering the loop stability, the zero compensation module 50 can be connected to the gate G of the power transistor 30 or the first end of the voltage conversion module 40 for compensation, so as to ensure the stability of the loop.

[0046] Referring to Figures 8-9 , Figure 8 is a fifth circuit diagram of a low dropout linear voltage regulator provided by an embodiment of the present application, Figure 9 is a sixth circuit diagram of a low dropout linear voltage regulator provided by an embodiment of the present application. Referring to Figure 8 The zero compensation module 50 comprises a first resistor R1 and a first capacitor C1, a first end of the first resistor R1 is connected to the gate G of the NMOS transistor 31, a second end of the first resistor R1 is connected to a first end of the first capacitor C1, and a second end of the first capacitor C1 is grounded. Referring to Figure 9 The zero compensation module 50 comprises a first resistor R1 and a first capacitor C1, a first end of the first resistor R1 is connected to the gate G of the first PMOS transistor PM1, a second end of the first resistor R1 is connected to a first end of the first capacitor C1, and a second end of the first capacitor C1 is grounded.

[0047] In the embodiment of the present application, an external capacitor and a resistor are connected between the error amplifier 10 and the power transistor 30 to form a fixed zero point. This zero point is located in the loop gain bandwidth, which can help the system to maintain stability when the load changes.

[0048] The application further provides an electronic device comprising the low dropout linear regulator provided by any of the embodiments of the application. Since the electronic device comprises the low dropout linear regulator provided by any of the embodiments of the application, and the voltage conversion module is arranged between the error amplifier and the power tube in the low dropout linear regulator, the gate voltage of the power tube is adjusted, the output stage of the error amplifier can work in the saturation region, and thus the loop gain and stability are ensured.

[0049] The preferred embodiments of the application are described above with reference to the drawings, but the scope of the application is not limited thereto. Any modification, equivalent replacement and improvement made by those skilled in the art without departing from the scope and spirit of the application shall fall within the scope of the application.

Claims

1. A low dropout linear regulator, characterized by, The error amplifier, the voltage dividing sampling circuit, the power tube and the voltage conversion module are included. The error amplifier includes a first input end, a second input end and an output end, the first input end is used for accessing a reference voltage, the output end is connected with a first end of the voltage conversion module, a second end of the voltage conversion module is connected with a gate of the power tube, a source of the power tube is connected with a power supply voltage, a drain of the power tube is connected with an input end of the voltage dividing sampling circuit, and an output end of the voltage dividing sampling circuit is connected with the second input end. The voltage conversion module is used for converting the gate voltage of the power tube into a target voltage, so that an output stage of the error amplifier works in a saturation region.

2. The low dropout linear regulator of claim 1, wherein, The power tube includes an NMOS tube, correspondingly, the first input end of the error amplifier is a positive input end, and the second input end of the error amplifier is a negative input end; the voltage conversion module is used for reducing the gate voltage of the NMOS tube to a target voltage, so that the output stage of the error amplifier works in the saturation region.

3. The low dropout linear regulator of claim 2, wherein, The voltage conversion module includes a first PMOS tube and a first bias unit; a gate of the first PMOS tube is connected with the output end of the error amplifier, a drain of the first PMOS tube is grounded, a source of the first PMOS tube is connected with the gate of the NMOS tube, and the source of the first PMOS tube is also connected with the first bias unit.

4. The low dropout linear regulator of claim 3, wherein, The first bias unit includes a second PMOS tube, a gate of the second PMOS tube is used for connecting a bias voltage, a source of the second PMOS tube is used for connecting a power supply voltage, and a drain of the second PMOS tube is connected with the source of the first PMOS tube.

5. The low dropout linear regulator of claim 1, wherein, The power tube includes a PMOS tube, correspondingly, the first input end of the error amplifier is a negative input end, and the second input end of the error amplifier is a positive input end; the voltage conversion module is used for increasing the gate voltage of the PMOS tube to a target voltage, so that the output stage of the error amplifier works in the saturation region.

6. The low dropout linear regulator of claim 5, wherein, The voltage conversion module includes a first NMOS tube and a second bias unit; a gate of the first NMOS tube is connected with the output end of the error amplifier, a source of the first NMOS tube is used for connecting a power supply voltage, a drain of the first NMOS tube is connected with the gate of the PMOS tube, and the drain of the first NMOS tube is also connected with the second bias unit.

7. The low dropout linear regulator of claim 6, wherein, The second bias unit includes a second NMOS tube, a gate of the second NMOS tube is used for connecting a bias voltage, a drain of the second NMOS tube is grounded, and a source of the second NMOS tube is connected with the drain of the first NMOS tube.

8. The low dropout linear regulator of claim 1, wherein, The low-dropout linear regulator further includes a zero-point compensation module, the zero-point compensation module is connected with the gate of the power tube, or the zero-point compensation module is connected with the first end of the voltage conversion module.

9. The low dropout linear regulator of claim 8, wherein, The zero-point compensation module includes a first resistor and a first capacitor, a first end of the first resistor is connected with the gate of the power tube or the first end of the voltage conversion module, a second end of the first resistor is connected with a first end of the first capacitor, and a second end of the first capacitor is grounded.

10. An electronic device, comprising: The electronic device comprises the low dropout linear regulator of any one of claims 1-9.

Images