Battery management system, battery pack and electric device

Abstract

The utility model discloses a battery management system, a battery pack and an electric device. The battery management system comprises a circuit board, the circuit board at least comprises a first circuit board and a second circuit board, sampling lines on the first circuit board comprise a first sampling line and a second sampling line, and the first sampling line and the second sampling line are electrically connected with the two ends of a first target battery cell respectively; the sampling lines on the second circuit board comprise a third sampling line and a fourth sampling line, and the third sampling line and the fourth sampling line are electrically connected with the two ends of the second target cell respectively; and the sampling chip is electrically connected with the first, second, third and fourth sampling lines and is used for acquiring a sampling parameter value of the first target battery cell through the first and second sampling lines and acquiring a sampling parameter value of the second target battery cell through the third and fourth sampling lines. According to the embodiment of the invention, the sampling precision and reliability can be improved.

Description

Technical Field

[0001] This application relates to the field of battery management technology, and in particular to a battery management system, a battery pack, and an electrical device. Background Technology

[0002] In new energy vehicles and energy storage systems, the Battery Management System (BMS) is the core system ensuring the safe and stable operation of batteries. The BMS monitors and manages the battery's health status by collecting parameters such as voltage and temperature. Among these, the accurate sampling of battery voltage directly determines the accuracy of the BMS's assessment of battery health status.

[0003] In recent years, plug-in battery management systems (BMS) have become widely adopted. The location and interface definition of the battery voltage sampling connector in a plug-in BMS depend on the battery pack structure. Related technologies are susceptible to external electromagnetic interference in the routing of battery voltage sampling signal lines, leading to decreased sampling accuracy and affecting the accurate assessment of battery performance and safe operation. Utility Model Content

[0004] This application provides a battery management system, a battery pack, and an electrical device, which can effectively improve the anti-interference capability of battery voltage sampling, reduce the impact of external interference on battery voltage sampling, and thus improve the battery voltage sampling accuracy and reliability of the battery management system.

[0005] In a first aspect, this application provides a battery management system electrically connected to a battery pack. The battery pack includes at least a first cell group and a second cell group. The first cell group includes a first target cell, and the second cell group includes a second target cell. The first target cell and the second target cell are electrically connected through a busbar assembly. The system includes: a circuit board, which includes at least a first circuit board and a second circuit board. The sampling lines on the first circuit board include a first sampling line and a second sampling line, which are electrically connected to the two ends of the first target cell, respectively. The sampling lines on the second circuit board include a third sampling line and a fourth sampling line, which are electrically connected to the two ends of the second target cell, respectively. A sampling chip is electrically connected to the first sampling line, the second sampling line, the third sampling line, and the fourth sampling line, and is used to obtain the sampling parameter values ​​of the first target cell through the first sampling line and the second sampling line, and to obtain the sampling parameter values ​​of the second target cell through the third sampling line and the fourth sampling line.

[0006] According to the battery management system provided in this application, the battery management system is electrically connected to a battery pack. The battery pack includes at least a first cell group and a second cell group. The first cell group includes a first target cell, and the second cell group includes a second target cell. The first and second target cells are electrically connected through a busbar assembly. The battery management system includes a circuit board and a sampling chip. The circuit board includes at least a first circuit board and a second circuit board. The sampling lines on the first circuit board include a first sampling line and a second sampling line, which are electrically connected to the two ends of the first target cell, respectively, and can collect the voltage signals at the two ends of the first target cell. The sampling lines on the second circuit board include a third sampling line and a fourth sampling line, which are electrically connected to the two ends of the second target cell, respectively, and can collect the voltage signals at the two ends of the second target cell. The sampling chip is electrically connected to the first, second, third, and fourth sampling lines. The sampling chip can acquire the sampling parameter values ​​of the first target cell through the first and second sampling lines, and the sampling parameter values ​​of the second target cell through the third and fourth sampling lines. In other words, the sampling chip can acquire the voltage across the first target cell through the first and second sampling lines on the first circuit board, and the voltage across the second target cell through the third and fourth sampling lines on the second circuit board. Therefore, two sampling lines connecting the two ends of the same target cell can be located on the same circuit board, allowing the differential sampling lines (two sampling lines connecting the two ends of the same target cell) to be symmetrically arranged. This effectively improves the anti-interference capability of battery voltage sampling, reduces the impact of external interference on battery voltage sampling, and thus improves the battery voltage sampling accuracy and reliability of the battery management system.

[0007] In one possible implementation of the first aspect, the first battery cell group and the second battery cell group are arranged in a first direction, and the third sampling line and the fourth sampling line are adjacent in the first direction.

[0008] The embodiments of this application can ensure that differential sampling lines (such as the third sampling line and the fourth sampling line) can be arranged closely in parallel on the circuit board, which can improve the sampling anti-interference capability.

[0009] In one possible implementation of the first aspect, in the first direction, the third sampling line and the fourth sampling line are equidistant from the center of the second target cell.

[0010] In this embodiment of the application, by maintaining an equidistant and symmetrical arrangement of the differential sampling lines (such as the third and fourth sampling lines) with the center of the corresponding target cell in the first direction, the lengths of the differential sampling lines (the third and fourth sampling lines) can be kept consistent, effectively eliminating the differences in high-frequency noise coupling caused by the difference in line length, and enhancing the anti-interference capability.

[0011] In one possible implementation of the first aspect, different sampling lines on the same circuit board do not intersect.

[0012] The embodiments of this application can use a single-layer circuit board, and different sampling lines on the same circuit board adopt a non-crossing layout. By eliminating crosstalk between lines, sampling accuracy is improved and cost is reduced.

[0013] In one possible implementation of the first aspect, the battery management system further includes a main circuit board and connectors, with the sampling chip located on the main circuit board. The connectors include a first connector and a second connector, the first connector electrically connecting the first circuit board and the sampling chip, and the second connector electrically connecting the second circuit board and the sampling chip.

[0014] This application embodiment uses different circuit boards to electrically connect different connectors, which avoids the problem of excessive insertion and extraction force caused by too many connector pins when one connector connects to multiple circuit boards, making it difficult to insert and remove the connector. It also brings convenience to the production process and improves production efficiency and operability.

[0015] In one possible implementation of the first aspect, the main circuit board further includes a first connecting line and a second connecting line, the first connecting line and the second connecting line being connected between the second connector and the sampling chip, and the first connecting line being electrically connected to the third sampling line and the second connecting line being electrically connected to the fourth sampling line, the first connecting line and the second connecting line being arranged adjacent to each other.

[0016] The embodiments of this application not only ensure that the pair of differential sampling lines (the third sampling line and the fourth sampling line) for sampling the second target cell are arranged closely and in parallel on the same circuit board (the second circuit board), but also enable the first connecting line and the second connecting line that connect the third sampling line and the fourth sampling line to be arranged closely and in parallel on the main circuit board, thereby improving the anti-interference capability of battery voltage sampling.

[0017] In one possible implementation of the first aspect, the sampling chip includes a first sampling circuit and a second sampling circuit;

[0018] The first sampling circuit is electrically connected to the first sampling line and the second sampling line, and is used to obtain the sampling parameter values ​​of the first target battery cell;

[0019] The second sampling circuit is electrically connected to the third and fourth sampling lines and is used to obtain the sampling parameter values ​​of the second target battery cell.

[0020] In this embodiment, the sampling chip connects to the differential sampling lines corresponding to the first and second target cells by setting different sampling circuits, thereby realizing independent acquisition and calculation of voltages of different cells and forming an electrically isolated sampling channel. This avoids measurement errors caused by signal crosstalk and improves the accuracy and reliability of multi-cell voltage sampling.

[0021] In one possible implementation of the first aspect, the second sampling line and the third sampling line are electrically connected to the two ends of the bus component, and the sampling chip further includes a gating circuit for connecting the third sampling line and the second sampling circuit.

[0022] This application embodiment uses a sampling chip with a gating circuit, which can flexibly switch the sampling channels connected to the sampling circuit. The fourth sampling line can be connected to the second sampling circuit as needed to form a sampling channel with the second or third sampling line. This can optimize resource allocation according to actual sampling needs and avoid resource idleness or insufficiency.

[0023] In one possible implementation of the first aspect, the sampling chip is used to collect parameter values ​​of m cells, where m is an integer greater than 1. The sampling chip includes m+1 first-type pins arranged in sequence and at least one spare pin. The second sampling line and the fourth sampling line are electrically connected to two adjacent first-type pins arranged in sequence on the sampling chip, and the third sampling line is connected to the spare pin.

[0024] This embodiment connects the third sampling line to a spare pin of the sampling chip and uses a gating circuit to replace a specific first-type pin with the spare pin, thereby reconstructing the sampling channel. By utilizing the spare resources of the sampling chip, previously idle spare pins can participate in the sampling process, and all sampling circuits within the sampling chip can be fully utilized, improving chip resource utilization and avoiding the cost increase caused by adding additional sampling chips or sampling channels due to resource waste, thus saving costs.

[0025] In one possible implementation of the first aspect, the second sampling line and the third sampling line are electrically connected to the two ends of the bus component, respectively, and the second sampling line, the third sampling line and the fourth sampling line are electrically connected to three first-type pins that are sequentially adjacent on the sampling chip.

[0026] In this embodiment of the application, when the sampling chip does not have spare pins or its spare pins are occupied, all sampling lines can be connected to the first type of pins of the sampling chip in sequence, which can ensure normal sampling function under different chip resource conditions.

[0027] Based on the same technical concept, in a second aspect, embodiments of this application provide a battery pack, including a battery group and a battery management system as described in any one of the embodiments of the first aspect.

[0028] Based on the same technical concept, in a third aspect, embodiments of this application provide an electrical device including a battery pack as described in any embodiment of the second aspect.

[0029] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0030] The features, advantages, and technical effects of exemplary embodiments of this application will now be described with reference to the accompanying drawings.

[0031] Figure 1 A schematic diagram of the structure of a battery management system of the related technology provided in the embodiments of this application;

[0032] Figure 2 This is another schematic diagram of the battery management system provided in an embodiment of this application;

[0033] Figure 3 This is another schematic diagram of the battery management system provided in an embodiment of this application;

[0034] Figure 4 This is another schematic diagram of the battery management system provided in an embodiment of this application;

[0035] Figure 5 This is another schematic diagram of the battery management system provided in an embodiment of this application;

[0036] Figure 6 This is another schematic diagram of the battery management system provided in an embodiment of this application;

[0037] Figure 7 This is another schematic diagram of the battery management system provided in an embodiment of this application;

[0038] Figure 8 This is another schematic diagram of the battery management system provided in an embodiment of this application;

[0039] Figure 9 This is a schematic diagram of a battery pack provided in an embodiment of this application;

[0040] Figure 10 This is a schematic diagram of the structure of an electrical device provided in an embodiment of this application. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0042] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used in the description of this application is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms "comprising" and "having," and any variations thereof, in the description, claims, and accompanying drawings of this application are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the description, claims, or accompanying drawings of this application are used to distinguish different objects, not to describe a specific order or hierarchy.

[0043] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "attachment" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0044] Before describing the technical solutions provided in the embodiments of this application, in order to facilitate understanding of the embodiments of this application, this application first specifically explains the problems existing in the related technologies:

[0045] In new energy vehicles and energy storage systems, the Battery Management System (BMS) is the core system ensuring the safe and stable operation of batteries. The BMS monitors and manages the battery's health status by collecting parameters such as voltage and temperature. Among these, the accurate sampling of battery voltage directly determines the accuracy of the BMS's assessment of battery health status.

[0046] In recent years, plug-in battery management systems (BMS) have become widely adopted. However, the location and interface definition of the battery voltage sampling connector in plug-in BMS are entirely dependent on the battery pack structure and cannot be flexibly adjusted. In contrast, the cell voltage sampling lines of plug-in BMS are integrated and led out from the cell wafer using a flexible printed circuit board (FPC). The BMS connects directly to the FPC connector, eliminating the need for traditional wiring harness adapters.

[0047] The inventors discovered that in the wiring layout of the battery voltage sampling signal line, the differential sampling signal line used to collect the same cell parameters is located on two circuit boards and connected to two connectors respectively, resulting in poor anti-interference capability of the sampling channel for collecting the cell and severe fluctuations after radiated interference injection.

[0048] For example, such as Figure 1 As shown, Figure 1 Two cell groups are shown. One group includes cells CELL1~CELL27, and the other includes cells CELL28~CELL54. A pair of differential sampling lines (i.e., the sampling line connecting sampling point V27 and the sampling line connecting sampling point V28, where sampling point V27 is located at the left end of CELL27 and sampling point V28 is located at the left end of CELL28) used to collect parameters of cell CELL28 are located on circuit boards FPC1 and FPC2, respectively. Circuit boards FPC1 and FPC2 are connected to two connectors. The voltage across cell CELL28 is VCELL28 = V28 - V27. Electromagnetic compatibility (EMC) tests show that the sampling channel has very poor immunity, with severe fluctuations after radiated interference injection. Therefore, in related technologies, the routing of the two differential sampling signal lines used to collect the same cell parameters is relatively arbitrary, making them susceptible to external electromagnetic interference, leading to decreased sampling accuracy and affecting the accurate evaluation of battery performance and safe operation.

[0049] Based on this, embodiments of this application provide a battery management system, a battery pack, and a power-consuming device. By laying out two sampling lines connecting the two ends of the same target cell on the same circuit board, it is possible to support the parallel laying out of two differential sampling lines used to collect the same cell parameters on the same circuit board. This can effectively improve the anti-interference capability of battery voltage sampling, reduce the impact of external interference on battery voltage sampling, and thus improve the battery voltage sampling accuracy and reliability of the battery management system.

[0050] The battery management system provided in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0051] Figure 2 This is a schematic diagram of the structure of a battery management system provided in an embodiment of this application, such as... Figure 2 As shown, the battery management system 100 is electrically connected to the battery pack 200. The battery pack 200 includes at least a first cell group 201 and a second cell group 202. The first cell group 201 includes a first target cell (e.g., CELL27), and the second cell group 202 includes a second target cell (e.g., CELL28). The first target cell and the second target cell are electrically connected through a busbar assembly 300.

[0052] Among them, the battery cell refers to the basic unit (or "battery cell") that can realize the conversion between chemical energy and electrical energy. It is mainly composed of positive electrode material, negative electrode material, electrolyte, separator, etc., and can realize the conversion and storage of electrical energy through internal chemical reactions.

[0053] A battery cell assembly is a single physical module composed of multiple battery cells connected in series, parallel, or a combination of series and parallel connections. A battery cell assembly can also be referred to as a row of battery cells.

[0054] The battery pack 200 may include multiple cell packs to meet the voltage, current, and capacity requirements of different devices. The number of cell packs can be set according to actual needs, and this embodiment of the application is not limited in this respect.

[0055] Different battery cell assemblies can be connected via a busbar assembly 300. In this embodiment, the busbar assembly 300 is used to connect different battery cell assemblies, allowing current to flow smoothly between them. The busbar assembly can be made of conductive materials, such as copper busbars, aluminum busbars, etc. For example, as... Figure 1 As shown, the busbar assembly 300 connects the first target cell CELL27 in the first cell group 201 and the second target cell CELL28 in the second cell group 202. The busbar assembly 300 acts as a bridge to connect the two cells and realize the transmission of electrical energy.

[0056] It should be noted that in this embodiment, the first target cell is CELL27 and the second target cell is CELL28, which are merely illustrative and not intended to limit this application. Of course, in other embodiments, two adjacent cells located in different cell groups connected by the bus assembly 300 can both be referred to as the first target cell and the second target cell.

[0057] See also Figure 2 The battery management system 100 may include a circuit board 10 and a sampling chip 20.

[0058] The circuit board 10 includes at least a first circuit board 11 and a second circuit board 12. The sampling lines on the first circuit board 11 include a first sampling line 111 and a second sampling line 112. The first sampling line 111 and the second sampling line 112 are electrically connected to the two ends of the first target battery cell CELL27, respectively. The sampling lines on the second circuit board 12 include a third sampling line 121 and a fourth sampling line 122, which are electrically connected to the two ends of the second target battery cell CELL28, respectively.

[0059] The sampling chip 20 is electrically connected to the first sampling line 111, the second sampling line 112, the third sampling line 121, and the fourth sampling line 122. It is used to obtain the sampling parameter values ​​(such as voltage values) of the first target cell CELL27 through the first sampling line 111 and the second sampling line 112, and to obtain the sampling parameter values ​​(such as voltage values) of the second target cell CELL28 through the third sampling line 121 and the fourth sampling line 122.

[0060] In this embodiment, circuit board 10 is a printed circuit board (PCB). Specifically, circuit board 10 can be a flexible printed circuit board (FPC), which is a circuit board made of a flexible substrate. It can maintain its electrical performance under different bending or folding conditions and is suitable for various applications requiring flexible circuitry. Of course, in other embodiments, circuit board 10 can also be a rigid printed circuit board (Rigid PCB). Rigid PCBs have high structural strength and can provide stable support and electrical connections for electronic components, and can be selected according to actual needs in battery management systems.

[0061] The sampling chip 20 can be connected via differential sampling lines (two sampling lines connecting the two ends of the same cell, for example...). Figure 2 The first sampling line 111 and the second sampling line 112 in the example, for example Figure 2 The third sampling line 121 and the fourth sampling line 122 in the sampling chip acquire the sampling parameter values ​​(voltage values ​​at both ends of the battery cell) of the battery cell. For example, the sampling chip 20 can be an analog front-end (AFE) sampling chip. The analog front-end sampling chip is at the very beginning of the processing chain, processing analog signals. In the battery management system, the analog front-end sampling chip is used to collect physical quantities such as voltage and temperature of the battery cell, and it sends the collected data back to the central processing unit for processing. The analog front-end sampling chip can have a built-in analog-to-digital converter (ADC), which can convert the analog signals (such as the battery cell voltage signal) collected by the differential sampling lines into digital signals.

[0062] Compared to Figure 1As shown in the example, an additional sampling line (third sampling line 121) is used in this embodiment to ensure that the two differential voltage sampling lines used to unify the battery cells can be arranged in parallel and closely on the same circuit board. That is, the first sampling line 111 and the second sampling line 112 for collecting the voltage across the first target battery cell CELL27 can be arranged in parallel and closely on the same circuit board (first circuit board 11), and the third sampling line 121 and the fourth sampling line 122 for collecting the voltage across the second target battery cell CELL28 can be arranged in parallel and closely on the same circuit board (second circuit board 12).

[0063] According to the battery management system provided in this application embodiment, the sampling chip 20 can collect the voltage across the first target cell CELL27 via the first sampling line 111 and the second sampling line 112 on the first circuit board 11, and collect the voltage across the second target cell CELL28 via the third sampling line 121 and the fourth sampling line 122 on the second circuit board 12. The first sampling line 111 and the second sampling line 112 for collecting the voltage across the first target cell CELL27 are located on the same circuit board (first circuit board 11), and the third sampling line 121 and the fourth sampling line 122 for collecting the voltage across the second target cell CELL28 are located on the same circuit board (second circuit board 12). This allows the differential sampling lines (two sampling lines connecting the two ends of the same target cell) to be laid out on the same circuit board, which can effectively improve the anti-interference capability of battery voltage sampling, reduce the influence of external interference on battery voltage sampling, and thus improve the battery voltage sampling accuracy and reliability of the battery management system.

[0064] The following are exemplary descriptions of some wiring methods for sampling lines on the circuit board in the battery management system provided in the embodiments of this application.

[0065] Figure 3 This is another structural schematic diagram of the battery management system provided in the embodiments of this application.

[0066] In some embodiments, such as Figure 3 As shown, the first battery cell group 201 and the second battery cell group 202 are arranged in the first direction, and the third sampling line 121 and the fourth sampling line 122 are arranged adjacent to each other in the first direction.

[0067] Adjacent arrangement can mean that, in the first direction, there are no other sampling lines between the third sampling line 121 and the fourth sampling line 122. Of course, in other embodiments, the first sampling line 111 and the second sampling line 112 can also be arranged adjacently in the first direction.

[0068] For example, the length of the sampling line connected to the second target cell CELL28 is greater than the length of the sampling line connected to any other cell in the second cell group 202.

[0069] When the lengths of the two sampling lines used to collect data from the same battery cell are large, excessive spacing between the sampling lines can lead to noise coupling differences that cause differential signal distortion. However, this embodiment addresses this by arranging the differential sampling lines (third sampling line 121 and fourth sampling line 122) adjacently on the circuit board. This ensures that the differential sampling lines (third sampling line 121 and fourth sampling line 122) are arranged closely in parallel on the circuit board, making the distance from the interference source to both lines almost the same, thereby improving anti-interference capability.

[0070] The embodiments of this application can ensure that the differential sampling lines (the third sampling line 121 and the fourth sampling line 122) can be arranged closely in parallel on the circuit board, which can improve the sampling anti-interference capability.

[0071] For example, the first sampling line 111 and the second sampling line 112 are arranged adjacent to each other in a first direction. The length of the sampling line (first sampling line 111 and second sampling line 112) connected to the first target cell CELL27 is greater than the length of the sampling line connected to any other cell in the first cell group 201.

[0072] In some embodiments, see [link to relevant documentation]. Figure 3 In the first direction, the distance between the third sampling line 121 and the fourth sampling line 122 and the center of the second target cell CELL28 is equal. Of course, as... Figure 3 As shown, in the first direction, other differential sampling lines can also be arranged equidistantly and symmetrically with the center of the corresponding target cell. For example, in the first direction, the first sampling line 111 and the second sampling line 112 can be equidistant from the center of the first target cell CELL27. Here, "equidistant" allows for a certain degree of error.

[0073] In this embodiment of the application, by maintaining an equidistant and symmetrical arrangement of the differential sampling lines (such as the third sampling line 121 and the fourth sampling line 122) with the center of the corresponding target cell in the first direction, the lengths of the differential sampling lines (the third sampling line 121 and the fourth sampling line 122) can be kept consistent, effectively eliminating the high-frequency noise coupling differences caused by the difference in line length and enhancing the anti-interference capability.

[0074] In some embodiments, see [link to relevant documentation]. Figure 3 Different sampling lines on the same circuit board do not intersect.

[0075] The first circuit board 11 includes 28 sampling lines connecting sampling points V0 to V27, and these lines do not intersect. The second circuit board 12 includes 28 sampling lines connecting sampling points V28 to V54, and these lines do not intersect.

[0076] For example, the sampling line between the sampling point and the connector (e.g.) Figure 3 The traces that overlap with the battery cells can all be located on the circuit board, not just... Figure 3 The traces arranged in a fan shape at the bottom center are located on the circuit board.

[0077] In this application embodiment, a single-layer circuit board can be used, and different sampling lines on the same circuit board adopt a non-crossing layout. For example, the first circuit board 11 is a single-layer circuit board, and different sampling lines on the first circuit board 11 do not cross. As another example, the second circuit board 12 is a single-layer circuit board, and different sampling lines on the second circuit board 12 do not cross. Crosstalk between lines is eliminated by non-crossing routing, which improves sampling accuracy and reduces cost.

[0078] The following are exemplary descriptions of some connection methods between the circuit board and the sampling chip in the battery management system provided in the embodiments of this application.

[0079] In some embodiments, see [link to relevant documentation]. Figure 3 The battery management system 100 also includes a main circuit board 30 and connectors. The sampling chip 20 is located on the main circuit board 30. The connectors include a first connector 41 and a second connector 42. The first connector 41 is electrically connected to the first circuit board 11 and the sampling chip 20, and the second connector 42 is electrically connected to the second circuit board 12 and the sampling chip 20.

[0080] Among them, multiple connectors are electrically connected to multiple circuit boards one by one.

[0081] For example, a connector may include multiple connection pins, which are electrically connected to multiple sampling lines in a one-to-one correspondence. For instance, a first circuit board 11 includes 28 sampling lines for connecting sampling points V0 to V27, and a first connector 41 includes at least 28 connection pins, which are connected to the 28 sampling lines for connecting sampling points V0 to V27 in a one-to-one correspondence.

[0082] For example, the second circuit board 12 includes 28 sampling lines for connecting sampling points V28 to V54, and the second connector 42 includes at least 28 connection pins, which are connected one-to-one with the 28 sampling lines for connecting sampling points V28 to V54.

[0083] In this embodiment, the first connector 41 is electrically connected to the first circuit board 11, and the second connector 42 is electrically connected to the second circuit board 12. Multiple battery cell groups correspond one-to-one with multiple circuit boards, and multiple circuit boards correspond one-to-one with multiple connectors. Of course, in other embodiments, the number of circuit boards can be 3, 4, 5, or more, and the number of connectors must match the number of circuit boards to ensure that each connector can establish an electrical connection with its corresponding circuit board. This embodiment does not limit the specific number of circuit boards.

[0084] For example, multiple connectors can be electrically connected to multiple circuit boards one-to-one via insulation displacement connection (IDC). IDC is a connection technology that achieves electrical contact by mechanically piercing the insulation layer of the wires. The connector has sharp blades or needles (such as V-groove or U-groove structures) inside. When the sampling wires (such as copper or aluminum conductors) from the circuit board are inserted, the blades pierce their insulation layer (such as PVC or PTFE), directly forming reliable direct metal contact with their internal conductors (copper, aluminum, etc.). This eliminates the need for traditional wire stripping or soldering processes, supports parallel connections of multiple wires, and meets the requirements of high-density wiring. Of course, in other embodiments, other connection methods can be used between the circuit board and the connector, such as soldering, plug-in connectors, conductive adhesive, magnetic attraction, etc., and this application embodiment is not limited to these methods.

[0085] If a connector needs to connect to multiple circuit boards, the number of pins required for the connector will be relatively large. However, the embodiments of this application use different connectors that are electrically connected to different circuit boards, which avoids the problem of excessive insertion and extraction force due to too many connector pins, making insertion and extraction difficult. At the same time, it also brings convenience to the production process and improves production efficiency and operability.

[0086] In some embodiments, see [link to relevant documentation]. Figure 3 The main circuit board 30 also includes a first connecting line 31 and a second connecting line 32. The first connecting line 31 and the second connecting line 32 are connected between the second connector 42 and the sampling chip 20. The first connecting line 31 is electrically connected to the third sampling line 121, and the second connecting line 32 is electrically connected to the fourth sampling line 122. The first connecting line 31 and the second connecting line 32 are arranged adjacent to each other.

[0087] Adjacent arrangement refers to the absence of other sampling lines between the two.

[0088] In this embodiment, since the third sampling line 121 and the fourth sampling line 122 transmit differential signals (voltage signals at both ends of the second target chip CELL28), and the third sampling line 121 and the fourth sampling line 122 are arranged on the same circuit board (second circuit board 12), the first connecting line 31 and the second connecting line 32 connecting the third sampling line 121 and the fourth sampling line 122 are connected to the same connector (second connector 42). Therefore, the first connecting line 31 and the second connecting line 32 can be arranged adjacently on the main circuit board 30 and transmit the differential signal to the sampling chip 20. This not only ensures that the pair of differential sampling lines (third sampling line 121 and fourth sampling line 122) for collecting data from the second target cell CELL28 are arranged closely and parallel on the same circuit board (second circuit board 12), but also allows the first connecting line 31 and the second connecting line 32 connecting the third sampling line 121 and the fourth sampling line 122 to be arranged closely and parallel on the main circuit board 30, further improving the anti-interference capability of battery voltage sampling.

[0089] The following describes some structures of the sampling chip of the battery management system provided in the embodiments of this application.

[0090] Figure 4 This is another structural schematic diagram of the battery management system provided in the embodiments of this application.

[0091] In some embodiments, such as Figure 4 As shown, the sampling chip 20 includes a sampling circuit 50, which includes a first sampling circuit 51 and a second sampling circuit 52.

[0092] The first sampling circuit 51 is electrically connected to the first sampling line 111 and the second sampling line 112, and is used to obtain the sampling parameter values ​​of the first target cell CELL27.

[0093] The second sampling circuit 52 is electrically connected to the third sampling line 121 and the fourth sampling line 122, and is used to obtain the sampling parameter values ​​of the second target cell CELL28.

[0094] For example, the first sampling circuit 51 can determine the cell voltage of the first target cell CELL27 based on the voltage difference collected by the first sampling line 111 and the second sampling line 112. The second sampling circuit 52 can determine the cell voltage of the second target cell CELL28 based on the voltage difference collected by the third sampling line 121 and the fourth sampling line 122.

[0095] In this embodiment, the sampling chip 20 connects to the differential sampling lines corresponding to the first target cell CELL27 and the second target cell CELL28 by setting different sampling circuits, thereby realizing independent acquisition and calculation of voltages of different cells and forming an electrically isolated sampling channel. This avoids measurement errors caused by signal crosstalk and improves the accuracy and reliability of multi-cell voltage sampling.

[0096] The following describes a first connection method between the sampling chip and the sampling line of the battery management system provided in this application embodiment. The first connection method can save the sampling channels of the sampling chip.

[0097] Figure 5 This is another structural schematic diagram of the battery management system provided in the embodiments of this application.

[0098] In some embodiments, such as Figure 5 As shown, the second sampling line 112 and the third sampling line 121 are electrically connected to the two ends of the bus assembly 300, respectively. The sampling chip 20 also includes a gating circuit 60, which is used to connect the third sampling line 121 and the second sampling circuit 52.

[0099] The sampling chip consists of multiple first-type pins arranged in sequence. Each pair of adjacent first-type pins forms a sampling channel, and each sampling channel corresponds to a sampling circuit. The number of sampling channels (i.e., the number of sampling circuits) in the sampling chip is a limited resource.

[0100] The gating circuit 60 can flexibly configure the sampling channels connected to the sampling circuit, such as... Figure 5 As shown, the gating circuit 60 can connect the fourth sampling line 122 and the third sampling line 121 to form a sampling channel and connect it to the second sampling circuit 52; alternatively, the gating circuit 60 can connect the fourth sampling line 122 and the second sampling line 112 to form a sampling channel and connect it to the second sampling circuit 52. In this embodiment, the gating circuit 60 is used to connect the fourth sampling line 122 and the third sampling line 121 to form a sampling channel and connect it to the second sampling circuit 52.

[0101] This application embodiment uses a sampling chip 20 with a gating circuit 60, which can flexibly switch the sampling channels connected to the sampling circuit. The fourth sampling line can be connected to the second sampling circuit 52 as needed to form a sampling channel with the second or third sampling line. This can optimize resource allocation according to actual sampling needs and avoid resource idleness or insufficiency.

[0102] Figure 6 This is another structural schematic diagram of the battery management system provided in the embodiments of this application.

[0103] In some embodiments, such as Figure 6As shown, the sampling chip 20 is used to collect parameter values ​​of m cells, where m is an integer greater than 1. The sampling chip 20 includes m+1 first-type pins (such as VC0~VC18) arranged in sequence and at least one spare pin (such as VBB). The second sampling line 112 and the fourth sampling line 122 are electrically connected to two adjacent first-type pins (such as VC9 and VC10) arranged in sequence on the sampling chip. The third sampling line 121 is connected to the spare pin VBB.

[0104] Among them, the spare pins are the pins on the sampling chip other than the first type of pins.

[0105] See Figure 6 The sampling chip 20 includes m+1 first-class pins arranged in sequence (e.g., there are 19 first-class pins in total, including VC0~VC18) and at least one spare pin (e.g., VBB), where m represents the number of sampling channels of the sampling chip 20 (two adjacent first-class pins can form a sampling channel).

[0106] For example, the sampling circuit determines the voltage of cell CELL19 based on the voltage difference between the first type pin VC1 and the first type pin VC0; the sampling circuit determines the voltage of cell CELL20 based on the voltage difference between the first type pin VC2 and the first type pin VC1, and so on. The sampling circuit determines the voltage of cell CELL27 based on the voltage difference between the first type pin VC9 and the first type pin VC8, the sampling circuit determines the voltage of cell CELL128 based on the voltage difference between the first type pin VC10 and the spare pin VBB, and so on.

[0107] See also Figure 6 The output of the gating circuit 60 is connected to its second input (the spare pin VBB connected to the third sampling line 121), and disconnected from its first input (the first type pin VC9 connected to the second sampling line 112). In other words, the spare pin VBB can be used to replace the first type pin VC9 through the gating circuit, that is, the original sampling channel composed of the first type pin VC9 and the first type pin VC10 is replaced with the sampling channel composed of the spare pin VBB and the first type pin VC10, thus realizing the reconstruction of the sampling channel.

[0108] This embodiment connects the third sampling line 121 to the spare pin VBB of the sampling chip 20, and uses the gating circuit 60 to replace a specific first-type pin (such as VC9) with the spare pin VBB, thereby reconstructing the sampling channel. By utilizing the spare resources of the sampling chip, previously idle spare pins can participate in the sampling process, and all sampling circuits within the sampling chip can be fully utilized, improving chip resource utilization and avoiding the cost increase caused by the need for additional sampling chips or sampling channels due to resource waste, thus saving costs.

[0109] The following describes a second connection method between the sampling chip and the sampling line of the battery management system provided in this application embodiment. This second connection method can be used when the sampling chip does not have a spare pin or its spare pin is occupied.

[0110] Figure 7 This is another structural schematic diagram of the battery management system provided in the embodiments of this application.

[0111] In some embodiments, such as Figure 7 As shown, the second sampling line 112 and the third sampling line 121 are electrically connected to the two ends of the bus assembly 300, respectively. The second sampling line 112, the third sampling line 121, and the fourth sampling line 122 are electrically connected to three first-type pins (such as VC9, VC10, and VC11) that are sequentially adjacent on the sampling chip 20.

[0112] Among them, the voltage obtained by the sampling channel corresponding to the two sampling lines connected to the same sampling point is the voltage at both ends of the bus assembly 300, not the cell voltage. For example, the voltage of the sampling channel (the sampling channel composed of VC9 and VC10) corresponding to the second sampling line 112 and the third sampling line 121 is the voltage at both ends of the bus assembly 300.

[0113] For example, the sampling circuit determines the voltage of cell CELL19 based on the voltage difference between the first type pin VC1 and the first type pin VC0; the sampling circuit determines the voltage of cell CELL20 based on the voltage difference between the first type pin VC2 and the first type pin VC1; and so on. The sampling circuit determines the voltage of cell CELL27 based on the voltage difference between the first type pin VC9 and the first type pin VC8; the sampling circuit determines the voltage of cell CELL128 based on the voltage difference between the first type pin VC11 and the first type pin VC10, and so on.

[0114] In this embodiment, when the sampling chip 20 does not have spare pins or its spare pins are occupied, all sampling lines can be connected sequentially to the first type of pins (such as VC0~VC18) of the sampling chip 20, ensuring normal sampling function under different chip resource conditions. In other words, for a front-end analog sampling AFE chip without spare pins, circuit optimization across connectors can be achieved by sacrificing a normal voltage sampling channel.

[0115] Figure 8 This is another structural schematic diagram of the battery management system provided in the embodiments of this application.

[0116] In one embodiment, such as Figure 8As shown, the battery pack 200 contains four cell groups (or four rows of cells), namely the first cell group 201, the second cell group 202, the third cell group 203, and the fourth cell group 204, with each cell group comprising 27 cells. The sampling lines of the cells are connected to the connectors via a flexible printed circuit board (FPC) (the FPC is laid flat on each row of cells) using a crimp-piercing method.

[0117] The circuit board 10 may include a first circuit board 11, a second circuit board 12, a third circuit board 13, and a fourth circuit board 14. The first circuit board 11 corresponds to battery cells CELL1~CELL27, the second circuit board 12 corresponds to battery cells CELL28~CELL54, the third circuit board 13 corresponds to battery cells CELL55~CELL81, and the fourth circuit board 14 corresponds to battery cells CELL82~CELL108.

[0118] The connection method between the sampling line and the pins of the sampling cell is as follows: Figure 6 As shown, for example, each sampling chip can sample the voltage of up to 18 battery cells. Sampling chip 1 samples the voltage of cells CELL1~CELL18, sampling chip 2 samples the voltage of cells CELL19~CELL36, sampling chip 3 samples the voltage of cells CELL37~CELL54, and so on. Alternatively, the connection method between the sampling line and the pins of the sampling cell is as follows: Figure 7 As shown, for example, each sampling chip can collect the voltage of up to 17 cells. Sampling chip 1 collects the voltage of cells CELL1~CELL17, sampling chip 2 collects the voltage of cells CELL18~CELL34, sampling chip 3 collects the voltage of cells CELL35~CELL51, and so on.

[0119] The voltage of cell CELL28 is collected by sampling chip 2. Normally, VCELL28 = V28 - V27. However, in related technologies, the two sampling lines (second sampling line 112 and fourth sampling line 122) connecting sampling points V28 and V27 are distributed across two connectors and two flexible printed circuit boards (FPCs), making the cell voltage sampling susceptible to interference. In this embodiment, an additional sampling line (third sampling line 121) is added to sampling point Vn. By configuring the sampling chip, it can achieve the same function as the second sampling line 112, ensuring that VCELL28 = V28 - Vn. This guarantees that the pair of differential sampling lines (fourth sampling line 122 and third sampling line 121) for collecting data from cell CELL28 are on the same flexible printed circuit board (FPC) and arranged closely in parallel, improving anti-interference capability.

[0120] Based on the same technological concept, such as Figure 9As shown, this application provides a battery pack 1000, including a battery group 200 and a battery management system 100 as described in any of the above embodiments.

[0121] Based on the same technological concept, such as Figure 10 As shown, this application provides an electrical device 2000, including a battery pack 1000 as described in any embodiment of the second aspect.

[0122] The power-consuming device includes the battery pack provided in any of the above embodiments, and the battery pack includes the battery management system provided in any of the above embodiments. Therefore, the power-consuming device and the battery pack have all the beneficial effects of the battery management system described above.

[0123] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other.

[0124] Although this application has been described with reference to preferred embodiments, various modifications can be made thereto and components can be replaced with equivalents without departing from the scope of this application. In particular, the technical features mentioned in the various embodiments can be combined in any manner, provided there is no structural conflict. This application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A battery management system, characterized by, The battery management system is electrically connected with a battery pack, the battery pack at least includes a first cell group and a second cell group, the first cell group includes a first target cell, the second cell group includes a second target cell, the first target cell and the second target cell are electrically connected through a bus assembly, comprising: A circuit board, the circuit board at least includes a first circuit board and a second circuit board, the sampling lines on the first circuit board include a first sampling line and a second sampling line, the first sampling line and the second sampling line are electrically connected to two ends of the first target cell respectively; the sampling lines on the second circuit board include a third sampling line and a fourth sampling line, the third sampling line and the fourth sampling line are electrically connected to two ends of the second target cell respectively; A sampling chip is electrically connected with the first sampling line, the second sampling line, the third sampling line and the fourth sampling line, for acquiring sampling parameter values of the first target cell through the first sampling line and the second sampling line, and acquiring sampling parameter values of the second target cell through the third sampling line and the fourth sampling line.

2. The battery management system of claim 1, wherein, The first cell group and the second cell group are arranged in a first direction, and the third sampling line and the fourth sampling line are adjacent in the first direction.

3. The battery management system of claim 2, wherein, In the first direction, the third sampling line and the fourth sampling line are equal in distance to the center of the second target cell.

4. The battery management system of any one of claims 1 to 3, wherein, Different sampling lines on the same circuit board do not cross.

5. The battery management system of claim 1, wherein, The battery management system further includes a main circuit board and a connector, the sampling chip is located on the main circuit board, the connector includes a first connector and a second connector, the first connector is electrically connected with the first circuit board and the sampling chip, and the second connector is electrically connected with the second circuit board and the sampling chip.

6. The battery management system of claim 5, wherein, The main circuit board further includes a first connecting line and a second connecting line, the first connecting line and the second connecting line are connected between the second connector and the sampling chip, the first connecting line is electrically connected with the third sampling line, the second connecting line is electrically connected with the fourth sampling line, and the first connecting line and the second connecting line are arranged adjacently.

7. The battery management system of claim 1, wherein, The sampling chip includes a first sampling circuit and a second sampling circuit; The first sampling circuit is electrically connected with the first sampling line and the second sampling line, for acquiring sampling parameter values of the first target cell; The second sampling circuit is electrically connected with the third sampling line and the fourth sampling line, for acquiring sampling parameter values of the second target cell.

8. The battery management system of claim 7, wherein, The second sampling line and the third sampling line are respectively electrically connected to two ends of the bus assembly, and the sampling chip further includes a gating circuit, which is used for connecting the third sampling line and the second sampling circuit.

9. The battery management system of claim 8, wherein, The sampling chip is used for collecting parameter values of m cells, m is an integer greater than 1, the sampling chip includes m+1 first type pins and at least one standby pin which are sequentially arranged, the second sampling line and the fourth sampling line are electrically connected to two first type pins which are sequentially arranged on the sampling chip, and the third sampling line is connected to the standby pin.

10. The battery management system of claim 7, wherein, The second sampling line and the third sampling line are electrically connected to two ends of the bus assembly respectively, and the second sampling line, the third sampling line and the fourth sampling line are electrically connected to three first-type pins arranged in sequence and adjacent to each other on the sampling chip.

11. A battery pack, characterized by A battery pack comprising a battery pack and a battery management system as claimed in any of claims 1-10.

12. An electrical device, characterized by A battery pack comprising a battery pack and a battery management system as claimed in any of claims 1-10. A battery pack comprising a battery pack and a battery management system as claimed in any of claims 1-10.

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