Residual voltage monitoring and pressure relief system based on FPGA
The FPGA-based residual pressure monitoring and depressurization system can quickly and accurately detect and automatically depressurize, solving the problems of slow response and low accuracy of traditional residual pressure detection methods, and ensuring the safety of equipment and maintenance personnel.
Patent Information
- Application Number
- CN202520476035.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-18
- Publication Date
- 2025-12-30
- Estimated Expiration
- 2035-03-18
AI Technical Summary
Traditional residual pressure detection methods are slow in response and have low accuracy. They also lack automatic and efficient pressure relief methods, which makes it impossible to deal with safety hazards in a timely manner and poses potential safety risks.
An FPGA-based residual voltage monitoring and pressure relief system is adopted. The pressure relief judgment module, composed of voltage transformer, filter, differential amplifier circuit, level conversion circuit, FPGA and half-bridge drive circuit, realizes fast and accurate detection of residual voltage and automatic pressure relief. The FPGA is used for signal processing and threshold comparison to drive thyristors or relays to relieve pressure.
It enables rapid and accurate measurement of residual pressure and automatic pressure relief, improving response speed, ensuring system safety, and reducing manual intervention and potential safety hazards.
Smart Images
Figure CN223744378U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the technical field of residual voltage discharge, particularly relates to a residual voltage monitoring and discharge system based on FPGA. BACKGROUND
[0002] After the equipment is powered off, although the power supply has been cut off, there may still be a certain voltage remaining in the circuit, which poses a potential risk to the safe operation of the equipment and the personal safety of maintenance personnel. The presence of residual voltage may cause the equipment to malfunction when restarted, or even damage the equipment components. For maintenance personnel, if they inadvertently come into contact with these residual voltages, they may be electrocuted, leading to safety accidents.
[0003] Traditional residual voltage detection methods have many shortcomings. First, their response speed is slow, and they cannot quickly and accurately detect residual voltage in the circuit, which may result in safety hazards that cannot be addressed in a timely manner. Second, the accuracy of traditional detection methods is low, and they may not be able to accurately measure the actual value of the residual voltage, affecting accurate judgment of the equipment status. In addition, traditional residual voltage detection methods also lack automatic and efficient discharge means. Once residual voltage is detected, manual intervention and processing are often required, which not only increases the workload, but also may cause greater safety hazards due to untimely or improper handling. SUMMARY
[0004] The utility model aims at least solve the technical problem existing in prior art, and particularly innovatively provides a residual voltage monitoring and discharge system based on FPGA
[0005] In order to realize the above purpose of the utility model, the utility model provides a residual voltage monitoring and discharge system based on FPGA, which comprises a discharge judgment module and a discharge module, the discharge judgment module comprises: a voltage transformer, a filter, a differential amplification circuit, a level conversion circuit, an FPGA, a half-bridge drive circuit and a resistor;The input end of the voltage transformer is connected with the equipment needing residual voltage monitoring and detection, the output end of the voltage transformer is connected with the input end of the filter, the output end of the filter is connected with the input end of the differential amplification circuit, the output end of the differential amplification circuit is connected with the input end of the level conversion circuit, the output end of the level conversion circuit is connected with the input end of the FPGA, the output end of the FPGA is connected with the input end of the half-bridge drive circuit, the output end of the half-bridge drive circuit is connected with the first end of the resistor, and the second end of the resistor is connected with the power supply ground.
[0006] The residual high voltage of the device is initially reduced to a lower voltage by a voltage transformer, the voltage is converted into two differential signals after passing through a filter circuit with two active low-pass filters and high-pass filters in series, the common-mode signal is suppressed and the differential-mode signal is amplified after passing through a differential amplifier circuit composed of three operational amplifiers, and an external voltage follower is connected to the differential amplifier circuit to raise the voltage, so that the output of the differential amplifier circuit is only positive voltage. The output positive voltage is converted into a 3.3V logic level by a level conversion circuit, input into the chip through the ACD pin of the FPGA chip, and two PWM signals are output after the size comparison between the level and the threshold value is realized in the chip (realized by FPGA programming). If the signal is greater than the threshold value, the two signals are connected to the half-bridge drive circuit to drive the conduction of MOSFET or IGBT, and the external grounding resistor realizes pressure relief. In addition, the residual voltage monitoring is realized by FPGA, when the residual voltage drops to a safe range, the FPGA control circuit stops the pressure relief operation, and the relevant state information is fed back to the upper computer or other monitoring equipment.
[0007] The pressure relief module comprises: the output end of the device is connected to the anode of the thyristor through the output end of the half-bridge drive circuit, and the cathode of the thyristor is connected to the power supply ground through a resistor.
[0008] Preferably, a voltage sensor and a display screen are further included, the input end of the voltage sensor is connected to the output end of the half-bridge drive circuit, and the output end of the voltage sensor is connected to the input end of the display screen.
[0009] Preferably, the voltage transformer and the filter comprise an operational amplifier.
[0010] Preferably, the model of the operational amplifier is AD8065.
[0011] Preferably, the filter is converted into two differential signals by the first filter circuit and the second filter circuit.
[0012] The circuit connection of the first filter circuit and the second filter circuit is the same, and the circuit connection of the first filter circuit is as follows: the input positive terminal of the operational amplifier U3 is connected with the first terminal of the capacitor C4 and the first terminal of the resistor R3, the second terminal of the resistor R3 is connected with the first terminal of the capacitor C5 and the first terminal of the resistor R4, the second terminal of the resistor R4 is connected with the terminal post RF1, and the second terminal of the capacitor C4 is connected with the power supply ground; the positive power supply terminal of the operational amplifier U3 is connected with the power supply, and the negative power supply terminal of the operational amplifier U3 is connected with the power supply ground; the input negative terminal of the operational amplifier U3, the output terminal of the operational amplifier U3, the first terminal of the capacitor C3 and the second terminal of the capacitor C5 are connected, the second terminal of the capacitor C3 is connected with the first terminal of the capacitor C2 and the first terminal of the resistor R6, the second terminal of the capacitor C2 is connected with the first terminal of the resistor R5 and the input positive terminal of the operational amplifier U2, the second terminal of the resistor R5 is connected with the power supply ground, the input negative terminal of the operational amplifier U2 is connected with the second terminal of the resistor R6 and the output terminal of the operational amplifier U2, and the output terminal of the operational amplifier U2 outputs the first differential signal.
[0013] The circuit connection of the second filter circuit is as follows: the input positive terminal of the operational amplifier U7 is connected with the first terminal of the capacitor C9 and the first terminal of the resistor R21, the second terminal of the resistor R21 is connected with the first terminal of the capacitor C10 and the first terminal of the resistor R22, the second terminal of the resistor R22 is connected with the terminal post RF2, and the second terminal of the capacitor C9 is connected with the power supply ground; the positive power supply terminal of the operational amplifier U7 is connected with the power supply, and the negative power supply terminal of the operational amplifier U7 is connected with the power supply ground; the input negative terminal of the operational amplifier U7, the output terminal of the operational amplifier U7, the first terminal of the capacitor C8 and the second terminal of the capacitor C10 are connected, the second terminal of the capacitor C8 is connected with the first terminal of the capacitor C7 and the first terminal of the resistor R25, the second terminal of the capacitor C7 is connected with the first terminal of the resistor R24 and the input positive terminal of the operational amplifier U6, the second terminal of the resistor R24 is connected with the power supply ground, the input negative terminal of the operational amplifier U6 is connected with the output terminal of the operational amplifier U6 and the second terminal of the resistor R25, and the output terminal of the operational amplifier U6 outputs the second differential signal.
[0014] Preferably, the differential amplification circuit is composed of an operational amplifier:
[0015] The input positive terminal of the operational amplifier U1 is connected with the first terminal of the resistor R1, the second terminal of the resistor R1 is connected with the output terminal of the first filter circuit,
[0016] The input negative terminal of the operational amplifier U1 is connected with the first terminal of the resistor R9, the first terminal of the resistor R8, the first terminal of the resistor R12, and the first terminal of the resistor R13,
[0017] The second terminal of the resistor R9 is connected with the first terminal of the slide resistor R15 and the sliding terminal of the slide resistor R15,
[0018] The second end of the resistor R13 is connected with the first end of the resistor R17, the second end of the resistor R12 is connected with the first end of the resistor R16, the second end of the slide resistor R15, the second end of the resistor R16, the second end of the resistor R17 and the first end of the resistor R11 are connected with the input negative end of the operational amplifier U5, the input positive end of the operational amplifier U5 is connected with the first end of the resistor R20, the second end of the resistor R20 is connected with the output end of the second filter circuit,
[0019] The output end of the operational amplifier U1 is connected with the second end of the resistor R8 and the first end of the resistor R7, the second end of the resistor R7 is connected with the input negative end of the operational amplifier U4, the first end of the capacitor C1 and the first end of the resistor R2, the second end of the capacitor C1 and the second end of the resistor R2 are connected with the output end of the operational amplifier U4;
[0020] The second end of the resistor R11 is connected with the first end of the resistor R10 and the output end of the operational amplifier U5, the second end of the resistor R10 is connected with the first end of the resistor R14, the first end of the capacitor C6 and the input positive end of the operational amplifier U4, the second end of the resistor R14 is connected with the first end of the resistor R19, the second end of the capacitor C6 and the first end of the resistor R18, the second end of the resistor R19 is connected with the power supply ground, and the second end of the resistor R18 is connected with the voltage follower.
[0021] Preferably, the voltage follower comprises: the output end of the operational amplifier U8 is connected with the second end of the resistor R18, the first end of the capacitor C12 and the first end of the resistor R27, the second end of the capacitor C12 and the second end of the resistor R27 are connected with the input negative end of the operational amplifier U8, the input positive end of the operational amplifier U8 is connected with the first end of the resistor R23, the first end of the resistor R26 and the first end of the capacitor C11, the second end of the resistor R26 and the second end of the capacitor C11 are connected with the power supply ground, and the second end of the resistor R23 is connected with the power supply.
[0022] Preferably, the silicon-controlled rectifier is replaced by a relay.
[0023] In summary, since the above technical scheme is adopted, the residual voltage signal is collected by the sensor and converted into an electric signal, and after being processed by the signal conditioning circuit, the electric signal is sent to the FPGA core board, the FPGA collects and processes the signal, judges whether the residual voltage exceeds the set threshold, and if yes, generates a control signal to drive the silicon-controlled rectifier or the relay in the pressure relief circuit to act, so that the residual voltage is discharged. At the same time, the feedback and protection circuit monitors the pressure relief process and provides a protection mechanism to ensure the safety of the system.
[0024] The utility model discloses a high-precision sensor and 24 bit ADC realize residual voltage accurate measurement, combine FPGA high -speed processing (microsecond level response) with adaptive algorithm, can quickly trigger silicon controlled rectifier / relay automatic pressure relief, build " detection - release - feedback " closed loop control, realized the promotion of overall response speed.
[0025] The additional aspects and advantages of the utility model will be partly given in the following description, some will become obvious from the following description, or be understood by the practice of the utility model. BRIEF DESCRIPTION OF DRAWINGS
[0026] The above and / or additional aspects and advantages of the utility model will become apparent and more readily understood from the following description, taken in conjunction with the accompanying drawings, in which:
[0027] Figure 1 It is the structure connection schematic drawing of the pressure relief judging part of the utility model.
[0028] Figure 2 It is the circuit connection schematic drawing of the filter circuit and the amplification circuit of the utility model.
[0029] Figure 3 It is the circuit connection schematic drawing of the half bridge output of the utility model. DETAILED DESCRIPTION
[0030] The embodiments of the utility model are described in detail below, the example of the embodiment is shown in the drawings, wherein the same or similar signs represent the same or similar elements or elements with the same or similar function throughout. The embodiments described below by referring to the drawings are exemplary, only for explaining the utility model, and can not be understood as the limitation of the utility model.
[0031] The utility model discloses a residual voltage monitoring and pressure relief system based on FPGA, including pressure relief judging module and pressure relief module, when pressure relief judging module judges to satisfy pressure relief condition, pressure relief module starts;The pressure relief module includes: the output end of equipment is connected with the anode of silicon controlled rectifier through the output end of half bridge drive circuit, and the cathode of silicon controlled rectifier is connected to power supply ground through resistance.
[0032] Wherein the pressure relief judging module is as Figure 1 Shown, including: voltage transformer, filter, differential amplifier circuit, level conversion circuit, FPGA, half bridge drive circuit, voltage sensor, display screen and resistance;The voltage transformer, filter are formed by operational amplifier;
[0033] The input end of the voltage transformer is connected with a device requiring residual voltage monitoring and detection, the output end of the voltage transformer is connected with the input end of the filter, the output end of the filter is connected with the input end of the differential amplification circuit, the output end of the differential amplification circuit is connected with the input end of the level conversion circuit, the output end of the level conversion circuit is connected with the input end of the FPGA, the output end of the FPGA is connected with the input end of the half-bridge drive circuit, the output end of the half-bridge drive circuit is connected with the input end of the voltage sensor and the first end of the resistor respectively, the output end of the voltage sensor is connected with the input end of the display screen, and the second end of the resistor is connected with the power supply ground.
[0034] The high voltage of the device residual is initially reduced to a lower voltage through the voltage transformer, the voltage is converted into two differential signals through a filter circuit in which two active low-pass filters (the signal passes through a 10.23-kilohm resistor first) and a high-pass filter (the signal passes through a 100nF capacitor first) are connected in series, after the two differential signals pass through a differential amplification circuit composed of three operational amplifiers, the common-mode signal is suppressed and the differential-mode signal is amplified, wherein an external voltage follower of the differential amplification circuit raises the voltage, so that the output of the differential amplification circuit has only positive voltage. The output positive voltage is converted into a 3.3V logic level through a level conversion circuit, is input into a chip through the ACD pin of the FPGA chip, and two PWM signals are output after the size comparison between the level and the threshold value is realized in the chip (this process is realized through FPGA programming). If the signal is greater than the threshold value, the two signals are connected to a half-bridge drive circuit to drive the conduction of MOSFET or IGBT, and a connected grounding resistor realizes pressure relief.
[0035] The sensor collects the residual voltage signal of the line and converts it into an electrical signal, which is sent to the FPGA core board after being processed by the signal conditioning circuit. The FPGA collects and processes the signal to determine whether the residual voltage exceeds the set threshold value, and if it does, generates a control signal to drive the silicon controlled rectifier or relay in the pressure relief circuit to act, thereby realizing residual voltage relief. At the same time, the feedback and protection circuit monitors the pressure relief process and provides a protection mechanism to ensure system safety.
[0036] The filter and the differential amplification circuit are both composed of operational amplifiers, and the model of the operational amplifier is AD8065, and the specific connection relationship is shown in Figure 2 .
[0037] The filter is composed of a filter circuit in which two active low-pass filters and a high-pass filter are connected in series, and converts the input signal into two differential signals,
[0038] The circuit connection of the first filter circuit and the second filter circuit is the same, and the circuit connection of the first filter circuit is as follows: the input positive terminal (non-inverting input terminal) of the operational amplifier U3 is connected with the first terminal of the capacitor C4 and the first terminal of the resistor R3, the second terminal of the resistor R3 is connected with the first terminal of the capacitor C5 and the first terminal of the resistor R4, the second terminal of the resistor R4 is connected with the terminal post RF1, and the second terminal of the capacitor C4 is connected with the power supply ground;
[0039] The input negative terminal (inverting input terminal) of the operational amplifier U3 and the output terminal of the operational amplifier U3 are connected with the first terminal of the capacitor C3 and the second terminal of the capacitor C5, the second terminal of the capacitor C3 is connected with the first terminal of the capacitor C2 and the first terminal of the resistor R6, the second terminal of the capacitor C2 is connected with the first terminal of the resistor R5 and the input positive terminal of the operational amplifier U2,
[0040] The second terminal of the resistor R5 is connected with the power supply ground,
[0041] The input negative terminal of the operational amplifier U2 is connected with the second terminal of the resistor R6 and the output terminal of the operational amplifier U2, and the output terminal of the operational amplifier U2 outputs the first differential signal.
[0042] The circuit connection of the second filter circuit is as follows:
[0043] The input positive terminal (non-inverting input terminal) of the operational amplifier U7 is connected with the first terminal of the capacitor C9 and the first terminal of the resistor R21, the second terminal of the resistor R21 is connected with the first terminal of the capacitor C10 and the first terminal of the resistor R22, the second terminal of the resistor R22 is connected with the terminal post RF2, and the second terminal of the capacitor C9 is connected with the power supply ground; the positive power supply terminal of the operational amplifier U7 is connected with the power supply +10V, and the negative power supply terminal of the operational amplifier U7 is connected with the power supply ground;
[0044] The input negative terminal (inverting input terminal) of the operational amplifier U7 and the output terminal of the operational amplifier U7 are connected with the first terminal of the capacitor C8 and the second terminal of the capacitor C10, the second terminal of the capacitor C8 is connected with the first terminal of the capacitor C7 and the first terminal of the resistor R25, the second terminal of the capacitor C7 is connected with the first terminal of the resistor R24 and the input positive terminal of the operational amplifier U6,
[0045] The second terminal of the resistor R24 is connected with the power supply ground,
[0046] The input negative terminal of the operational amplifier U6 is connected with the output terminal of the operational amplifier U6 and the second terminal of the resistor R25, and the output terminal of the operational amplifier U6 outputs the second differential signal.
[0047] Filter is an electronic device that can pass the useful frequency signal while suppressing the useless frequency signal, commonly used in signal processing, data transmission and interference suppression, etc. Active filter is actually an amplifier with specific frequency response, which is composed of some passive elements such as R, C on the basis of operational amplifier.
[0048] The circuit connection of the differential amplification circuit is:
[0049] The input positive terminal (non-inverting input terminal) of the operational amplifier U1 is connected with the first terminal of the resistor R1, the second terminal of the resistor R1 is connected with the output terminal (outputting the first differential signal) of the first filter circuit,
[0050] The input negative terminal (inverting input terminal) of the operational amplifier U1 is connected with the first terminal of the resistor R9, the first terminal of the resistor R8, the first terminal of the resistor R12, the first terminal of the resistor R13,
[0051] The second terminal of the resistor R9 is connected with the first terminal of the slide resistor R15 and the slide terminal of the slide resistor R15,
[0052] The second terminal of the resistor R13 is connected with the first terminal of the resistor R17, the second terminal of the resistor R12 is connected with the first terminal of the resistor R16, the second terminal of the slide resistor R15, the second terminal of the resistor R16, the second terminal of the resistor R17 and the first terminal of the resistor R11 are connected with the input negative terminal (inverting input terminal) of the operational amplifier U5, the input positive terminal (non-inverting input terminal) of the operational amplifier U5 is connected with the first terminal of the resistor R20, the second terminal of the resistor R20 is connected with the output terminal (outputting the second differential signal) of the second filter circuit,
[0053] The output terminal of the operational amplifier U1 is connected with the second terminal of the resistor R8 and the first terminal of the resistor R7, the second terminal of the resistor R7 is connected with the input negative terminal (inverting input terminal) of the operational amplifier U4, the first terminal of the capacitor C1 and the first terminal of the resistor R2, the second terminal of the capacitor C1 and the second terminal of the resistor R2 are connected with the output terminal of the operational amplifier U4;
[0054] The second terminal of the resistor R11 is connected with the first terminal of the resistor R10 and the output terminal of the operational amplifier U5, the second terminal of the resistor R10 is connected with the first terminal of the resistor R14, the first terminal of the capacitor C6 and the input positive terminal (non-inverting input terminal) of the operational amplifier U4, the second terminal of the resistor R14 is connected with the first terminal of the resistor R19, the second terminal of the capacitor C6 and the first terminal of the resistor R18, the second terminal of the resistor R19 is connected with the power supply ground; the second terminal of the resistor R18 is connected with the voltage follower for raising voltage;
[0055] The voltage follower comprises: the output end of the operational amplifier U8 is connected with the second end of the resistor R18, the first end of the capacitor C12 and the first end of the resistor R27, the second end of the capacitor C12 and the second end of the resistor R27 are connected with the input negative end (the inverting input end) of the operational amplifier U8, the input positive end (the non-inverting input end) of the operational amplifier U8 is connected with the first end of the resistor R23, the first end of the resistor R26 and the first end of the capacitor C11, the second end of the resistor R26 and the second end of the capacitor C11 are connected with the power supply ground, and the second end of the resistor R23 is connected with the power supply +10V.
[0056] The differential amplifier circuit is used to remove the direct current component generated by the signal source by amplifying the difference between two signals in a differential manner and outputting the amplifier, and the measurement signal without the direct current component is obtained by subtracting two output signals with a phase difference of 90°.
[0057] The half-bridge driving circuit uses a high-power MOS tube with a model number of EG2131, as shown in the figure. Figure 3 The half-bridge driving circuit uses two switching devices, usually MOSFET or IGBT. One of the switching devices is connected to the positive pole of the power supply, and the other device is connected to the negative pole of the power supply, and the flow direction of the current is controlled by controlling the state of the two switches.
[0058] Based on the above-mentioned residual voltage monitoring and pressure relief system based on FPGA, the working process is as follows:
[0059] 1. Signal acquisition and processing: the sensor converts the line residual voltage signal into an electrical signal, which is processed by the signal conditioning circuit and input to the ADC interface of the FPGA. The FPGA performs analog-to-digital conversion on the collected signals to obtain digital signals.
[0060] 2. Residual voltage judgment: the FPGA internally programs and sets the residual voltage threshold. By analyzing and processing the collected digital signals, such as filtering, comparison and other operations, it is determined whether the current line residual voltage exceeds the set threshold (220V).
[0061] 3. Pressure relief control: when the residual voltage exceeds the threshold, the FPGA outputs a control signal to drive the thyristor in the pressure relief circuit to realize the discharge of the line residual voltage.
[0062] 4. Feedback and protection: during the pressure relief process, the FPGA continuously monitors the change of the line residual voltage, and when the residual voltage drops to a safe range, the pressure relief operation is stopped, and relevant state information can be fed back to the upper computer or other monitoring equipment.
[0063] Although the embodiments of the utility model have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, replacements and variations can be made to these embodiments without departing from the principles and purposes of the utility model, and the scope of the utility model is defined by the claims and their equivalents.
Claims
1. An FPGA-based residual voltage monitoring and pressure relief system, characterized in that, The device comprises a pressure relief judging module and a pressure relief module, the pressure relief judging module comprises a voltage transformer, a filter, a differential amplification circuit, a level conversion circuit, an FPGA, a half-bridge driving circuit and a resistor, wherein the input end of the voltage transformer is connected with a device needing residual voltage monitoring and detection, the output end of the voltage transformer is connected with the input end of the filter, the output end of the filter is connected with the input end of the differential amplification circuit, the output end of the differential amplification circuit is connected with the input end of the level conversion circuit, the output end of the level conversion circuit is connected with the input end of the FPGA, the output end of the FPGA is connected with the input end of the half-bridge driving circuit, the output end of the half-bridge driving circuit is connected with the first end of the resistor, and the second end of the resistor is connected with a power supply ground. The pressure relief module comprises that the pressure relief output end of the device is connected with the anode of a thyristor through the output end of the half-bridge driving circuit, and the cathode of the thyristor is connected to the power supply ground through a resistor.
2. The FPGA-based residual voltage monitoring and pressure relief system of claim 1, wherein, The device further comprises a voltage sensor and a display screen, the input end of the voltage sensor is connected with the output end of the half-bridge driving circuit, and the output end of the voltage sensor is connected with the input end of the display screen.
3. The FPGA-based residual voltage monitoring and pressure relief system of claim 1, wherein, The voltage transformer and the filter comprise an operational amplifier.
4. The FPGA-based residual voltage monitoring and pressure relief system of claim 3, wherein, The model of the operational amplifier is AD8065.
5. The FPGA-based residual voltage monitoring and pressure relief system of claim 1, wherein, The filter converts the input signal into two differential signals by a first filter circuit and a second filter circuit. The circuit connection of the first filter circuit and the second filter circuit is the same, and the circuit connection of the first filter circuit is that the input positive end of the operational amplifier U3 is connected with the first end of the capacitor C4 and the first end of the resistor R3, the second end of the resistor R3 is connected with the first end of the capacitor C5 and the first end of the resistor R4, the second end of the resistor R4 is connected with a terminal post RF1, and the second end of the capacitor C4 is connected with a power supply ground; the positive power supply end of the operational amplifier U3 is connected with a power supply, and the negative power supply end of the operational amplifier U3 is connected with the power supply; the input negative end of the operational amplifier U3, the output end of the operational amplifier U3, the first end of the capacitor C3 and the second end of the capacitor C5 are connected, the second end of the capacitor C3 is connected with the first end of the capacitor C2 and the first end of the resistor R6, the second end of the capacitor C2 is connected with the first end of the resistor R5 and the input positive end of the operational amplifier U2, the second end of the resistor R5 is connected with the power supply ground, the input negative end of the operational amplifier U2 is connected with the second end of the resistor R6 and the output end of the operational amplifier U2, and the output end of the operational amplifier U2 outputs a first differential signal; The pressure relief module comprises that the pressure relief output end of the device is connected with the anode of a thyristor through the output end of the half-bridge driving circuit, and the cathode of the thyristor is connected to the power supply ground through a resistor. The device further comprises a voltage sensor and a display screen, the input end of the voltage sensor is connected with the output end of the half-bridge driving circuit, and the output end of the voltage sensor is connected with the input end of the display screen. The voltage transformer and the filter comprise an operational amplifier. The model of the operational amplifier is AD8065. The filter converts the input signal into two differential signals by a first filter circuit and a second filter circuit. The circuit connection of the first filter circuit and the second filter circuit is the same, and the circuit connection of the first filter circuit is that the input positive end of the operational amplifier U3 is connected with the first end of the capacitor C4 and the first end of the resistor R3, the second end of the resistor R3 is connected with the first end of the capacitor C5 and the first end of the resistor R4, the second end of the resistor R4 is connected with a terminal post RF1, and the second end of the capacitor C4 is connected with a power supply ground; the positive power supply end of the operational amplifier U3 is connected with a power supply, and the negative power supply end of the operational amplifier U3 is connected with the power supply; the input negative end of the operational amplifier U3, the output end of the operational amplifier U3, the first end of the capacitor C3 and the second end of the capacitor C5 are connected, the second end of the capacitor C3 is connected with the first end of the capacitor C2 and the first end of the resistor R6, the second end of the capacitor C2 is connected with the first end of the resistor R5 and the input positive end of the operational amplifier U2, the second end of the resistor R5 is connected with the power supply ground, the input negative end of the operational amplifier U2 is connected with the second end of the resistor R6 and the output end of the operational amplifier U2, and the output end of the operational amplifier U2 outputs a first differential signal; The circuit connection of the second filter circuit is that: the input positive terminal of the operational amplifier U7 is connected with the first terminal of the capacitor C9 and the first terminal of the resistor R21, the second terminal of the resistor R21 is connected with the first terminal of the capacitor C10 and the first terminal of the resistor R22, the second terminal of the resistor R22 is connected with the terminal post RF2, and the second terminal of the capacitor C9 is connected with the power supply ground; the positive power supply terminal of the operational amplifier U7 is connected with the power supply, and the negative power supply terminal of the operational amplifier U7 is connected with the power supply ground; the input negative terminal of the operational amplifier U7, the output terminal of the operational amplifier U7, the first terminal of the capacitor C8 and the second terminal of the capacitor C10 are connected, the second terminal of the capacitor C8 is connected with the first terminal of the capacitor C7 and the first terminal of the resistor R25, the second terminal of the capacitor C7 is connected with the first terminal of the resistor R24 and the input positive terminal of the operational amplifier U6, the second terminal of the resistor R24 is connected with the power supply ground, the input negative terminal of the operational amplifier U6 is connected with the output terminal of the operational amplifier U6 and the second terminal of the resistor R25, and the output terminal of the operational amplifier U6 outputs the second differential signal.
6. The FPGA-based residual voltage monitoring and pressure relief system of claim 1, wherein, The differential amplification circuit is composed of an operational amplifier: The input positive terminal of the operational amplifier U1 is connected with the first terminal of the resistor R1, the second terminal of the resistor R1 is connected with the output terminal of the first filter circuit, The input negative terminal of the operational amplifier U1 is connected with the first terminal of the resistor R9, the first terminal of the resistor R8, the first terminal of the resistor R12 and the first terminal of the resistor R13, The second terminal of the resistor R9 is connected with the first terminal of the sliding resistor R15 and the sliding terminal of the sliding resistor R15, The second terminal of the resistor R13 is connected with the first terminal of the resistor R17, the second terminal of the resistor R12 is connected with the first terminal of the resistor R16, the second terminal of the sliding resistor R15, the second terminal of the resistor R16, the second terminal of the resistor R17 and the first terminal of the resistor R11 are connected with the input negative terminal of the operational amplifier U5, the input positive terminal of the operational amplifier U5 is connected with the first terminal of the resistor R20, the second terminal of the resistor R20 is connected with the output terminal of the second filter circuit, The output terminal of the operational amplifier U1 is connected with the second terminal of the resistor R8 and the first terminal of the resistor R7, the second terminal of the resistor R7 is connected with the input negative terminal of the operational amplifier U4, the first terminal of the capacitor C1 and the first terminal of the resistor R2, the second terminal of the capacitor C1 and the second terminal of the resistor R2 are connected with the output terminal of the operational amplifier U4; The second terminal of the resistor R11 is connected with the first terminal of the resistor R10 and the output terminal of the operational amplifier U5, the second terminal of the resistor R10 is connected with the first terminal of the resistor R14, the first terminal of the capacitor C6 and the input positive terminal of the operational amplifier U4, the second terminal of the resistor R14 is connected with the first terminal of the resistor R19, the second terminal of the capacitor C6 and the first terminal of the resistor R18, the second terminal of the resistor R19 is connected with the power supply ground, and the second terminal of the resistor R18 is connected with the voltage follower.
7. The FPGA-based residual voltage monitoring and pressure relief system of claim 6, wherein, The voltage follower comprises: the output end of the operational amplifier U8 is connected with the second end of the resistor R18, the first end of the capacitor C12 and the first end of the resistor R27; the second end of the capacitor C12 and the second end of the resistor R27 are connected with the input negative end of the operational amplifier U8; the input positive end of the operational amplifier U8 is connected with the first end of the resistor R23, the first end of the resistor R26 and the first end of the capacitor C11; the second end of the resistor R26 and the second end of the capacitor C11 are connected with the power supply ground; and the second end of the resistor R23 is connected with the power supply.
8. The FPGA-based residual voltage monitoring and pressure relief system of claim 1, wherein, The silicon controlled rectifier is replaced by a relay.