Digital high-speed low-phase noise broadband frequency synthesis system
By using a digital high-speed low-phase-noise wideband frequency synthesis system, combined with an ultra-low phase-noise reference clock, low-noise power supply, and high-speed data transmission, the problems of frequency hopping speed and phase noise in phase-locked loop schemes are solved, realizing fast frequency hopping and low-phase-noise wideband signal output, thus improving the testing efficiency and accuracy of vector network analyzers.
Patent Information
- Application Number
- CN202520055592.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-10
- Publication Date
- 2026-01-02
- Estimated Expiration
- 2035-01-10
AI Technical Summary
In existing technologies, phase-locked loop (PLL) solutions cannot simultaneously achieve low phase noise and fast frequency hopping, which limits the scanning speed of vector network analyzers and affects testing efficiency and accuracy.
A digital high-speed, low-phase-noise, wideband frequency synthesis system is adopted, including a reference clock unit, a power supply system, a control system, and a frequency synthesis unit. It utilizes an ultra-low phase-noise temperature-controlled crystal oscillator, a combination of a DC-DC converter and a low-dropout linear regulator, high-speed data transmission, and a DDS chip to achieve a high-frequency, low-jitter reference clock and a low-noise power supply, which are then used in conjunction with the DDS chip for signal processing and output.
It achieves a fast frequency hopping speed of less than 3µs and a phase noise improvement of -105dBc/Hz@4GHz with a frequency offset of 10kHz, and outputs a wideband signal of DC~Fclk*40%, which improves the testing efficiency and accuracy of the vector network analyzer.
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Figure CN223758266U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model belongs to the field of frequency synthesis technology, specifically relates to a kind of digital high-speed low phase noise wideband frequency synthesis system. BACKGROUND
[0002] With the continuous improvement of the measurement accuracy and measurement speed requirements of user to vector network analyzer, the continuous enrichment of frequency converter test, filter test, spectrum test, THz spread spectrum test and other functions, it requires that the frequency synthesis source in vector network analyzer can realize low phase noise and has very fast scanning speed.
[0003] Generally, the wideband frequency synthesis of vector network analyzer adopts phase-locked loop scheme, as shown in Figure 1 The phase-locked loop is a feedback system, which can ensure the stable frequency of the voltage-controlled oscillator (VCO) output, mainly composed of frequency discriminator, loop filter, VCO, fractional divider and reference frequency. The phase discriminator is a phase comparison device, which compares the N-divided frequency of the VCO with the reference frequency and uses the difference output signal to adjust the control voltage applied to the tuning end of the VCO. The loop filter is used to filter out the high-frequency components, output ripple and out-of-band noise generated by the phase discriminator, and take out the average component to control the output frequency of the VCO. The VCO is controlled by the tuning voltage output by the loop filter, and outputs the corresponding signal to make its frequency close to the frequency of the reference signal until the frequency difference disappears and the loop is locked. This scheme cannot output signals lower than the reference frequency, and needs to be combined with other frequency synthesis methods to generate low-frequency signals, which undoubtedly increases the hardware cost and circuit size, and the signal establishment time is relatively long. The frequency hopping speed and phase noise are mutually restricted, the phase-locked loop bandwidth is small, the phase noise is low, and the frequency hopping speed is relatively slow; the loop bandwidth is large, the frequency hopping speed is fast, but the phase noise is relatively large. The phase-locked time is generally more than 10us, which limits the scanning speed of the whole machine, affects the user's test efficiency and test experience in the multi-scan point test of frequency converter, filter, etc., and it is difficult to further improve the phase-locked speed. In order to improve the frequency hopping speed, the single phase-locked loop scheme is usually used, which leads to the fact that the phase noise is not very good, generally-105dBc / Hz@4GHz frequency deviation 10kHz, which will affect the test accuracy of the whole machine in spectrum test, THz spread spectrum test. UTILITY MODEL CONTENTS
[0004] To solve the problems in the prior art, the present application provides a kind of digital high-speed low phase noise wideband frequency synthesis system, which realizes the wideband frequency synthesis of fast frequency hopping while ensuring low phase noise.
[0005] The technical scheme adopted by the application to solve its technical problems is as follows: a kind of digital high-speed low phase noise wideband frequency synthesis system, comprising: reference clock unit, based on ultra-low phase noise thermostat crystal oscillator, high-frequency low-jitter reference clock signal output is realized by the way of frequency multiplication combined with nonlinear transmission line;Power supply system, using DC-DC converter and low dropout linear regulator LDO combination transformer mode, output low phase noise electrical signal;Control system, including signal processing unit and slave controller unit, using local self-defined bus signal transmission mode to realize high-speed data transmission, complete register command fast read-write;Frequency synthesis unit, including DDS chip, filter and low noise amplifier, frequency synthesis unit is connected with output port;The output end of reference clock unit, the output end of power supply system and the output end of control system are all connected to frequency synthesis unit, reference clock unit provides high-frequency low-jitter reference clock to frequency synthesis unit, power supply system supplies power to frequency synthesis unit, and control system sets parameters for frequency synthesis unit.
[0006] Further, a plurality of filters are arranged in the reference clock unit, and an amplifier is connected to the output end of each filter.
[0007] Further, a power filter and a magnetic bead are arranged in the power supply system, the power filter is connected between the DC-DC converter and the low dropout linear regulator LDO, and the magnetic bead is connected to the output end of the low dropout linear regulator LDO.
[0008] Further, in the frequency synthesis unit, a filter and a low noise amplifier are connected between the DDS chip and the output port.
[0009] Further, the control system sends control data 0x3C to write into the register with address 0x000 of the DDS chip, to realize the function of multiple-cycle automatic increment of the register address of the DDS chip.
[0010] Further, the filter in the reference clock unit adopts a band-pass filter, and the amplifier adopts a low phase noise amplifier.
[0011] Further, three filters are arranged in the reference clock unit.
[0012] Further, the power filter adopts a three-terminal filter.
[0013] Further, the filter in the frequency synthesis unit is a band-pass filter.
[0014] Compared with the prior art, the application has the following beneficial effects:
[0015] 1. A digital frequency synthesis method is proposed, which realizes faster frequency hopping speed through high-speed data transmission, optimized register configuration and address bit merging, and the frequency hopping speed can be realized within 3us.
[0016] 2. By using a high-frequency, low-jitter reference clock and a low-noise power supply network, the output signal achieves lower phase noise performance, with a phase noise improvement of 15-20 dBc / Hz compared to the single phase-locked loop scheme.
[0017] 3. It can output a wideband signal of DC to Fclk*40%, and the low-frequency signal is no longer limited by the reference clock;
[0018] In summary, this application uses a digital wideband DDS chip as its core, combined with an external high-frequency low-jitter reference clock, a low-noise power supply system, and a high-speed data control system, to achieve high-speed wideband low-phase-noise signal output from 10MHz to 4GHz. Attached Figure Description
[0019] Figure 1 Here is a block diagram of a phase-locked loop circuit scheme;
[0020] Figure 2 This is a schematic diagram of the technical solution of this application;
[0021] Figure 3 This is a block diagram of the DDS chip parameter setting scheme in Example 2;
[0022] Figure 4 This is a graph showing the frequency hopping speed test results in Example 2.
[0023] Figure 5 This is a phase noise test curve from Example 2. Detailed Implementation
[0024] To facilitate understanding of this application, a more detailed description is provided below with reference to the accompanying drawings and specific embodiments. However, this application can be implemented in many different forms and is not limited to the embodiments described in this specification. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application.
[0025] Example 1: Combination Figure 2To understand, a kind of digital high-speed low-phase noise wideband frequency synthesis system, reference clock unit, with ultra-low phase noise constant temperature crystal oscillator as foundation, high-frequency low-jitter reference clock signal output is realized by the way of frequency multiplication combined with nonlinear transmission line, multiple filters are arranged in reference clock unit, and amplifier is connected at the output end of each filter;Power supply system, using the way of DC-DC converter and low dropout linear regulator LDO combination voltage conversion, output low phase noise electrical signal, power filter and magnetic bead are arranged in power supply system, power filter is connected between DC-DC converter and low dropout linear regulator LDO, magnetic bead is connected at the output end of low dropout linear regulator LDO, filter is mainly to filter out interference or noise by preventing or passing certain specific frequency signals, and magnetic bead eliminates the influence of electromagnetic field by the action of magnetic permeability and impedance, the output voltage of DC-DC converter is 1.2V, 2.4V and 5.6V, and the output voltage of magnetic bead is 1.0V, 1.8V and 3.3V in turn, which is used in combination with voltage supply in the scheme, can improve power supply efficiency, suppress power noise and improve output signal spectrum performance;Control system, including signal processing unit and slave controller unit, realizes high-speed data transmission by using local self-defined bus signal transmission mode, and completes the rapid read and write of register command;Frequency synthesis unit, including DDS chip, filter and low noise amplifier, the DDS chip is connected with the filter, the filter is connected with the low noise amplifier, and the low noise amplifier is connected with the output port;The output end of reference clock unit, the output end of power supply system and the output end of control system are connected to frequency synthesis unit, reference clock unit provides high-frequency low-jitter reference clock to frequency synthesis unit, power supply system supplies power to frequency synthesis unit, and control system sets parameters for frequency synthesis unit.
[0026] In one embodiment, the filter in the reference clock unit adopts a band-pass filter, and the amplifier adopts a low-phase noise amplifier.
[0027] In one embodiment, three filters are arranged in the reference clock unit.
[0028] In one embodiment, the power filter adopts a three-terminal filter.
[0029] In one embodiment, the filter in the frequency synthesis unit is a band-pass filter.
[0030] Through testing, it is found that the frequency hopping speed can be realized within 3us, and if high-speed digital communication mode is used, the frequency hopping speed can be realized within 1us;The phase noise is also improved by 15-20dBc / Hz compared with the single phase-locked loop scheme as shown in Figure 1 The output signal can cover the frequency range of DC to F clk *40% of reference clock.
[0031] Embodiment 2: a digital high-speed low-phase noise wideband frequency synthesis system, as shown in Figure 2 The system takes a digital wideband DDS chip as the core, cooperates with an external high-frequency low-jitter reference clock unit, a low-noise power supply system and a high-speed data control system, and realizes DC-4GHz high-speed wideband low-phase noise signal output.
[0032] The reference clock unit takes an ultra-low phase noise oven-controlled crystal oscillator as the basis, realizes high-frequency low-jitter reference clock signal output through frequency multiplication combined with a nonlinear transmission line, avoids the problems of phase noise deterioration and large circuit volume caused by the multi-stage frequency multiplication circuit in the traditional scheme, simultaneously adopts multi-stage combined filtering in the link to improve spectral purity, adopts a low-phase noise amplifier to improve reference clock driving power, provides a high-frequency low-jitter reference clock F clk for the DDS chip, optimizes the phase noise of the output signal of the DDS chip; the power supply system adopts a DC-DC converter and a low-dropout linear regulator LDO combined voltage conversion method, and is matched with a power filter and a magnetic bead, which can not only improve power supply efficiency, but also suppress power supply noise, reduce the generation of stray signals, and improve the spectral performance of the output signal; the control system adopts a local self-defined bus signal transmission method to realize high-speed data transmission and complete fast reading and writing of register commands; by sending control data 0x3C to write the register at address 0x000 of the DDS chip, the DDS chip register address multi-cycle automatic increment function is realized, the number of register address configurations is reduced, the data transmission time is shortened, and the frequency hopping speed is further improved; the DDS chip output signal is filtered and amplified in the frequency synthesis unit to improve the spectral purity and driving power of the signal, and finally a DC-F clk 40% wideband signal can be output; the connection mode of the scheme is shown in Figure 2 The DDS chip of the frequency synthesis unit is powered by the power supply system; the reference clock unit provides a high-frequency low-jitter reference clock for the DDS chip; the control system provides the data required by the DDS chip; and the overall signal output of the DDS chip is realized.
[0033] The scheme in this embodiment is realized through the following steps:
[0034] S1, the power supply system supplies power to the frequency synthesis unit;
[0035] S2, the reference clock unit provides a high-frequency low-jitter reference clock Fclk to the frequency synthesis unit;
[0036] S3, the control system sets parameters, and understands that the following steps are realized: Figure 3
[0037] S301, a reset command is transmitted from the controller unit FPGA to complete initialization of the DDS chip;
[0038] S302, set the communication mode with the DDS chip from the controller unit FPGA, select the SPI communication protocol as the communication mode;
[0039] S303, transmit the start command from the controller unit FPGA, start the clock receiving function of the DDS chip, and start the power supply of the DAC and the bias circuit of the DDS chip;
[0040] S304, send the port control command from the controller unit FPGA, select the signal generation port of the DDS chip;
[0041] S305, receive and analyze the data sent by the signal processing unit FPGA from the controller unit FPGA, and decode and convert the data to control the sub-channel and main channel of the DDS chip;
[0042] S306, send the sub-channel data of the DDS chip from the controller unit FPGA to drive the sub-channel NCO;
[0043] S307, send the main channel data of the DDS chip from the controller unit FPGA to drive the main channel NCO;
[0044] S4, the DDS chip completes the signal processing of the sub-channel NCO and the main channel NCO, and the frequency synthesis unit realizes signal output.
[0045] The time for the 4GHz point frequency to jump to 1GHz point frequency is tested using a spectrum analyzer, and the result is shown in Figure 4 The phase noise of the 4GHz point frequency is tested using a spectrum analyzer, and the result is shown in Figure 5 and Table 1.
[0046] Table 1: Phase noise statistics of 4GHz point frequency
[0047]
[0048] This embodiment realizes fast frequency hopping while ensuring the low phase noise performance of the output signal, wherein, as shown in Figure 4 D2 shows 2.2us, and compared with the traditional single phase-locked loop, the frequency hopping speed is improved very obviously. If the communication mode between FPGA and DDS is Serdes JESD204B, the frequency hopping speed has very large space for improvement, and the frequency hopping speed can be realized within 1us. As shown in Figure 5 and Table 1, the frequency offset of 10kHz reaches-122dBc / Hz, which is improved very obviously compared with the traditional single phase-locked loop scheme, about 17dB.
[0049] Any technical features in the above-described embodiments can be combined in any manner, and, for the sake of brevity, the foregoing description has not described all possible combinations of the technical features. However, it is contemplated that the scope of the disclosure encompasses all possible combinations of the technical features.
Claims
1. A digitized high-speed low-phase noise wide-band frequency synthesis system, characterized in that, The application relates to a high-frequency low-jitter frequency synthesizer. The reference clock unit is based on a constant-temperature crystal oscillator with ultra-low phase noise, realizes high-frequency low-jitter reference clock signal output through frequency multiplication and a nonlinear transmission line, and outputs a low-phase-noise electric signal through a DC-DC converter and a low-dropout linear voltage regulator (LDO) combination voltage conversion mode. The control system comprises a signal processing unit and a slave controller unit, realizes high-speed data transmission through a local self-defined bus signal transmission mode, and completes fast reading and writing of register commands. The frequency synthesis unit comprises a DDS chip, a filter and a low-noise amplifier, and is connected with an output port. The output end of the reference clock unit, the output end of the power supply system and the output end of the control system are connected to the frequency synthesis unit, the reference clock unit provides high-frequency low-jitter reference clock for the frequency synthesis unit, the power supply system supplies power for the frequency synthesis unit, and the control system sets parameters for the frequency synthesis unit. A plurality of filters are arranged in the reference clock unit, and an amplifier is connected to the output end of each filter.
2. The digitized high-speed low phase noise wide-band frequency synthesis system of claim 1, wherein, A power supply filter and a magnetic bead are arranged in the power supply system, the power supply filter is connected between the DC-DC converter and the low-dropout linear voltage regulator (LDO), and the magnetic bead is connected to the output end of the low-dropout linear voltage regulator (LDO).
3. The digitized high-speed low phase noise wide-band frequency synthesis system of claim 2, wherein, In the frequency synthesis unit, the DDS chip is connected with the filter and the low-noise amplifier between the output port.
4. The digitized high-speed low phase noise wide-band frequency synthesis system of claim 3, wherein, The control system realizes the DDS chip register address multi-cycle automatic increment function by sending control data 0x3C to write the register with the address of 0x000.
5. The digitized high-speed low phase noise wide-band frequency synthesis system according to any of claims 1-4, characterized in that, The filter in the reference clock unit adopts a band-pass filter, and the amplifier adopts a low-phase-noise amplifier.
6. The digitized high-speed low phase noise wide-band frequency synthesis system according to any of claims 2-4, characterized in that, Three filters are arranged in the reference clock unit.
7. The digitized high-speed low phase noise wide-band frequency synthesis system of claim 6, wherein, The power supply filter adopts a three-terminal filter.
8. The digitized high-speed low phase noise wide band frequency synthesis system of claim 2 or 3, wherein, The filter in the frequency synthesis unit is a band-pass filter.
9. The digitized high-speed low phase noise wide-band frequency synthesis system of claim 4, wherein,