LDMOS device and integrated circuit
By introducing a P-type radiation hardening buffer and an isolation region to isolate the source and drain regions in the LDMOS device, the problem of total dose irradiation effect is solved, and the radiation resistance is improved without changing the main structure and process of the device, thus reducing the impact on performance.
Patent Information
- Application Number
- CN202520006622.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-02
- Publication Date
- 2026-01-06
- Estimated Expiration
- 2035-01-02
AI Technical Summary
When improving the radiation resistance of LDMOS devices, conventional methods change the main structure and size of the device, affecting performance, and the process is complex, which cannot effectively solve the problem of total dose irradiation effect.
In LDMOS devices, a radiation hardening buffer is introduced around the source region. By setting up a P-type radiation hardening buffer and an isolation region to isolate the source and drain regions, a lightly doped P-type buffer is formed using existing processes to prevent the formation of leakage channels under total dose irradiation.
Without altering the main structure and process of the device, the radiation hardening capability was improved, the total effect of total dose radiation was reduced, the formation of leakage current channels in the device was decreased, the radiation resistance of the device was enhanced, and the impact on performance was reduced.
Smart Images
Figure CN223772421U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor technology, specifically to an LDMOS device and integrated circuit. Background Technology
[0002] Electronic systems used in special applications such as aerospace, aviation, and space stations have high requirements for the radiation resistance of components (including integrated circuits). The radiation effects on electronic components are most typically total dose radiation effect and single-event effect. Among them, the total dose radiation effect is mainly due to the charge accumulation effect caused by the disruption of SiO2 bonds in the isolation region of the device by cosmic rays.
[0003] Conventional total dose radiation hardening methods are categorized into three levels: system-level, device-level, and process-level. System-level radiation hardening primarily relies on redundant design, which significantly improves radiation resistance but consumes substantial chip space and is costly. Device-level radiation hardening mainly involves specialized device structure design to enhance total dose radiation resistance. Typical methods include ring gates, big-head gates, inverted proportional gates, and P+ guard rings. While these methods effectively improve radiation resistance, they severely limit channel dimensions, significantly impacting device performance and creating complex gate shapes, thus posing significant constraints on design, manufacturing processes, and parameter modeling. Process-level radiation hardening, for example, involves high-concentration silicon surface implantation at the bottom of the isolation region to increase the difficulty of inversion and thus improve radiation resistance. While this method can improve radiation resistance to some extent, it cannot fundamentally solve the problem of total dose radiation effects.
[0004] Therefore, how to solve the total dose irradiation problem and reduce the impact on device performance without changing the main structure, size and process of the device as much as possible is an urgent problem to be solved in the field of radiation resistance. Utility Model Content
[0005] To overcome the above-mentioned defects, this utility model is proposed to solve the total dose irradiation problem and reduce the impact on device performance while minimizing changes to the main structure, size and process of the device.
[0006] In a first aspect, this utility model provides an LDMOS device, which includes:
[0007] Substrate of the first conductivity type;
[0008] A second type of conductivity well region extends from the surface of the substrate into the substrate;
[0009] The drift region of the second conductivity type is located on one side of the well region;
[0010] The body region of the first conductivity type is located on the other side of the well region;
[0011] A gate structure comprising a stacked gate dielectric layer and a gate, wherein the gate structure covers a portion of the body region and a portion of the drift region;
[0012] A source / drain injection region of a first conductivity type is located inside the well region. The source / drain injection region includes a source region and a drain region. A channel region is formed between the source region and the drain region. The source region and the drain region are located on opposite sides of the gate structure, respectively. The source region is located within the body region, and the drain region is located within the drift region.
[0013] A radiation hardening buffer zone of the first conductivity type is located inside the body region and surrounds the source region;
[0014] An isolation region is located on the surface of the substrate, and the orthographic projection of the isolation region on the substrate surface surrounds the orthographic projection of the radiation hardening buffer zone on the substrate surface, and surrounds the orthographic projection of the drain region on the substrate surface.
[0015] Furthermore, in the LDMOS device described above, the doping concentration of the radiation hardening buffer and the doping concentration of the body region are both light doping concentrations;
[0016] Both the source region and the drain region have heavy doping concentrations.
[0017] Furthermore, in the LDMOS device described above, the radiation hardening buffer and the body region are formed using the same process.
[0018] Furthermore, in the LDMOS device described above, the width of the radiation hardening buffer is between 0.1µm and 1µm.
[0019] Furthermore, in the LDMOS device described above, the source / drain injection region includes a first sub-injection region surrounding the source region and a second sub-injection region surrounding the drain region; wherein the first sub-injection region is connected to the second sub-injection region;
[0020] The first sub-injection region includes a first side along the gate width direction, a second side along the gate width direction, and a third side along the gate length direction, wherein the orthographic projections of the first side and the second side on the substrate surface extend into the orthographic projection of the gate on the substrate surface.
[0021] Furthermore, in the LDMOS device described above, the distance d1 by which the orthographic projections of the first side and the second side onto the substrate surface extend into the orthographic projection of the gate onto the substrate surface satisfies the following condition:
[0022] 10 < d1 < 100 nm.
[0023] Furthermore, in the LDMOS device described above, the isolation region employs dielectric isolation.
[0024] Furthermore, the LDMOS device described above also includes:
[0025] A lightly doped drain region is located between the drain region and the channel region.
[0026] Secondly, this utility model provides an integrated circuit, including at least one LDMOS device as described in any of the preceding claims.
[0027] The LDMOS device and integrated circuit provided by this utility model isolate the source and drain regions from the isolation region by setting a radiation hardening buffer around the source region. In this way, the main structure of the original LDMOS device is relatively small and the process is relatively simple. Under the premise of ensuring the channel length between the source and drain regions, even if the total dose irradiation effect causes the silicon surface layer under the entire isolation region to be inverted, the existence of the radiation hardening buffer prevents the formation of a leakage path between the source and drain regions. Theoretically, this can completely solve the impact of total dose irradiation on the device and improve the radiation resistance. Attached Figure Description
[0028] The disclosure of this utility model will become more readily understood with reference to the accompanying drawings. It will be readily understood by those skilled in the art that these drawings are for illustrative purposes only and are not intended to limit the scope of protection of this utility model. Furthermore, similar numbers in the drawings are used to denote similar structures or areas, wherein:
[0029] Figure 1 This is a schematic diagram of the structure of an existing N-type LDMOS device;
[0030] Figure 2 yes Figure 1 Cross-sectional view along line AA;
[0031] Figure 3 This is a schematic diagram of an NMOS structure in an existing CMOS device;
[0032] Figure 4 This is a schematic diagram of the structure of an N-type LDMOS device according to an embodiment of the present invention;
[0033] Figure 5 yes Figure 4 Cross-sectional view along line BB. Detailed Implementation
[0034] To make the above-mentioned objects, features, and advantages of this utility model more apparent and understandable, the specific embodiments of this utility model will be described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a full understanding of this utility model. However, this utility model can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this utility model. Therefore, this utility model is not limited to the specific embodiments disclosed below.
[0035] In the description of this utility model, the terms "first," "second," etc., are used for descriptive and distinguishing purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Furthermore, in this utility model, unless otherwise expressly specified and limited, the terms "connected," "linked," etc., should be interpreted broadly; for example, they can refer to a direct connection or an indirect connection through an intermediate medium, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.
[0036] Total Ionizing Dose Effect (TID) refers to the cumulative dose absorbed by a sample during irradiation. It is the ionizing radiation effect of cumulative dose and the process by which cumulative irradiation leads to device failure. The region most sensitive to the TID effect is the area on the substrate surface covered by the isolation region. For conventional Laterally Diffused Metal Oxide Semiconductor (LDMOS) processes, STI (Shallow Trench Isolation) or LOCOS (Local Oxidation of Silicon) isolation techniques are often used due to the need for physical isolation. The STI or LOCOS region is the isolation region in direct contact with the Si substrate, and therefore is most sensitive to TID.
[0037] Figures 1 to 2 Taking an N-type LDMOS device using LOCOS isolation technology as an example, the total dose irradiation effect is explained. Figure 1As shown, a conventional N-type LDMOS device includes an active region 1 and an isolation region 2, wherein the isolation region 2 uses dielectric isolation. The active region 1 forms the main structure of the device, including an N+ source region 11, an N+ drain region 12, and a channel region defined by the gate structure 7. The N+ source region 11 and the N+ drain region 12 are located on both sides of the channel region. The area outside the active region 1 is the isolation region 2, where the silicon surface is covered with a thick oxide layer to form a physical isolation region between devices. As those skilled in the art will know, this N-type LDMOS device may also include a P-type substrate 3, an N-well region 4, an N+ source / drain injection region 5', an N-drift region 10, and a P-body region 20. The N-well region 4 extends from the surface of the P-type substrate 3 into the P-type substrate 3. The N-drift region 10 is located on one side of the N-well region 4, and the N+ drain region 12 is located within the N-well region 4. The P-body region 20 is located on the other side of the N-well region 4, and the N+ source region 11 is located within the P-body region 20. The N+ source / drain implantation region 5' is located within the N-well region 4 and is used only for implantation of the N+ source / drain regions 11 and 12 and the polygate. Due to the obstruction of the thick oxide layer in the isolation region 2, N+ source / drain implantation cannot actually be injected into the underlying P-type substrate 3. Here, P-type can be used as the first conductivity type, and N-type can be used as the second conductivity type.
[0038] like Figure 2 As shown, without irradiation, the N+ source region 11 is electrically isolated from the N-well region 4, N-drift region 10, and N+ drain region 12 through the P-body region 20, thus blocking the leakage path between the source and drain. However, after total dose irradiation, a large number of electron-hole pairs are generated in the thick oxide layer. Due to their lighter mass, electrons escape from the silicon oxide layer through the surface barrier of the SiO2 / Poly gate under the action of the electric field. Holes, due to their heavier mass and higher interface barrier, cannot cross the SiO2 / Si interface and gradually accumulate at the interface under the action of the electric field, forming a cluster of positive charges. The thicker the oxide layer, the more significant this charge accumulation effect, that is, the more severe the damage to the oxide layer caused by the irradiation. When the charge accumulates to a certain extent, the resulting positive electric field will cause the surface layer of the P-body region 20 (i.e., below the isolation region 2 corresponding to region C circled in the figure) to invert, creating a potential leakage path between the source and drain. Figure 2 (As indicated by the arrow), which in turn leads to device leakage. Therefore, for N-type LDMOS devices, total dose irradiation is mainly due to the accumulation of positive charges causing inversion of the P-body region 20 at the bottom of the field region, thus forming a potential leakage channel and ultimately weakening the isolation effect of the field region.
[0039] Generally, considering both cost and radiation resistance, device structure optimization is a relatively ideal radiation hardening solution. However, in practical applications, when optimizing the structure of complex high-voltage devices such as LDMOS devices in BCD process platforms, it has been found that using the same structural optimization methods as for CMOS devices provides relatively limited improvement in radiation resistance.
[0040] Specifically, such as Figure 3 The NMOS structure in the CMOS device may include an active region 1' and an isolation region 2', wherein the isolation region 2' employs dielectric isolation. The active region 1' forms the main structure of the device, including the channel region defined by the N+ source region 11', the N+ drain region 12', and the gate structure 7', with the N+ source region 11' and the N+ drain region 12' located on both sides of the channel region. The area outside the active region 1' is the isolation region 2', where the silicon surface is covered with a thick oxide layer to form a physical isolation region between devices. As will be known to those skilled in the art, the NMOS device may further include a P-type substrate 3', a P-well region 4', and an N+ source / drain injection region 5'". The P-well region 4' extends from the surface of the P-type substrate 3' into the P-type substrate 3'. The N+ drain region 12' is located within the P-well region 4'. The N+ source / drain injection region 5' is located within the P-well region 4' and is used only for the injection of N+ source regions 11' and N+ drain regions 12'. Due to the obstruction of the thick oxide layer, N+ source / drain injection cannot actually be injected into the substrate 3' under the isolation region 2'. P-type can be used as the first conductivity type, and N-type can be used as the second conductivity type.
[0041] See also Figure 3 To improve the radiation resistance of CMOS devices, a P+ type isolation ring 8' is formed in the active region 1. The P+ type isolation ring 8' isolates the source / drain region from the isolation region, similar to adding an "isolation strip" between the source / drain region and the isolation region, preventing leakage current channels from forming between the source and drain due to radiation through the thick oxide layer. Although this scheme can effectively improve the radiation resistance of the device, it also has obvious shortcomings: (1) The isolation region includes the outer buffer N+ active region 9' and the P+ type isolation ring 8', which occupies a large device area. (2) The P+ type isolation ring 8' directly contacts the N+ source / drain to form a double-sided abrupt PN junction, which has a significant impact on the device's withstand voltage, especially for the drain region that requires high voltage withstand.
[0042] It should be noted that, Figure 3 Due to the presence of the P+ type isolation ring 8', the N+ source-drain injection region 5' is actually the region excluding the P+ type isolation ring 8'.
[0043] refer to Figure 1 and Figure 3 Compared to Figure 3 CMOS devices, Figure 1LDMOS devices have a more complex structure, with the following specific differences:
[0044] First, the source / drain of the LDMOS device is no longer symmetrically distributed with respect to the gate, and is not on the same active region 1;
[0045] Second, the isolation region 2 of the LDMOS device occupies a larger area (isolation region 2 is a weak radiation resistance region), and the active region 1 where the source / drain is located is also divided by the isolation region, resulting in a larger contact area between the active region of the source / drain and the field oxygen dielectric of the isolation region, and higher requirements for radiation hardening.
[0046] Third, in order to improve the breakdown voltage of the device, the N+ drain region 12 has a large area of N-drift region 10 covering the drain region. The N-drift region 10 makes a part of the silicon under the isolation region 2 also N-type, further reducing the source / drain region spacing and increasing the risk of leakage.
[0047] Fourth, the drain region of LDMOS devices needs to withstand higher voltages (6–100V). Therefore, traditional radiation hardening methods, such as P+ guard rings, have a more significant impact on the intrinsic performance of these devices, posing a greater challenge to improving the radiation resistance of LDMOS through traditional device structure optimization.
[0048] Fifth, the entire LDMOS is in the background of the N-well region 4. Even without the inversion caused by total dose irradiation, most of the area under the isolation region of this device is N-type, which makes it easier to cause leakage between the source and drain.
[0049] In summary, all the aforementioned situations pose significant challenges to improving the radiation resistance of NLDMOS through traditional device structure optimization methods. Therefore, to address these technical problems, this invention adopts the following technical solution.
[0050] Figure 4 This is a schematic diagram of the structure of an N-type LDMOS device according to an embodiment of the present invention. Figure 5 yes Figure 4 A cross-sectional view along line BB. (See attached image.) Figures 4 to 5 As shown, this LDMOS device in Figure 1 Based on the LDMOS device shown, the mask layout of the N+ source / drain injection region 5' is optimized to obtain the following: Figure 4The shape of the mask pattern for the N+ source / drain injection region 5 ensures that after the injection of N+ source region 11 and N+ drain region 12, N+ source region 11 and isolation region 2 are no longer in direct contact. Instead, a P-type ring 6, or radiation hardening buffer 6, is formed between them. This P-type radiation hardening buffer 6 surrounds N+ source region 11, and the orthogonal projection of isolation region 2 on the surface of P-type substrate 3 surrounds the orthogonal projection of radiation hardening buffer 6 on the surface of P-type substrate 3, as well as the orthogonal projection of N+ drain region 12 on the surface of P-type substrate 3. Thus, when charge accumulates to a certain level, the resulting positive electric field inverts the surface layer of P-body region 20 near the interface, but due to the presence of the P-type radiation hardening buffer 6, a leakage path cannot be formed between N+ source region 11 and N+ drain region 12.
[0051] See also Figure 1 and Figure 5 The LDMOS device in this embodiment is relative to Figure 1 For the LDMOS device shown, the gate, source, and drain regions remain basically unchanged, so it does not impose a significant constraint on the design of the LDMOS device. Furthermore, the P-type radiation hardening buffer 6 is only located in the N+ source region 11, which has a smaller impact on the N+ drain region 12 of the LDMOS, resulting in a relatively small impact on the overall performance of the LDMOS.
[0052] In this embodiment, the LDMOS device isolates the source and drain regions from the isolation region 2 by setting a radiation hardening buffer 6 around the source region. This results in relatively minor changes to the main structure of the original LDMOS device and a relatively simple process. Under the premise of ensuring the channel length between the source and drain regions, even if the total dose irradiation effect causes the silicon surface layer under the well region 4 and the entire isolation region 2 to be inverted, the presence of the radiation hardening buffer 6 prevents the formation of a leakage current path between the source and drain regions, greatly reducing the impact of total dose irradiation on the device.
[0053] In a specific implementation, the P-type radiation hardening buffer 6 is of P-conductivity, allowing the doping concentration of the radiation hardening buffer 6 to be the same as that of the P-bulk region 20. This enables the formation of both the P-radiation hardening buffer 6 and the P-bulk region 20 using the same process step. Figure 1 Compared to the previous process, no additional process is required. That is, after forming the P-body region 20, the N+ source-drain injection region 5 according to this scheme is used for injection. The P-body region 20 between the N+ source region 11 and the N+ drain region 12 and the isolation region 2 serves as the P-type radiation hardening buffer zone 6.
[0054] In a specific implementation, since the doping concentration of the radiation hardening buffer 6 is lightly doped, while the doping concentrations of the source region and the drain region are both heavily doped, this ensures that the depletion region between the P- radiation hardening buffer 6 and the N+ source region 11 is relatively wide. Furthermore, since the P- radiation hardening buffer 6 is only located in the N+ source region 11, the withstand voltage capability of the N+ drain region 12 will not be affected by the setting of the radiation hardening buffer 6.
[0055] In a specific implementation, the wider the P-irradiation buffer, the better. However, considering the actual chip area limitations, the width of the P-irradiation buffer can be set between 0.1µm and 1µm depending on the different technology nodes.
[0056] See also Figure 3 and Figure 4 , Figure 3 In the CMOS device shown, the parasitic PN junction in the source region is a double-sided abrupt junction, while Figure 4 The parasitic PN junction in the source region of the LDMOS device is a single-sided abrupt junction, resulting in a gentler concentration gradient in the P-type region and stronger breakdown voltage. This not only enhances radiation resistance but also reduces adverse effects on device performance, and requires no additional processing steps, leading to lower costs. Furthermore, the area occupied by the P-radiation hardening buffer 6 is relatively small compared to... Figure 3 The P+ type isolation ring 8' occupies a smaller area and has a greater cost advantage.
[0057] In one specific implementation, the LDMOS device also includes a lightly doped drain region (LDD) (not shown in the figure). The conventional LDD region covers all active regions of the device, which is called general injection. Such lightly doped drain region injection may neutralize or even invert the P-buffer in this invention. Therefore, the injection of the lightly doped drain region in this invention is changed from the general injection in the active region in the prior art to injection based on the mask layout of the optimized N+ source-drain injection region 5.
[0058] See also Figure 4 The N+ source-drain injection region 5 includes a first sub-injection region 51 surrounding the N+ source region 11 and a second sub-injection region 52 surrounding the N+ drain region 12; wherein the first sub-injection region 51 and the second sub-injection region 52 are connected, so that the N+ source-drain injection region 5 forms a closed region.
[0059] like Figure 5As shown, the first sub-implantation region 51 includes a first side 511 along the gate width direction, a second side 512 along the gate width direction, and a third side 513 along the gate length direction. The orthographic projections of the first side 511 and the second side 512 onto the surface of the substrate 3 extend into the orthographic projection of the gate onto the surface of the substrate 3, wherein the penetration distance d1 satisfies the following condition: 10 < d1 < 100 nm. This arrangement is to ensure that even if there are fluctuations in the N+ source-drain injection lithography alignment during mass production, at least one of the N+ source region 11 and / or the N+ drain region 12 will not directly contact the isolation region 2, thereby ensuring that no leakage path will appear between the N+ source region 11 and the N+ drain region 12.
[0060] Unless otherwise specified, in the description of this embodiment, the gate width direction refers to the direction from the source region to the drain region or from the drain region to the source region (corresponding to the horizontal direction in the figure), that is, the gate width direction is consistent with the channel length direction; the gate width direction is perpendicular to the gate length direction (corresponding to the vertical direction in the figure).
[0061] In a specific implementation process, the LDMOS device of the above embodiment can be obtained by following the fabrication process flow:
[0062] S1, forming N-well region 4;
[0063] S2, forming an N-drift region 10;
[0064] S3, forming active region 1;
[0065] S4, forming gate oxide;
[0066] S5, forming a polycrystalline gate;
[0067] A thin gate oxide layer is formed on the N-well region 4, and a polysilicon layer is formed on the thin gate oxide layer to form a polysilicon gate. The specific formation process can be referred to existing related technologies, and will not be described in detail here.
[0068] S6. Inject P-body region 20;
[0069] S7. Perform NLDD region injection;
[0070] Masking of NLDD region and N+ source / drain injection region 5 Figure 1 This is different from the NLDD region injection in existing technologies, which involves general injection in the active region.
[0071] S8. Forming side walls;
[0072] The process for forming the sidewalls can be referenced from existing related technologies, and will not be elaborated here.
[0073] S9. Inject N+ source region 11 and N+ drain region 12, and simultaneously form P-radiation hardening buffer zone 6;
[0074] Because the injected doses of N+ source region 11 and N+ leak region 12 are much greater than those of P-body region 20, in order to prevent the general injection of existing technology from reversing the P-body region 20, this case must be handled in accordance with... Figure 4 The optimized N+ source-drain injection region 5 is used to inject N+ source region 11 and N+ drain region 12. The P-body region 20 between N+ source region 11 and isolation region 2 is used as P-radiation hardening buffer 6.
[0075] S10, metal silicide process;
[0076] S11, Contact hole process;
[0077] S12, metal interconnect process.
[0078] The forming processes of S1 to S6, S8, and S10 to S11 can be referred to existing related technologies, and will not be elaborated here.
[0079] The technical solution of this utility model has been described above with reference to the preferred embodiments shown in the accompanying drawings. However, it will be readily understood by those skilled in the art that the protection scope of this utility model is obviously not limited to these specific embodiments. Without departing from the principle of this utility model, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will all fall within the protection scope of this utility model.
Claims
1. An LDMOS device, characterized by, Comprising: a substrate of a first conductivity type; a well region of a second conductivity type extending from a surface of the substrate into the substrate; a drift region of the second conductivity type located in one side of the well region; a body region of the first conductivity type located in another side of the well region; a gate structure, the gate structure comprising a gate dielectric layer and a gate electrode stacked, and the gate structure covering part of the body region and part of the drift region; a source-drain implant region of the first conductivity type located inside the well region, the source-drain implant region comprising a source region and a drain region, a channel region being formed between the source region and the drain region, the source region and the drain region being located on two sides of the gate structure respectively, and the source region being located in the body region and the drain region being located in the drift region; a radiation-hardened buffer region of the first conductivity type located inside the body region and surrounding the source region; an isolation region located on the surface of the substrate, and a projection of the isolation region on the surface of the substrate surrounding a projection of the radiation-hardened buffer region on the surface of the substrate, and a projection of the drain region on the surface of the substrate.
2. The LDMOS device of claim 1, wherein: a doping concentration of the radiation-hardened buffer region is the same as a doping concentration of the body region.
3. The LDMOS device of claim 2, wherein: the doping concentration of the radiation-hardened buffer region and the doping concentration of the body region are both light doping concentrations; a doping concentration of the source region and a doping concentration of the drain region are both heavy doping concentrations.
4. The LDMOS device of claim 1, wherein: the radiation-hardened buffer region and the body region are formed by the same process.
5. The LDMOS device of claim 1, wherein: a width of the radiation-hardened buffer region is between 0.1um and 1um.
6. The LDMOS device of any one of claims 1 to 5, wherein: the source-drain implant region comprises a first sub-implant region surrounding the source region and a second sub-implant region surrounding the drain region; and wherein the first sub-implant region is connected to the second sub-implant region; the first sub-implant region comprises a first edge along a gate width direction, a second edge along the gate width direction, and a third edge along a gate length direction, and wherein a projection of the first edge and the second edge on the surface of the substrate extends into a projection of the gate electrode on the surface of the substrate.
7. The LDMOS device of claim 6, wherein: a distance d1, at which the projection of the first edge and the second edge on the surface of the substrate extends into the projection of the gate electrode on the surface of the substrate, satisfies the following condition: 10 < d1 < 100nm.
8. The LDMOS device of any one of claims 1 to 4, wherein: the isolation region is a dielectric isolation.
9. The LDMOS device of any one of claims 1 to 4, wherein, Further comprising: a lightly doped drain region located between the drain region and the channel region.
10. An integrated circuit, characterized by Comprising at least one LDMOS device as claimed in any one of claims 1 to 9.