Pre-voltage-stabilizing circuit with current supplement

Abstract

The utility model provides a pre-voltage-stabilizing circuit with current supplementation, which comprises a grid voltage generating circuit, a low-voltage power supply generating circuit, a power tube switching circuit and a current supplementation circuit, and the current supplementation circuit supplements current of a first branch and / or weakens current of a second branch when the power supply voltage is higher than that of a fourth transistor in a working state. The turn-off of the third transistor is accelerated; and when the fourth transistor is turned off, the second branch current is supplemented and / or the first branch current is weakened, so that the conduction of the third transistor is accelerated. Therefore, according to the pre-voltage-stabilizing circuit with the current supplementing function, the output response speed of the power tube switching circuit is increased through the current supplementing circuit, and the problem of power failure of the output end of the low-voltage power supply generating circuit is solved.

Description

Technical Field

[0001] This utility model relates to a pre-regulatory circuit, and more specifically to a pre-regulatory circuit with current compensation. Background Technology

[0002] like Figure 1 The diagram shows a typical pre-regulator circuit, which includes a gate voltage generation circuit 101, a power transistor switching circuit 102, and a low-voltage power supply generation circuit 103.

[0003] The gate voltage generation circuit 101 includes a first current source Q1 whose negative terminal is connected to the power supply voltage VCC. The positive terminal of the first current source Q1 is grounded through a first capacitor C1, and also grounded through a first Zener diode D1 and a first transistor M1 (NMOS transistor), and is configured to output a first gate voltage Vn1. The positive terminal of the first Zener diode D1 is connected to the drain and gate of the first transistor M1, and the negative terminal is connected to the first current source Q1.

[0004] Therefore, the gate voltage generation circuit 101 is used to regulate and clamp the gate of the second transistor M2 to obtain the first gate voltage Vn1. When the system is powered on, the first capacitor C1 causes the output first gate voltage Vn1 to rise relatively smoothly, that is, the gate voltage of the second transistor M2 rises relatively smoothly. The first Zener diode D1, the first transistor M1, and the first current source Q1 jointly generate the gate voltage of the second transistor M2.

[0005] The power transistor switching circuit 102 is configured to output the gate voltage Vp1 of the corresponding third transistor M3 at its output terminal according to the first gate voltage Vn1.

[0006] The low-voltage power generation circuit 103 includes a third transistor M3 (PMOS power transistor), whose source is connected to the power supply voltage VCC, and whose gate is connected to the output terminal of the power transistor switching circuit 102 and to the power supply voltage VCC through a third Zener diode D3. Its drain is grounded through a second capacitor C2 and a second Zener diode D2, and is also connected to the source of a second transistor M2 (NMOS transistor). The gate of the second transistor M2 is connected to a first gate voltage Vn1, and its drain is connected to the power supply voltage VCC. The third Zener diode D3 is used to stabilize the gate voltage of the third transistor M3; the second Zener diode D2 is used to stabilize the output voltage VDD; and the second capacitor C2 allows the output voltage VDD to change smoothly when the system is powered on.

[0007] Based on the properties of PMOS and NMOS transistors, a rise in the gate voltage of a PMOS transistor indicates a turn-off operation, while a decrease in the gate voltage indicates a turn-on operation. Similarly, for an NMOS transistor, a rise in the gate voltage indicates a turn-on operation, and a decrease indicates a turn-off operation. A rise in gate voltage is also called a pull-up, and a decrease in gate voltage is called a pull-down. In the design of the power transistor switching circuit 102, when the power supply voltage VCC is high, the gate voltage of the third transistor M3 (PMOS power transistor) will be pulled up to the power supply voltage, turning M3 off. When the power supply voltage VCC is low, the gate voltage of the third transistor M3 will be pulled down to ground by the current in the second branch, turning M3 on.

[0008] The first gate voltage Vn1 is provided to the power transistor switching circuit 102 and also to the second transistor M2 (NMOS power transistor) in the low-voltage power generation circuit 103 as the gate voltage. The source of the second transistor M2 (NMOS power transistor) and the drain of the third transistor M3 (PMOS power transistor) are connected, and this connection is used as the output terminal of the low-voltage power generation circuit 103 to obtain the output voltage VDD.

[0009] Therefore, in the operating mode, when the power supply voltage is high, the second transistor M2 is turned on and the third transistor M3 is turned off, and the output voltage VDD can be expressed as V GS1 +V D1 -V GS2 , where V GS1 It is the voltage difference between the gate and source of the first transistor M1; V GS2 It is the voltage difference between the gate and source of the second transistor M2; V D1 This refers to the voltage difference across the first Zener diode D1. When the power supply voltage is low, the second transistor M2 is off, and the third transistor M3 is on, causing the output voltage VDD to follow the power supply voltage VCC. This achieves a low-voltage power supply VDD that follows the power supply voltage VCC (at low voltage), is relatively stable (at high voltage), and has a certain load-carrying capacity within a 2V to 10V power supply system. However, when the power supply voltage drops rapidly from a higher voltage (i.e., when the second transistor M2 is on) to a lower voltage (when M3 is on), the power transistor switching circuit 102 cannot respond quickly enough, preventing the power transistors from switching quickly. This causes VDD to fail to follow the power supply voltage change rapidly, resulting in a power outage. In other words, even when the power supply voltage VCC drops rapidly, VDD still drops rapidly due to the on state of M2, causing VDD to fall below the power supply voltage.

[0010] Considering that this pre-regulator circuit is typically used in high-voltage chip systems to generate a low-voltage power supply within the system to power subsequent low-voltage logic and low-voltage analog circuit modules, if this circuit experiences a power failure, it will cause other circuit modules to malfunction. Utility Model Content

[0011] The purpose of this invention is to provide a pre-regulatory circuit with current compensation to solve the problem of output voltage drop when the power supply is about to shut down, without contributing additional standby current.

[0012] To achieve the above objectives, this utility model provides a pre-regulatory circuit with current compensation, comprising: a gate voltage generation circuit for regulating and clamping the gate of a second transistor to obtain a first gate voltage; a low-voltage power supply generation circuit, including a second transistor and a third transistor, wherein the gate of the second transistor is connected to the first gate voltage, and the low-voltage power supply generation circuit is configured to: when the third transistor is turned on and the second transistor is turned off, make the output voltage follow the power supply voltage; and when the third transistor is turned off and the second transistor is turned on, make the output voltage correlated with the first gate voltage; and a power transistor switching circuit, which includes a fourth transistor whose gate is connected to the first gate voltage. The circuit is configured such that when the power supply voltage is high enough for the fourth transistor to turn on, the gate voltage of the third transistor is pulled up to the power supply voltage to turn off; when the fourth transistor is turned off, the gate voltage of the third transistor is pulled down to ground to turn on. The current compensation circuit is configured to: in the operating state, when the power supply voltage is high enough for the fourth transistor to turn on, supplement the first branch current and / or reduce the second branch current to accelerate the turn-off of the third transistor; when the fourth transistor is turned off, supplement the second branch current and / or reduce the first branch current to accelerate the turn-on of the third transistor; wherein both the first branch current and the second branch current are electrically connected to the gate of the third transistor.

[0013] The current compensation circuit is also configured to turn off when the externally input standby signal is high, in order to avoid standby power consumption.

[0014] The current compensation circuit includes a seventh transistor and an eighth transistor with a common gate. The drain of the seventh transistor is the first output terminal of the current compensation circuit, and the source of the seventh transistor is connected to the drain of the ninth transistor, the source of the ninth transistor is grounded. The drain of the eighth transistor is the second output terminal of the current compensation circuit, and the source of the eighth transistor is connected to the drain of the tenth transistor, the source of the tenth transistor is grounded.

[0015] The standby signal is connected to the gates of the seventh and eighth transistors, and the gates of the eleventh, twelfth, and thirteenth transistors via an inverter, and is also directly connected to the gates of the fifteenth and eighteenth transistors; the power supply voltage is connected to the drain of the eleventh transistor via a first resistor, to the drain of the twelfth transistor via a fifth Zener diode, and to the drain of the thirteenth transistor via a second resistor; the gate voltage of the tenth transistor is connected to the source of the eleventh transistor, the drain of the fourteenth transistor, the drain of the fifteenth transistor, the drain of the sixteenth transistor, and the gate of the seventeenth transistor, and the sources of the fourteenth, fifteenth, sixteenth, seventeenth, and eighteenth transistors are grounded; the gate voltage of the ninth transistor is connected to the source of the thirteenth transistor, the drain of the seventeenth transistor, and the drain of the eighteenth transistor; the gate of the fourteenth transistor is connected to the drain and gate of the first transistor in the gate voltage generation circuit to receive the gate voltage of the first transistor; the gate of the sixteenth transistor is connected to the source of the twelfth transistor and grounded via a third resistor.

[0016] The gate voltage generation circuit includes a first current source, the negative terminal of which is connected to the power supply voltage; the positive terminal of the first current source is grounded through a first capacitor, grounded through a first Zener diode and a first transistor, and is configured to output a first gate voltage; the positive terminal of the first Zener diode is connected to the drain and gate of the first transistor, and the negative terminal is connected to the first current source.

[0017] The source of the third transistor is connected to the power supply voltage, the gate is connected to the power transistor switching circuit and is connected to the power supply voltage through the third Zener diode, and its source is grounded through the second capacitor and the second Zener diode, and is connected to the source of the second transistor; the gate of the second transistor is connected to the first gate voltage, and the drain is connected to the power supply voltage.

[0018] The first gate voltage is connected to the gate of the fourth transistor. The source of the fourth transistor is grounded through the second current source and connected to the first output terminal of the current compensation circuit to receive the first compensation current. The drain of the fourth transistor is connected to the gate and drain of the fifth transistor. The fifth transistor and the sixth transistor form a first current mirror. The drain of the sixth transistor is connected to the gate voltage of the third transistor, connected to the second output terminal of the current compensation circuit to receive the second compensation current, and connected to the third current source.

[0019] The pre-regulator circuit with current compensation of this invention employs a current compensation circuit that supplements the current in the first branch or weakens the current in the second branch when the power supply voltage is high, thereby accelerating the turn-off of the third transistor; and supplements the current in the second branch or weakens the current in the first branch when the power supply voltage is low, thereby accelerating the turn-on of the third transistor. This achieves the goal of accelerating the switching speed of the power transistor when the power supply voltage rapidly drops from a higher voltage to a lower voltage. Furthermore, in standby mode, with Sleep high, the current compensation circuit is turned off, thus not contributing additional standby power consumption.

[0020] In summary, the pre-regulatory circuit with current compensation of this utility model not only solves the problem of output voltage drop when the power supply is fast off, but also does not contribute additional standby current. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of a typical pre-regulator circuit.

[0022] Figure 2 This is a structural block diagram of the pre-regulated circuit with current compensation according to this utility model;

[0023] Figure 3 This is a circuit diagram of a pre-regulatory circuit with current compensation according to an embodiment of the present invention.

[0024] Figure 4 This is a circuit diagram of the current compensation circuit of the pre-stabilized voltage circuit with current compensation of this utility model. Detailed Implementation

[0025] The preferred embodiments of this utility model are given below with reference to the accompanying drawings and described in detail.

[0026] like Figure 2 and Figure 3 The diagram shows a pre-regulated voltage circuit with current compensation according to an embodiment of the present invention, which includes a gate voltage generation circuit 101, a power transistor switching circuit 102 connected to the gate voltage generation circuit 101, a low-voltage power supply generation circuit 103 connected to both the gate voltage generation circuit 101 and the power transistor switching circuit 102, and a current compensation circuit 104 connected to the power transistor switching circuit 102.

[0027] The circuit structures of the gate voltage generation circuit 101, the power transistor switching circuit 102, and the low-voltage power generation circuit 103 are completely identical to those of the gate voltage generation circuit 101, the power transistor switching circuit 102, and the low-voltage power generation circuit 103 in the prior art pre-regulatory circuit.

[0028] Specifically, the gate voltage generation circuit 101 includes a first current source Q1, the negative terminal of which is connected to the power supply voltage VCC; the positive terminal of the first current source Q1 is grounded through a first capacitor C1, and also grounded through a first Zener diode D1 and a first transistor M1 (NMOS transistor), and is configured to output a first gate voltage Vn1. The positive terminal of the first Zener diode D1 is connected to the drain and gate of the first transistor M1, and the negative terminal is connected to the first current source Q1.

[0029] Therefore, the gate voltage generation circuit 101 is used to regulate and clamp the gate of the second transistor M2 to obtain the first gate voltage Vn1. When the system is powered on, the first capacitor C1 causes the output first gate voltage Vn1 to rise relatively smoothly, that is, the gate voltage of the second transistor M2 rises relatively smoothly. The first Zener diode D1, the first transistor M1, and the first current source Q1 jointly generate the gate voltage of the second transistor M2.

[0030] The low-voltage power generation circuit 103 includes a second transistor M2 (NMOS transistor) and a third transistor M3 (PMOS power transistor). The gate of the second transistor M2 is connected to a first gate voltage Vn1, and the gate of the third transistor M3 is connected to the first gate voltage Vn1 through a power transistor switching circuit 102. Specifically, the source of the third transistor M3 (PMOS power transistor) is connected to the power supply voltage VCC, and its gate is connected to the power transistor switching circuit 102 (to receive the gate voltage Vp1 of the third transistor M3) and is connected to the power supply voltage VCC through a third Zener diode D3. Its source is grounded through a second capacitor C2 and grounded through the second Zener diode D2, and is also connected to the source of the second transistor M2. The gate of the second transistor M2 is connected to the first gate voltage Vn1, and its drain is connected to the power supply voltage VCC. The third Zener diode D3 is used to stabilize the gate voltage of the third transistor M3; the second Zener diode D2 is used to stabilize the output voltage VDD; and the second capacitor C2 enables the output voltage VDD to change smoothly when the system is powered on.

[0031] Therefore, the second transistor M2 and the third transistor M3 in the low-voltage power generation circuit 103 jointly determine the output voltage VDD. The low-voltage power generation circuit 103 is configured such that when the third transistor M3 is on and the second transistor M2 is off, the output voltage VDD follows the power supply voltage VCC. When the third transistor M3 is off and the second transistor M2 is on, the output voltage VDD is related to the first gate voltage Vn1. Specifically, the output voltage VDD is represented as Vn1. GS1 +V D1 -V GS2 , where V GS1 It is the voltage difference between the gate and source of the first transistor M1; V GS2 It is the voltage difference between the gate and source of the second transistor M2; V D1It is the voltage difference across the first Zener diode D1.

[0032] The input terminal of the power transistor switching circuit 102 is connected to the first gate voltage Vn1, and its output terminal is connected to the gate voltage Vp1 of the third transistor M3.

[0033] The power transistor switching circuit 102 includes a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a second current source Q2, and a third current source Q3. The first gate voltage Vn1 is connected to the gate of the fourth transistor M4. The source of the fourth transistor M4 is grounded through the second current source Q2 and connected to the first output terminal of the current compensation circuit 104 to receive a first compensation current Ib1. The drain of the fourth transistor M4 is connected to the gate and drain of the fifth transistor M5. The fifth transistor M5 and the sixth transistor M6 form a first current mirror. The drain of the sixth transistor M6 is connected to the gate voltage Vp1 of the third transistor M3, connected to the second output terminal of the current compensation circuit 104 to receive a second compensation current Ib2, and connected to the third current source Q3.

[0034] Therefore, the fourth transistor M4 is an NMOS transistor, functioning as a transistor, primarily used to control the switching on and off of the branch containing the fifth transistor M5; the replication current ratio of the first current mirror is N times. When the power supply voltage VCC is high, i.e., the first gate voltage Vn1 minus the source voltage Vs4 of the fourth transistor M4 is greater than the threshold voltage vth4 of the fourth transistor M4 (i.e., the power supply voltage is high enough for the fourth transistor M4 to conduct), the first branch current I1 obtained by the current mirror replication of the sixth transistor M6 is greater than the second branch current I2, and the gate voltage Vp1 of the third transistor M3 is pulled up to the power supply voltage VCC; when the power supply voltage VCC is low, i.e., the first gate voltage Vn1 minus the source voltage Vs4 of the fourth transistor M4 is less than the threshold voltage vth4 of the fourth transistor M4 (the fourth transistor M4 is off), the first branch current I1 obtained by the current mirror replication of the sixth transistor M6 is less than the second branch current I2, and the gate voltage of the third transistor M3 is pulled down to ground. Here, Vs4 and vth4 are the source voltage and threshold voltage of the fourth transistor M4, respectively.

[0035] In addition, the gates of the fifth transistor M5 and the sixth transistor M6 are connected to the power supply voltage VCC through the fourth Zener diode D4 to stabilize the gate voltage of the fifth transistor M5 and the sixth transistor M6; the second current source Q2 and the third current source Q3 are used to provide current.

[0036] The current compensation circuit 104 is configured to: in the operating state, when the power supply voltage VCC is high enough that the fourth transistor M4 is turned on, compensate for the first branch current I1 and / or reduce the second branch current I2, thereby accelerating the turn-off of the third transistor M3; when the power supply voltage is low enough that the fourth transistor M4 is turned off, compensate for the second branch current I2 and / or reduce the first branch current I1, thereby accelerating the turn-on of the third transistor M3; thus achieving the purpose of accelerating the switching speed of the power transistors when the power supply voltage drops quickly from a higher voltage (the second transistor M2 of the NMOS is turned on) to a lower voltage (the third transistor M3 of the PMOS is turned on). The first and second compensation currents of the current compensation circuit 104 change accordingly with the change of the power supply voltage, thereby dynamically adjusting the response speed of the power transistor switching circuit 102.

[0037] In addition, the current compensation circuit 104 can also be configured to be turned off in standby mode (i.e., when the externally input standby signal Sleep is high), so as not to contribute additional standby power consumption.

[0038] Therefore, the advantage of the pre-stabilized voltage circuit with current compensation of this utility model is that after adding the current compensation circuit 104, it not only solves the problem of output voltage drop when the power supply is fast off, but also does not contribute additional standby current.

[0039] like Figure 3 and Figure 4 As shown, the current compensation circuit 104 includes a seventh transistor M7 and an eighth transistor M8 configured with a common gate CL. The drain of the seventh transistor M7 is the first output terminal of the current compensation circuit 104, and the source of the seventh transistor M7 is connected to the drain of the ninth transistor M9, the source of the ninth transistor M9 being grounded. The drain of the eighth transistor M8 is the second output terminal of the current compensation circuit 104, and the source of the eighth transistor M8 is connected to the drain of the tenth transistor M10, the source of the tenth transistor M10 being grounded. The gate voltage of the tenth transistor M10 is mm, and the gate voltage of the ninth transistor M9 is nn.

[0040] Among them, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 are all NMOS transistors.

[0041] Therefore, the first branch current I1 = IS6, where IS6 is the current flowing through the sixth transistor M6; the second branch current I2 = IQ3 + Ib2, where IQ3 is the current provided by the third current source Q3, and Ib2 is the current flowing through the eighth transistor M8.

[0042] like Figure 4As shown, the current compensation circuit 104 is connected to a standby signal Sleep. Specifically, the standby signal Sleep is connected to the gates CL of the seventh transistor M7 and the eighth transistor M8, as well as the gates of the eleventh transistor M11, the twelfth transistor M12, and the thirteenth transistor M13, via an inverter INV1. Furthermore, the standby signal Sleep is directly connected to the gates of the fifteenth transistor M15 and the eighteenth transistor M18. Therefore, in operating mode, the standby signal Sleep is low, and the gates CL of the seventh transistor M7 and the eighth transistor M8 are high; in standby mode, the standby signal Sleep is high, and the gates CL of the seventh transistor M7 and the eighth transistor M8 are low.

[0043] The current compensation circuit 104 is connected to the power supply voltage VCC. The power supply voltage VCC is connected to the drain of the eleventh transistor M11 through the first resistor R1, to the drain of the twelfth transistor M12 through the fifth Zener diode D5, and to the drain of the thirteenth transistor M13 through the second resistor R2.

[0044] The gate voltage mm of the tenth transistor M10 is connected to the source of the eleventh transistor M11, the drain of the fourteenth transistor M14, the drain of the fifteenth transistor M15, the drain of the sixteenth transistor M16, and the gate of the seventeenth transistor M17. The sources of the fourteenth transistor M14, the fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17, and the eighteenth transistor M18 are grounded. Therefore, the current flowing through the eleventh transistor M11 is the first gate branch current Ia1 of the tenth transistor, and the current flowing through the fourteenth transistor is the second gate branch current Ia2 of the tenth transistor. Both the first gate branch current Ia1 and the second gate branch current Ia2 of the tenth transistor are connected to the gate voltage mm of the tenth transistor M10, thus affecting the gate voltage mm of the tenth transistor M10.

[0045] The gate voltage nn of the ninth transistor M9 is connected to the source of the thirteenth transistor M13, the drain of the seventeenth transistor M17, and the drain of the eighteenth transistor M18.

[0046] The gate of the fourteenth transistor M14 is connected to the drain and gate of the first transistor M1 in the gate voltage generation circuit 101 to receive the gate voltage Vb1 of the first transistor. The gate of the sixteenth transistor M16 is connected to the source of the twelfth transistor M12 and grounded through the third resistor R3.

[0047] In this embodiment, the first transistor M10 to the eighteenth transistor M18 are all NMOS transistors.

[0048] The second transistor M2 and the third transistor M3 in the low-voltage power supply generation circuit 103 jointly determine the output voltage VDD. Considering the device characteristics and structure selection of NMOS and PMOS, when the power supply voltage VCC is high, it is necessary to accelerate the turn-on of the second transistor M2 (i.e., the NMOS transistor) and the turn-off of the third transistor M3 (i.e., the PMOS transistor). That is, it is necessary to supplement the first branch current I1 or reduce the second branch current I2 to accelerate the turn-off of the third transistor M3. The first branch current I1 and the second branch current I2 are both electrically connected to the third transistor M3.

[0049] Therefore, the current compensation circuit 104 is configured as follows: In the operating mode, when the power supply voltage VCC is high, the fourteenth transistor M14 is turned on, and the second gate branch current Ia2 of the tenth transistor in the current compensation circuit 104 is greater than the first gate branch current Ia1 of the tenth transistor, causing the gate voltage mm of the tenth transistor to be pulled down to ground, and the tenth transistor M10 to be turned off, which weakens the second compensation current Ib2 flowing through the eighth transistor M8, and thus weakens the second branch current I2; at the same time, the gate voltage mm of the tenth transistor being pulled down to ground causes the seventeenth transistor M17 to be turned off, which makes the second gate current Ia4 of the ninth transistor less than the first gate current Ia3 of the ninth transistor, and causes the gate voltage nn of the ninth transistor M9 to be pulled up to VCC-V R2 -V DS13 , where V R2 V is the voltage difference across the second resistor R2. DS13 Because of the voltage difference between the source and drain of the thirteenth transistor M13, the ninth transistor M9 turns on, thereby increasing the first supplementary current Ib1 flowing through the seventh transistor M7, which in turn increases the first branch current I1. The first branch current I1 is N times the sum of the first supplementary current Ib1 and the current of the second current mirror Q2; therefore, the increase in the first supplementary current Ib1 increases the value of the first branch current I1. Similarly, the second branch current I2 is provided by the third current source Q3. Therefore, the gate voltage Vp1 of the third transistor M3 is pulled up to the power supply voltage, thus accelerating the turn-off of the third transistor M3. At this time, the output voltage VDD is determined by the second transistor M2, and the output voltage VDD can be expressed as V... GS1 +V D1 -V GS2 , where V GS1 It is the voltage difference between the gate and source of the first transistor M1; V GS2 It is the voltage difference between the gate and source of the second transistor M2; V D1 It is the voltage difference across the first Zener diode D1.

[0050] In this embodiment, the size of the fourteenth transistor M14 is made large, or the size of the first resistor R1 is made appropriately small, so that when the fourteenth transistor M14 is turned on, the second gate branch current Ia2 of the tenth transistor is greater than the first gate branch current Ia1 of the tenth transistor.

[0051] When the power supply voltage VCC is low, it is necessary to speed up the turn-off of the second transistor M2 (i.e., NMOS transistor) and the turn-on of the third transistor M3 (i.e., PMOS transistor). Therefore, it is necessary to supplement the second branch current I2 or reduce the first branch current I1 to speed up the turn-on of the third transistor M3.

[0052] Therefore, the current compensation circuit 104 is configured as follows: In the operating mode, when the power supply voltage VCC is low, the gate voltage Vb1 received by the gate of the fourteenth transistor M14 is very small, so the fourteenth transistor M14 is turned off; the second gate branch current Ia2 of the tenth transistor is less than the first gate branch current Ia1 of the tenth transistor, which increases the gate voltage mm of the tenth transistor M10, turning on the tenth transistor M10. This increases the second compensation current Ib2 flowing through the eighth transistor M8, and further increases the second branch current I2. The gate voltage Vp1 of the third transistor M3 is pulled down to ground more quickly, thus accelerating the turn-on of the third transistor M3. At the same time, the increase in the gate voltage mm of the tenth transistor M10 turns on the seventeenth transistor M17, making the second gate current Ia4 of the ninth transistor greater than the first gate current Ia3 of the ninth transistor, causing the gate voltage nn of the ninth transistor M9 to be pulled down to ground, and the ninth transistor M9 is turned off. The gate voltage mm of the tenth transistor M10 controls its on / off state, and the gate voltage nn of the ninth transistor M9 controls its on / off state. Therefore, at this time, the tenth transistor M10 is on, and the ninth transistor M9 is off. This reduces the first supplementary current Ib1, causing the first branch current I1 to decrease, thus accelerating the conduction of the third transistor M3. The first branch current I1 is N times the current provided by the second current source Q2; the second branch current I2 is the sum of the current provided by the third current source Q3 and the second supplementary current Ib2 (i.e., the current flowing through the eighth transistor M8 and the tenth transistor M10). Therefore, the first branch current I1 is less than the second branch current I2. Consequently, the gate voltage Vp1 of the third transistor M3 is pulled down to ground, the third transistor M3 conducts, and the second transistor M2 is off. At this time, the third transistor M3 determines the output voltage VDD, making the output voltage VDD follow the power supply voltage VCC.

[0053] Furthermore, in operating mode, when the power supply voltage rapidly decreases from a higher voltage (M2 on, M3 off) to a lower voltage (M3 on, M2 off), the gate voltage Vb1 of the first transistor received by the gate of the fourteenth transistor M14 changes from high to low, the gate voltage mm of the tenth transistor M10 changes from low to high accordingly, and the gate voltage nn of the ninth transistor M9 also changes from high to low. The gate voltage of the sixteenth transistor M16 changes from high to low, weakening its pull-down capability for the seventeenth transistor M17. The first branch current I1 is N times the sum of the first compensation current Ib1 (i.e., the current flowing through M7 and M9) and the current provided by the second current source Q2. The first compensation current Ib1 gradually decreases to 0, and its pull-up capability for the third transistor M3 gradually weakens. The second branch current I2 is the sum of the current provided by the third current source Q3 and the second compensation current Ib2 (i.e., the current flowing through M8 and M10). The second compensation current Ib2 gradually increases, and its pull-down capability for the third transistor M3 gradually strengthens. This accelerates the pull-down of the gate of the third transistor M3 to ground, and the third transistor M3 quickly turns on, improving the speed at which the output voltage VDD switches to follow the power supply voltage VCC, thus solving the power-down problem at the output end.

[0054] In standby mode, the standby signal Sleep is high, and the inverted signal obtained by the inverter INV1 is low. Therefore, the seventh transistor M7, the eighth transistor M8, the eleventh transistor M11, the twelfth transistor M12, and the thirteenth transistor M13 are all turned off. The gate voltage mm of the tenth transistor M10 is pulled down to ground, and the tenth transistor M10 and the seventeenth transistor M17 are turned off. The eighteenth transistor M18 is turned on, the gate voltage nn of the ninth transistor M9 is pulled down to ground, and the ninth transistor M9 is turned off. The current compensation circuit does not work, so no additional standby current is introduced.

[0055] It should be noted that this utility model has been described in detail according to its specific embodiments. However, various modifications and variations can be made around this idea without departing from the spirit and scope of this utility model, and these modifications and variations are also considered to be within the protection scope of this utility model.

Claims

1. A pre-regulated voltage circuit with current compensation, characterized in that, include: The gate voltage generation circuit is used to regulate and clamp the gate of the second transistor to obtain the first gate voltage; A low-voltage power generation circuit includes a second transistor and a third transistor. The gate of the second transistor is connected to a first gate voltage. The low-voltage power generation circuit is configured to: when the third transistor is turned on and the second transistor is turned off, make the output voltage follow the power supply voltage; and when the third transistor is turned off and the second transistor is turned on, make the output voltage correlated with the first gate voltage. A power transistor switching circuit includes a fourth transistor whose gate is connected to a first gate voltage; configured to pull up the gate voltage of a third transistor to the power supply voltage to achieve turn-off when the power supply voltage is high enough for the fourth transistor to be turned on; and to pull down the gate voltage of the third transistor to ground to achieve turn-on when the fourth transistor is turned off. The current compensation circuit is configured to: in the working state, when the power supply voltage is high enough to turn on the fourth transistor, compensate for the current in the first branch and / or reduce the current in the second branch to accelerate the turn-off of the third transistor; When the fourth transistor is turned off, the second branch current is supplemented and / or the first branch current is reduced to accelerate the turn-on of the third transistor; wherein, both the first branch current and the second branch current are electrically connected to the gate of the third transistor.

2. The pre-regulated circuit with current compensation according to claim 1, characterized in that, The current compensation circuit is also configured to turn off when the externally input standby signal is high, in order to avoid standby power consumption.

3. The pre-regulated circuit with current compensation according to claim 2, characterized in that, The current compensation circuit includes a seventh transistor and an eighth transistor with a common gate. The drain of the seventh transistor is the first output terminal of the current compensation circuit, and the source of the seventh transistor is connected to the drain of the ninth transistor, the source of the ninth transistor is grounded. The drain of the eighth transistor is the second output terminal of the current compensation circuit, and the source of the eighth transistor is connected to the drain of the tenth transistor, the source of the tenth transistor is grounded.

4. The pre-regulatory circuit with current compensation according to claim 3, characterized in that, The standby signal is connected to the gates of the seventh and eighth transistors, as well as the gates of the eleventh, twelfth and thirteenth transistors, via an inverter, and is directly connected to the gates of the fifteenth and eighteenth transistors. The power supply voltage is connected to the drain of the eleventh transistor through the first resistor, to the drain of the twelfth transistor through the fifth Zener diode, and to the drain of the thirteenth transistor through the second resistor. The gate voltage of the tenth transistor is connected to the source of the eleventh transistor, the drain of the fourteenth transistor, the drain of the fifteenth transistor, the drain of the sixteenth transistor, and the gate of the seventeenth transistor, and the source of the fourteenth transistor, the source of the fifteenth transistor, the source of the sixteenth transistor, the source of the seventeenth transistor, and the source of the eighteenth transistor are grounded. The gate voltage of the ninth transistor is connected to the source of the thirteenth transistor, the drain of the seventeenth transistor, and the drain of the eighteenth transistor. The gate of the fourteenth transistor is connected to the drain and gate of the first transistor in the gate voltage generation circuit to receive the gate voltage of the first transistor; the gate of the sixteenth transistor is connected to the source of the twelfth transistor and grounded through a third resistor.

5. The pre-regulated voltage circuit with current compensation according to claim 1, characterized in that, The gate voltage generation circuit includes a first current source, the negative terminal of which is connected to the power supply voltage; the positive terminal of the first current source is grounded through a first capacitor, grounded through a first Zener diode and a first transistor, and is configured to output a first gate voltage; the positive terminal of the first Zener diode is connected to the drain and gate of the first transistor, and the negative terminal is connected to the first current source.

6. The pre-regulated circuit with current compensation according to claim 1, characterized in that, The source of the third transistor is connected to the power supply voltage, the gate is connected to the power transistor switching circuit and is connected to the power supply voltage through the third Zener diode, and its source is grounded through the second capacitor and the second Zener diode, and is connected to the source of the second transistor; the gate of the second transistor is connected to the first gate voltage, and the drain is connected to the power supply voltage.

7. The pre-regulated voltage circuit with current compensation according to claim 1, characterized in that, The first gate voltage is connected to the gate of the fourth transistor. The source of the fourth transistor is grounded through the second current source and connected to the first output terminal of the current compensation circuit to receive the first compensation current. The drain of the fourth transistor is connected to the gate and drain of the fifth transistor. The fifth transistor and the sixth transistor form a first current mirror. The drain of the sixth transistor is connected to the gate voltage of the third transistor, connected to the second output terminal of the current compensation circuit to receive the second compensation current, and connected to the third current source.

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