Ultrasonic flowmeter control system
By introducing a multi-channel drive module into the ultrasonic flow meter control system, the problem of low efficiency of the single-channel drive module is solved, synchronous signal processing and accurate flow measurement are achieved, and the real-time response capability of the system is improved.
Patent Information
- Application Number
- CN202520603306.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-01
- Publication Date
- 2026-01-13
- Estimated Expiration
- 2035-04-01
AI Technical Summary
Existing ultrasonic flow meters typically use a single-channel drive module, which leads to low efficiency in certain application scenarios.
An ultrasonic flowmeter control system was designed, including an isolated DC-DC module, a DC voltage divider module, an FPGA module, a drive module, a transducer, a digital potentiometer, a digital isolator, and an ADC acquisition active filter module. The drive module contains multiple channels, and upstream and downstream signals are acquired and processed synchronously through the multi-channel drive module.
It enables synchronous processing of multiple signals, reduces time offset and signal interference, ensures the accuracy of flow rate and flow measurement, and improves the real-time response capability of the system, making it particularly suitable for high-frequency or dynamically changing measurement scenarios.
Smart Images
Figure CN223796857U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of flow meter technology, and more specifically, to an ultrasonic flow meter control system. Background Technology
[0002] An ultrasonic flow meter is a type of flow meter developed based on the principle that the propagation speed of ultrasonic waves in a flowing medium is equal to the vector sum of the average flow velocity of the measured medium and the velocity of the sound wave in a stationary medium. It mainly consists of a transducer and a converter, and there are different types such as Doppler method, velocity difference method, beam deflection method, noise method and correlation method.
[0003] However, the drive module of existing ultrasonic flow meters is generally single-channel, meaning that only one ultrasonic transducer can be driven at a time. This may impose limitations in certain applications, resulting in low operational efficiency. Utility Model Content
[0004] The purpose of this invention is to provide an ultrasonic flow meter control system to solve the problem that the drive module in the prior art is a single channel.
[0005] This utility model is achieved through the following technical solution:
[0006] An ultrasonic flow meter control system includes an isolated DC-DC module, a DC voltage divider module, an FPGA module, a drive module, a transducer, a digital potentiometer, a digital isolator, and an ADC acquisition active filter module, wherein the drive module includes several channels;
[0007] The isolated DC-DC module is connected to the DC voltage divider module, and the DC voltage divider module is connected to the FPGA module, the driver module, the transducer, the digital potentiometer, the digital isolator, and the ADC acquisition active filter module.
[0008] The FPGA module is connected to the driver module, digital potentiometer, digital isolator and ADC acquisition active filter module respectively, and the other end of the driver module is connected to the transducer.
[0009] Preferably, the driving module includes a first driving channel and a second driving channel, wherein the first driving channel is connected to the second driving channel.
[0010] Preferably, the first driving channel includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first capacitor, a second capacitor, a third capacitor, a first MOSFET, and a first diode;
[0011] One end of the first resistor and one end of the third resistor are simultaneously connected to one end of the first MOSFET. One end of the second resistor and one end of the first capacitor are simultaneously connected to one end of the first MOSFET. The other end of the first capacitor is connected to the first diode. The other end of the first diode is connected to the second capacitor. The second capacitor, the fourth resistor, the fifth resistor, and the third capacitor are connected in series in sequence.
[0012] Preferably, the second driving channel includes a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a second MOSFET, and a second diode;
[0013] One end of the sixth resistor and the eighth resistor are simultaneously connected to one end of the second MOSFET. One end of the seventh resistor and the sixth capacitor are simultaneously connected to one end of the second MOSFET. The other end of the fourth capacitor is connected to the second diode. The other end of the second diode is connected to the fifth capacitor. The fifth capacitor, the ninth resistor, the tenth resistor, and the sixth capacitor are connected in series in sequence.
[0014] Preferably, the ADC acquisition active filter module includes an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, an operational amplifier unit, and a relay;
[0015] The eleventh, twelfth, and thirteenth resistors are connected to the digital potentiometer. Both ends of the seventh capacitor are connected to the digital potentiometer. The eighth capacitor is connected to the fourteenth resistor. The other end of the fourteenth resistor is connected to the operational amplifier unit and the digital potentiometer. The ninth capacitor is connected to the fifteenth resistor. The fifteenth resistor is connected to the operational amplifier unit. One end of the operational amplifier unit is connected to the digital potentiometer. The relay and the tenth capacitor are both connected to one end of the operational amplifier unit.
[0016] Preferably, the driving module uses a 2.5µs pulse width, so that the transducer resonates at its own resonant frequency.
[0017] Preferably, the ADC acquisition active filtering module further includes a low-noise operational amplifier unit.
[0018] Preferably, one end of the low-noise operational amplifier unit is connected to a first-order high-pass filter, and the other end is connected to a first-order low-pass filter.
[0019] The technical solution of this utility model has at least the following advantages and beneficial effects:
[0020] The structure described above mainly includes an isolated DC-DC module, a DC voltage divider module, an FPGA module, a driver module, a transducer, a digital potentiometer, a digital isolator, and an ADC acquisition active filter module. The driver module includes several channels. This structure, employing a multi-channel driver module, allows for the simultaneous acquisition of upstream and downstream signals. By synchronously processing multiple signals, time offset and signal interference are reduced, ensuring the accuracy of flow velocity and flow rate measurements. Furthermore, it enables parallel processing of multiple signals, reducing processing latency and improving the system's real-time response capability, making it particularly suitable for high-frequency or dynamically changing measurement scenarios. Attached Figure Description
[0021] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this utility model and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0022] Figure 1 This is a schematic diagram of the overall connection structure of this utility model;
[0023] Figure 2 This is a schematic diagram of the drive module of this utility model;
[0024] Figure 3 This is a schematic diagram of the active filter module for ADC acquisition of this utility model.
[0025] Icons: R6 - First resistor, R7 - Second resistor, R45 - Third resistor, R5 - Fourth resistor, R4 - Fifth resistor, R51 - Sixth resistor, R52 - Seventh resistor, R50 - Eighth resistor, R9 - Ninth resistor, R48 - Tenth resistor, R1 - Eleventh resistor, R2 - Twelfth resistor, R3 - Thirteenth resistor, R49 - Fourteenth resistor, R8 - Fifteenth resistor, C2 - First capacitor, C1 - Second capacitor, C82 - Third capacitor, C5 - Fourth capacitor, C4 - Fifth capacitor, C83 - Sixth capacitor, C3 - Seventh capacitor, C81 - Eighth capacitor, C48 - Ninth capacitor, C79 - Tenth capacitor, Q2 - First MOSFET, Q3 - Second MOSFET, D1 - First diode, D2 - Second diode, U2 - Operational amplifier unit, U1 - Digital potentiometer, L1 - Relay. Detailed Implementation
[0026] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. The components of the embodiments of this utility model described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0027] Please refer to Figures 1-3 An ultrasonic flow meter control system includes an isolated DC-DC module, a DC voltage divider module, an FPGA module, a drive module, a transducer, a digital potentiometer U1, a digital isolator, and an ADC acquisition active filter module. The drive module includes several channels.
[0028] The isolated DC-DC module is connected to the DC voltage divider module, which in turn is connected to the FPGA module, driver module, transducer, digital potentiometer U1, digital isolator, and ADC acquisition active filter module.
[0029] The FPGA module is connected to the driver module, digital potentiometer U1, digital isolator and ADC acquisition active filter module respectively, and the other end of the driver module is connected to the transducer.
[0030] The structure described above mainly includes an isolated DC-DC module, a DC voltage divider module, an FPGA module, a driver module, a transducer, a digital potentiometer U1, a digital isolator, and an ADC acquisition active filter module. The driver module includes several channels. This structure, employing a multi-channel driver module, allows for the simultaneous acquisition of upstream and downstream signals. By synchronously processing multiple signals, time offset and signal interference are reduced, ensuring the accuracy of flow velocity and flow rate measurements. Furthermore, it enables parallel processing of multiple signals, reducing processing latency and improving the system's real-time response capability, making it particularly suitable for high-frequency or dynamically changing measurement scenarios.
[0031] Specifically, after the product is supplied with 24V power, the power is divided by each power IC to distribute the power required by each module.
[0032] The FPGA's IO channel generates a 3.3V, 2.5µs pulse width drive signal to the drive module's channel. The drive module then uses the channel's NMOS transistor to convert the 3.3V drive signal into a 20V drive signal to drive the transducer in that channel.
[0033] The transducer is excited by an electrical signal and generates mechanical vibration, which transmits sound wave signals. The sound wave signals travel through the liquid in the pipe to the transducer at the other end.
[0034] The other channel transducer generates an electrical signal after being subjected to mechanical vibration. The electrical signal is amplified by the PGA and OPA, filtered by the active filter, and then sent to the ADC conversion module.
[0035] The ADC is controlled by the FPGA and uses 10MHz, 10-bit sampling to convert analog signals into digital signals and transmit them to the FPGA.
[0036] The FPGA repeats the above process to drive another channel IO, receiving the echo signal returned from the transducer in the opposite direction.
[0037] Because there is flowing liquid inside the pipe, sound wave signals from different directions have different reception times, which is the time difference caused by the flow velocity of the liquid inside the pipe.
[0038] The liquid flow rate is calculated and accumulated by comparing the echoes from two channels using relevant algorithms. The FPGA displays the flow rate and volume on the screen. The screen allows for FPGA settings via buttons, enabling the modification of various parameters such as calibration values, flow rate zeroing, and analog output.
[0039] While displaying information on the screen, the FPGA uses other analog, digital, and pulse outputs to output flow rate and volume. The pulse input can be connected to an external low level. Through the pulse input module, the FPGA senses changes in the external level and resets the flow rate to zero.
[0040] In one exemplary embodiment of this invention, the isolated DC-DC module is used to provide electrical isolation from reverse connection, surge protection, and external input voltage. Commonly used internal components include the DSS210 for reverse protection (100V reverse breakdown voltage) and the SMF30CA for surge protection, certified by a third-party proximity switch for surge protection. It features a dual-channel 20V output: one channel for analog output and the internal digital power supply of the digital output IC, and one channel for the digital power supply of the control circuit.
[0041] DC voltage divider module, input (related requirements): analog output, digital output, control circuit, and drive circuit power supply requirements. Specifically, dual DC-DC-RY8411 divides the isolated DC-DC dual-channel 20V voltage to 5V, LDO-SPX3819 divides the single-channel 5V voltage to 3.3V, and LDO-BL8064CB3TR12 divides the 3.3V voltage to 1.2V.
[0042] In one exemplary embodiment of this utility model, the driving module includes a first driving channel and a second driving channel, and the first driving channel is connected to the second driving channel.
[0043] Specifically, the first driving channel includes a first resistor R6, a second resistor R7, a third resistor R45, a fourth resistor R5, a fifth resistor R4, a first capacitor C2, a second capacitor C1, a third capacitor C82, a first MOSFET Q2, and a first diode D1.
[0044] One end of the first resistor R6 and one end of the third resistor R45 are simultaneously connected to one end of the first MOSFET Q2. One end of the second resistor R7 and one end of the first capacitor C2 are simultaneously connected to one end of the first MOSFET Q2. The other end of the first capacitor C2 is connected to the first diode D1. The other end of the first diode D1 is connected to the second capacitor C1. The second capacitor C1, the fourth resistor R5, the fifth resistor R4, and the third capacitor C82 are connected in series in sequence.
[0045] Specifically, the second drive channel includes the sixth resistor R51, the seventh resistor R52, the eighth resistor R50, the ninth resistor R9, the tenth resistor R48, the fourth capacitor C5, the fifth capacitor C4, the sixth capacitor C83, the second MOSFET Q3, and the second diode D2.
[0046] One end of the sixth resistor R51 and the eighth resistor R50 are simultaneously connected to one end of the second MOSFET Q3. One end of the seventh resistor R52 and the sixth capacitor C83 are simultaneously connected to one end of the second MOSFET Q3. The other end of the fourth capacitor C5 is connected to the second diode D2. The other end of the second diode D2 is connected to the fifth capacitor C4. The fifth capacitor C4, the ninth resistor R9, the tenth resistor R48, and the sixth capacitor C83 are connected in series.
[0047] Compared to the low-voltage drive, the signal-to-noise ratio of this high-voltage drive is twice as high, as measured by an external transducer. The high-voltage drive adopts a wide pulse form with a pulse width of 2.5µs, which allows the transducer to resonate at its own resonant frequency, making it adaptable to transducers of various resonant frequencies and more versatile.
[0048] In one exemplary embodiment of this utility model, the ADC acquisition active filter module includes an eleventh resistor R1, a twelfth resistor R2, a thirteenth resistor R3, a fourteenth resistor R49, a fifteenth resistor R8, a seventh capacitor C3, an eighth capacitor C81, a ninth capacitor C48, a tenth capacitor C79, an operational amplifier unit U2, and a relay L1.
[0049] The eleventh resistor R1, the twelfth resistor R2, and the thirteenth resistor R3 are connected to the digital potentiometer U1. Both ends of the seventh capacitor C3 are connected to the digital potentiometer U1. The eighth capacitor C81 is connected to the fourteenth resistor R49. The other end of the fourteenth resistor R49 is connected to the operational amplifier unit U2 and the digital potentiometer U1. The ninth capacitor C48 is connected to the fifteenth resistor R8. The fifteenth resistor R8 is connected to the operational amplifier unit U2. One end of the operational amplifier unit U2 is connected to the digital potentiometer U1. The relay L1 and the tenth capacitor C79 are both connected to one end of the operational amplifier unit U2.
[0050] It employs a dual-channel PGA, which amplifies controllable time-domain signals and converts dual-channel inputs into single-channel signals in different time domains to reduce costs, with a maximum gain of 46dB.
[0051] A high-speed operational amplifier RS8751 is used with an external digital potentiometer U1TPL0501 as the feedback resistor for gain adjustment. The TPL0501 has a maximum resistance of 100K and an input resistance of 100R. For a 1.6M signal, a feedback resistor of 20K can achieve a maximum amplification of 46dB. However, since the higher the resistance of the digital potentiometer U1, the greater the attenuation of high-frequency signals, the maximum amplification is about 43dB.
[0052] The low-noise operational amplifier GS8721 is used as an active filter. A first-order high-pass filter with a cutoff frequency of 400K is used before the filter and a first-order low-pass filter with a cutoff frequency of 3M is used after the filter. A 1.65:1 voltage divider is added to make the output signal reach the intermediate reference of 1V for AD acquisition.
[0053] A linear regulator is used for DC bias to improve its power supply rejection ratio and increase its integration density.
[0054] The above are merely preferred embodiments of this utility model and are not intended to limit the scope of this utility model. Various modifications and variations can be made to this utility model by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this utility model should be included within the protection scope of this utility model.
Claims
1. An ultrasonic flow meter control system, characterized by, The application relates to a DC-DC isolation module, a direct-current voltage division module, an FPGA module, a driving module, a transducer, a digital potentiometer, a digital isolator and an ADC acquisition active filter module. The driving module comprises a plurality of channels. The FPGA module is connected with the driving module, the digital potentiometer, the digital isolator and the ADC acquisition active filter module.
2. The ultrasonic flow meter control system of claim 1, wherein, The other end of the driving module is connected with the transducer.
3. An ultrasonic flow meter control system according to claim 2, wherein, The driving module comprises a first driving channel and a second driving channel. The first driving channel comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first capacitor, a second capacitor, a third capacitor, a first MOS tube and a first diode.
4. The ultrasonic flow meter control system of claim 2, wherein, The first resistor and the third resistor are connected with one end of the first MOS tube, the second resistor and the first capacitor are connected with one end of the first MOS tube, the other end of the first capacitor is connected with the first diode, the other end of the first diode is connected with the second capacitor, and the second capacitor, the fourth resistor, the fifth resistor and the third capacitor are connected in sequence. The second driving channel comprises a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a second MOS tube and a second diode.
5. The ultrasonic flow meter control system of claim 1, wherein, The sixth resistor and the eighth resistor are connected with one end of the second MOS tube, the seventh resistor and the sixth capacitor are connected with one end of the second MOS tube, the other end of the fourth capacitor is connected with the second diode, the other end of the second diode is connected with the fifth capacitor, and the fifth capacitor, the ninth resistor, the tenth resistor and the sixth capacitor are connected in sequence. The ADC acquisition active filter module comprises an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, an operational amplifier unit and a relay.
6. The ultrasonic flow meter control system of claim 1, wherein, The eleventh resistor, the twelfth resistor and the thirteenth resistor are connected with the digital potentiometer, the seventh capacitor is connected with the digital potentiometer, the eighth capacitor is connected with the fourteenth resistor, the other end of the fourteenth resistor is connected with the operational amplifier unit and the digital potentiometer, the ninth capacitor is connected with the fifteenth resistor, the fifteenth resistor is connected with the operational amplifier unit, one end of the operational amplifier unit is connected with the digital potentiometer, and the relay and the tenth capacitor are connected with one end of the operational amplifier unit.
7. The ultrasonic flow meter control system of claim 1, wherein, The driving module adopts 2.5uS pulse width, so that the transducer is self-vibrated at the natural frequency thereof.
8. The ultrasonic flow meter control system of claim 7, wherein, The ADC acquisition active filter module further comprises a low-noise operational amplifier unit. One end of the low-noise operational amplifier unit is connected with a first-order high-pass filter, and the other end is connected with a first-order low-pass filter.